[llvm] a8a376c - [RISCV] Add correct predicate over FMV instructions

[Anton Sidorenko via llvm-commits]

Author: Konstantin Vladimirov
Date: 2022-12-02T13:45:57+03:00
New Revision: a8a376cbc996711c0d645e27a330c5e577d81757

URL: https://github.com/llvm/llvm-project/commit/a8a376cbc996711c0d645e27a330c5e577d81757
DIFF: https://github.com/llvm/llvm-project/commit/a8a376cbc996711c0d645e27a330c5e577d81757.diff

LOG: [RISCV] Add correct predicate over FMV instructions

Restricts FMV usage for subtargets without 'f' extension.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D139105

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoF.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index 77834159cca5..10f578d50ae5 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -370,7 +370,7 @@ defm FCVT_WU_S : FPUnaryOp_r_frm_m<0b1100000, 0b00001, XFINX, "fcvt.wu.s">,
                  Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]>;
 defm           : FPUnaryOpDynFrmAlias_m<FCVT_WU_S, "fcvt.wu.s", XFINX>;
 
-let mayRaiseFPException = 0 in
+let Predicates = [HasStdExtF], mayRaiseFPException = 0 in
 def FMV_X_W : FPUnaryOp_r<0b1110000, 0b00000, 0b000, GPR, FPR32, "fmv.x.w">,
               Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]>;
 
@@ -392,7 +392,7 @@ defm FCVT_S_WU : FPUnaryOp_r_frm_m<0b1101000, 0b00001, FXINX, "fcvt.s.wu">,
                  Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]>;
 defm           : FPUnaryOpDynFrmAlias_m<FCVT_S_WU, "fcvt.s.wu", FXINX>;
 
-let mayRaiseFPException = 0 in
+let Predicates = [HasStdExtF], mayRaiseFPException = 0 in
 def FMV_W_X : FPUnaryOp_r<0b1111000, 0b00000, 0b000, FPR32, GPR, "fmv.w.x">,
               Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]>;