[PATCH] D139169: [RISCV][WIP] Move VSPILL/VRELOAD expansion for vector tuples to eliminateFrameIndex.

[Craig Topper via Phabricator via llvm-commits]

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We need a scratch GPR to increment the base pointer for each subsequent
register. We currently reuse the input GPR for the base pointer without
declaring it as a Def of the pseudo.

We can't add it as a Def of the pseudo at creation time because it doesn't
get register allocated. This was tried in D109405 <https://reviews.llvm.org/D109405>.

Seems the only choice we have is to scavenge the GPR. This patch
moves the expansion to eliminateFrameIndex where we can create
virtual registers that will be scavenged. This also eliminates the
extra operand for passing vlenb from frame lowering to expand pseudos.

I need to do more testing on real world code, but wanted to get this
up for early review.

I hope this will fix the issue reported in D123394 <https://reviews.llvm.org/D123394>, but I haven't
checked yet.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139169

Files:
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/test/CodeGen/RISCV/rvv/undef-subreg-range.mir
  llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir
  llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

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