[PATCH] D138883: [SelectionDAG][PowerPC] Memset reuse vector element for tail store

[Ting Wang via Phabricator via llvm-commits]

tingwang added inline comments.


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Comment at: llvm/test/CodeGen/ARM/memset-align.ll:21
 ; CHECK-NEXT:    str r1, [r2]
+; CHECK-NEXT:    add.w r2, r0, #15
+; CHECK-NEXT:    vst1.32 {d16[0]}, [r2]
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asavonic wrote:
> tingwang wrote:
> > Hello @dmgreen  @asavonic. This patch tries to reuse vector element for the tail store in memset by implementing `canCombineStoreAndExtract()` on PPC. This changed introduced test case change on ARM in llvm/test/CodeGen/ARM/memset-align.ll. Could you please help me check if the change looks good or not? Thank you!
> > 
> > Looked into the scenario on ARM, if the i8 fill value of memset is zero, it creates vector for the initial 16B, and constant tail for the remaining bytes, which exactly hit this patch's scenario. For other values, it creates i32 for memset and will not be impacted by this patch.
> This looks fine to me. VST1 and scalar STR seem equivalent in this case, if I'm reading the docs right.  
> This looks fine to me. VST1 and scalar STR seem equivalent in this case, if I'm reading the docs right.  

Thank you for the confirm!


Repository:
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  https://reviews.llvm.org/D138883/new/

https://reviews.llvm.org/D138883