[llvm] c19f905 - [PowerPC] Implement xscmpeqqp, xscmpgeqp, xscmpgtqp instructions

[Maryam Moghadas via llvm-commits]

Author: Maryam Moghadas
Date: 2022-12-01T15:01:49-06:00
New Revision: c19f905fed4bb67dbf38b405606a3e1e61ac76d6

URL: https://github.com/llvm/llvm-project/commit/c19f905fed4bb67dbf38b405606a3e1e61ac76d6
DIFF: https://github.com/llvm/llvm-project/commit/c19f905fed4bb67dbf38b405606a3e1e61ac76d6.diff

LOG: [PowerPC] Implement xscmpeqqp, xscmpgeqp, xscmpgtqp instructions

This patch adds 3 Power10 VSX Scalar compare for quad precision
instructions including xscmpeqqp, xscmpgeqp, xscmpgtqp

Reviewed By: amyk

Differential Revision: https://reviews.llvm.org/D138592

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/P10InstrResources.td
    llvm/lib/Target/PowerPC/PPCInstrP10.td
    llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
    llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/P10InstrResources.td b/llvm/lib/Target/PowerPC/P10InstrResources.td
index 232853635e0ae..7ba7cfd77b694 100644
--- a/llvm/lib/Target/PowerPC/P10InstrResources.td
+++ b/llvm/lib/Target/PowerPC/P10InstrResources.td
@@ -616,7 +616,10 @@ def : InstRW<[P10W_DX_5C, P10W_DISP_ANY, P10DX_Read, P10DX_Read],
     VMUL10EUQ,
     VSUBCUQ,
     VSUBUQM,
+    XSCMPEQQP,
     XSCMPEXPQP,
+    XSCMPGEQP,
+    XSCMPGTQP,
     XSCMPOQP,
     XSCMPUQP,
     XSMAXCQP,

diff  --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td
index a40b59423e8d3..853d81d05db8d 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrP10.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td
@@ -1100,6 +1100,12 @@ let Predicates = [PairedVectorMemops] in {
   }
 }
 
+let Predicates = [IsISA3_1] in {
+  def XSCMPEQQP : X_VT5_VA5_VB5<63, 68, "xscmpeqqp", []>;
+  def XSCMPGEQP : X_VT5_VA5_VB5<63, 196, "xscmpgeqp", []>;
+  def XSCMPGTQP : X_VT5_VA5_VB5<63, 228, "xscmpgtqp", []>;
+}
+
 let Predicates = [PCRelativeMemops] in {
   // Load i32
   def : Pat<(i32 (zextloadi1  (PPCmatpcreladdr PCRelForm:$ga))),

diff  --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
index 730b4b8ed3d68..5a42c3983e400 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
@@ -747,6 +747,15 @@
 # CHECK: xsmincqp 2, 2, 3
 0xfc 0x42 0x1d 0xc8
 
+# CHECK: xscmpeqqp 1, 2, 2
+0xfc 0x22 0x10 0x88
+
+# CHECK: xscmpgeqp 1, 2, 3
+0xfc 0x22 0x19 0x88
+
+# CHECK: xscmpgtqp 1, 2, 4
+0xfc 0x22 0x21 0xc8
+
 # CHECK: vstribr 2, 2
 0x10 0x41 0x10 0x0d
 

diff  --git a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
index 06c5b4900d989..d18c84dc73cbc 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
@@ -945,6 +945,15 @@
 # CHECK-BE: xsmincqp 2, 2, 3                      # encoding: [0xfc,0x42,0x1d,0xc8]
 # CHECK-LE: xsmincqp 2, 2, 3                      # encoding: [0xc8,0x1d,0x42,0xfc]
             xsmincqp 2, 2, 3
+# CHECK-BE: xscmpeqqp 1, 2, 2                     # encoding: [0xfc,0x22,0x10,0x88]
+# CHECK-LE: xscmpeqqp 1, 2, 2                     # encoding: [0x88,0x10,0x22,0xfc]
+            xscmpeqqp 1, 2, 2
+# CHECK-BE: xscmpgeqp 1, 2, 3                     # encoding: [0xfc,0x22,0x19,0x88]
+# CHECK-LE: xscmpgeqp 1, 2, 3                     # encoding: [0x88,0x19,0x22,0xfc]
+            xscmpgeqp 1, 2, 3
+# CHECK-BE: xscmpgtqp 1, 2, 4                     # encoding: [0xfc,0x22,0x21,0xc8]
+# CHECK-LE: xscmpgtqp 1, 2, 4                     # encoding: [0xc8,0x21,0x22,0xfc]
+            xscmpgtqp 1, 2, 4
 # CHECK-BE: vstribr 2, 2                          # encoding: [0x10,0x41,0x10,0x0d]
 # CHECK-LE: vstribr 2, 2                          # encoding: [0x0d,0x10,0x41,0x10]
             vstribr 2, 2