[PATCH] D139079: [RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.

[Philip Reames via Phabricator via llvm-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139079/new/

https://reviews.llvm.org/D139079