[PATCH] D139079: [RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.

[Alex Bradbury via Phabricator via llvm-commits]

asb added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:441
 
   // For now we support the compressible instructions which can encode all
   // registers and have a single register source.
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I missed this on the previous patch, but this comment is no longer accurate now there's support for some GPRC instructions.


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:473
 
+  // Is this operand a GPRC register. reg-reg instructions that require need
+  // GPRC need all register operands to be GPRC.
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"require need" => "require"


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:475
+  // GPRC need all register operands to be GPRC.
+  auto isCompressibleOp = [&](const MachineOperand &MO) {
+    if (!MO.isReg())
----------------
Not a huge deal either way as it's fairly clear from the context, but perhaps `isCompressibleOpnd` would be marginally better?


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:476
+  auto isCompressibleOp = [&](const MachineOperand &MO) {
+    if (!MO.isReg())
+      return true;
----------------
The fact this returns true for any non-register operand could perhaps be noted in the comment above?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139079/new/

https://reviews.llvm.org/D139079