[PATCH] D139086: [AArch64] Implement __arm_rsr128/__arm_wsr128

[Sam Elliott via Phabricator via llvm-commits]

lenary created this revision.
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This only contains the SelectionDAG implementation. GlobalISel to
follow.

The broad approach is:

- Introduce new builtins for 128-bit wide instructions.
- Lower these to @llvm.read_register.i128/@llvm.write_register.i128
- Introduce target-specific ISD nodes which have legal operands (two i64s rather than an i128). These are named AArch64::{MRRS, MSRR} to match the instructions they are for. These are a little complex as they need to match the "shape" of what they're replacing or the legaliser complains.
- Select these using the existing tryReadRegister/tryWriteRegister to share the MDString parsing code, and introduce additional code to ensure these are selected into the right MRRS/MSRR instructions. What makes this hard is ensuring that the two i64s end up in an XSeqPair register pair, because SelectionDAG doesn't care that much about register classes if it can avoid doing so.

The main change to existing code is the reorganisation of
tryReadRegister and tryWriteRegister to try to keep the string parsing
code separate from the instruction creating code.

This also includes the changes to clang to define and use the ACLE
feature macro named `__ARM_FEATURE_SYSREG128`.

Contributors:

  Sam Elliott
  Lucas Prates


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139086

Files:
  clang/include/clang/Basic/BuiltinsAArch64.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/arm_acle.h
  clang/test/CodeGen/arm_acle.c
  clang/test/Preprocessor/aarch64-target-features.c
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AArch64/aarch64-sysreg128.ll

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