[PATCH] D137530: [RISCV] Splat scalar to be of length VL instead of 1 for reductions
Wang Pengcheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 30 22:23:20 PST 2022
pcwang-thead marked 5 inline comments as done.
pcwang-thead added inline comments.
================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll:369
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v9, fa0
----------------
craig.topper wrote:
> Why is this e32,m1 instead of e32, mf2?
Good catch! Fixed.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D137530/new/
https://reviews.llvm.org/D137530
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