[PATCH] D139073: [X86] AMD Zen 4 Initial enablement

[Ganesh Gopalasubramanian via Phabricator via llvm-commits]

GGanesh created this revision.
GGanesh added reviewers: RKSimon, craig.topper, andreadb.
Herald added subscribers: Enna1, StephenFan, pengfei, gbedwell, javed.absar, hiraditya.
Herald added a project: All.
GGanesh requested review of this revision.
Herald added projects: clang, Sanitizers, LLVM.
Herald added subscribers: llvm-commits, Sanitizers, cfe-commits.

This patch has the initial skeleton that enables AMD znver4!

AMD znver4 belongs to Family 19h with model numbers as below
Models 0x10 to 0x1f 
Models 0x60 to 0x74
Models 0x78 to 0x7b
Models 0xA0 to 0xAf

The patch

1. Includes ISAs that already have target descriptions are added.
2. Uses znver3 scheduler model as of now. (We have update this later)
3. Updates few tests as per the initial enablement.
4. ISAs that are added are

avx512f, 
avx512dq, 
avx512ifma, 
avx512cd, 
avx512bw, 
avx512vl, 
avx512_bf16, 
avx512vbmi, 
avx512vbmi2,
avx512vl,
avx512_vnni, 
avx512_bitalg, 
avx512_vpopcntdq/vl


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139073

Files:
  clang/lib/Basic/Targets/X86.cpp
  clang/test/CodeGen/target-builtin-noerror.c
  clang/test/Driver/x86-march.c
  clang/test/Frontend/x86-target-cpu.c
  clang/test/Misc/target-invalid-cpu-note.c
  clang/test/Preprocessor/predefined-arch-macros.c
  compiler-rt/lib/builtins/cpu_model.c
  llvm/include/llvm/Support/X86TargetParser.h
  llvm/lib/Support/Host.cpp
  llvm/lib/Support/X86TargetParser.cpp
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86PfmCounters.td
  llvm/test/CodeGen/X86/rdpru.ll
  llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
  llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll
  llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll
  llvm/test/MC/X86/x86_long_nop.s
  llvm/test/tools/llvm-mca/X86/cpus.s
  llvm/test/tools/llvm-mca/X86/read-after-ld-1.s
  llvm/test/tools/llvm-mca/X86/register-file-statistics.s
  llvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s

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