[PATCH] D138899: [PowerPC] add a peephole to eliminate unnecessary load

[ChenZheng via Phabricator via llvm-commits]

shchenz added a comment.

Thanks for taking a look @nemanjai

> Please add some information about other approaches you considered/attempted to solve this problem.

Hope I explained enough for the reason I didn't do this in DAG-ISEL while lower calls with byval parameter. And PPC is working on switching to Global-ISEL, so that's another reason it is not so good to implement the load elimination for byval parameter in DAG-ISEL.

My first thought was implementing this in MachineCSE. But I did't do it there because:

- MachineCSE is a target independent pass. From what I got, byval parameter for the call seems will not be lowered to loads to the caller's stack frame for all the other targets(at least some?). Target independent peephole was also excluded because of this.
- MachineCSE seems only commoning instructions which have same opcodes, i.e., it can handle load elimination for pattern `load addr  ...  load addr`.



> While I am not all that familiar with MemorySSA, it would seem that this is the exact type of thing it should handle effortlessly.

MemorySSA is not an analysis pass that can be used by MIR pass for now. And MemorySSA depends on `AAResultsWrapperPass` which may leads to compiler time concern. IR level pass mem2reg also does not require `MemorySSA` to do the transformation.

I thought there is no other pass which can implement this opt in PPC pipeline except the above ones, but maybe you can give some insight here.


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https://reviews.llvm.org/D138899