[PATCH] D11621: AMDGPU/SI: Mark SMRD instructions as rematerializable

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

In D11621#3961345 <https://reviews.llvm.org/D11621#3961345>, @arsenm wrote:

> In D11621#3961342 <https://reviews.llvm.org/D11621#3961342>, @rampitec wrote:
>
>> In D11621#3958649 <https://reviews.llvm.org/D11621#3958649>, @arsenm wrote:
>>
>>> In D11621#3958647 <https://reviews.llvm.org/D11621#3958647>, @rampitec wrote:
>>>
>>>> I do not think this is OK. We may issue a scalar load before a first potentially aliasing store. After the store it must become a VMEM load because caches are not coherent. That said you cannot reorder SMRD with aliasing VMEM store, both because of the coherency and because memory may be indeed overwritten.
>>>
>>> This only happens for invariant MMOs. This isn't the only condition
>>
>> Where is that checked? Also needs tests, both positive and negative.
>
> https://github.com/llvm/llvm-project/blob/442c13f9ff8a8c6739d649c5a68e065f2a727480/llvm/lib/CodeGen/TargetInstrInfo.cpp#L956
>
> The patch as-is doesn't apply obviously. I wrote tests and found they don't work due to virtual register uses in any real case (which is I'm guessing what the special case in isReallyTriviallyReMaterializable is about)

I thought we are overriding TargetInstrInfo::isReallyTriviallyReMaterializable completely.


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https://reviews.llvm.org/D11621