[PATCH] D138302: [MachineCombiner][RISCV] Make hasReassociableSibling virtual and override it for RISCV

[Craig Topper via Phabricator via llvm-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM



================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1211
 
-  if (!Root.getFlag(MachineInstr::MIFlag::FmReassoc) ||
-      !Root.getFlag(MachineInstr::MIFlag::FmNsz) ||
-      !MI->getFlag(MachineInstr::MIFlag::FmReassoc) ||
-      !MI->getFlag(MachineInstr::MIFlag::FmNsz))
-    return false;
+  return RISCV::hasEqualFRM(Inst, Sibling);
+}
----------------
asi-sc wrote:
> Currently, `hasEqualFRM` returns `false` even if both instructions don't have FRM at all. So, to add integer instructions reassociation we:
>   1. Can check that `Inst` and `Sibling` are floating-point instructions and check FRM equality only in this case 
>   Or
>   2. return `true` from `hasEqualFRM` if both instructions do not have FRM operand.
> 
> I'd like to ask reviewers which way is better to follow? I'd prefer the second option. 
> 
> The question is not about this review, but I'm trying to think a few steps ahead.
Right now `hasEqualFRM` returns false if either instruction doesn't have an FRM operand. Does that false case ever happen? Sounds like your option 2 here would need that to return `true` if the FRM operand isn't present.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138302/new/

https://reviews.llvm.org/D138302