[PATCH] D137530: [RISCV] Splat scalar to be of length VL instead of 1 for reductions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1881
+  return (RegisterAVL && RegisterAVL->getReg() == RISCV::X0) ||
+         (ImmAVL && ImmAVL->getSExtValue() >= 1);
+}
----------------
AVL is unsigned. Why getSExtValue?


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:5732
+  if (ElementCount::isKnownGT(ContainerVT.getVectorElementCount(),
+                              M1VT.getVectorElementCount()))
+    IdentitySplat =
----------------
Add curly braces. LLVM coding standards say that if/else should both uses braces if one does.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:5806
+  if (ElementCount::isKnownGT(ContainerVT.getVectorElementCount(),
+                              M1VT.getVectorElementCount()))
+    ScalarSplat =
----------------
Curly braces


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:5887
+                              M1VT.getVectorElementCount()) ||
+      !hasNonZeroAVL(VL))
+    StartSplat = lowerScalarSplat(SDValue(), Op.getOperand(0),
----------------
Curly braces


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll:369
 ; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
+; CHECK-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
 ; CHECK-NEXT:    vfmv.s.f v9, fa0
----------------
Why is this e32,m1 instead of e32, mf2?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137530/new/

https://reviews.llvm.org/D137530