[llvm] 1f04ac5 - [RISCV] Merge two versions of adjustReg on TRI [nfc]
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 30 10:12:48 PST 2022
Author: Philip Reames
Date: 2022-11-30T10:12:40-08:00
New Revision: 1f04ac54f9f7f90edfaad7ffd9ef31264b827c7b
URL: https://github.com/llvm/llvm-project/commit/1f04ac54f9f7f90edfaad7ffd9ef31264b827c7b
DIFF: https://github.com/llvm/llvm-project/commit/1f04ac54f9f7f90edfaad7ffd9ef31264b827c7b.diff
LOG: [RISCV] Merge two versions of adjustReg on TRI [nfc]
After ac1ec9e, the version with the StackOffset param has a strict superset of behavior. As a result, we can switch callers to use it, and then inline the other version into the now-single caller.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
llvm/lib/Target/RISCV/RISCVRegisterInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index cca94d1d6158..dba3fc986867 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -297,8 +297,8 @@ void RISCVFrameLowering::adjustReg(MachineBasicBlock &MBB,
// We must keep the stack pointer aligned through any intermediate
// updates.
const RISCVRegisterInfo &RI = *STI.getRegisterInfo();
- RI.adjustReg(MBB, MBBI, DL, DestReg, SrcReg, Val, Flag,
- getStackAlign(), /*KillSrcReg=*/false);
+ RI.adjustReg(MBB, MBBI, DL, DestReg, SrcReg, StackOffset::getFixed(Val),
+ Flag, getStackAlign());
}
// Returns the register used to hold the frame pointer.
@@ -349,7 +349,7 @@ void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF,
const RISCVRegisterInfo &RI = *STI.getRegisterInfo();
RI.adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getScalable(Amount),
- Flag);
+ Flag, None);
}
void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 978237b7a4a7..1cc94e23fe10 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -162,22 +162,49 @@ bool RISCVRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
}
void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
+ MachineBasicBlock::iterator II,
const DebugLoc &DL, Register DestReg,
- Register SrcReg, int64_t Val,
+ Register SrcReg, StackOffset Offset,
MachineInstr::MIFlag Flag,
- MaybeAlign RequiredAlign,
- bool KillSrcReg) const {
- const uint64_t Align = RequiredAlign.valueOrOne().value();
- MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
- const RISCVSubtarget &ST = MBB.getParent()->getSubtarget<RISCVSubtarget>();
+ MaybeAlign RequiredAlign) const {
+
+ if (DestReg == SrcReg && !Offset.getFixed() && !Offset.getScalable())
+ return;
+
+ MachineFunction &MF = *MBB.getParent();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+ const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
const RISCVInstrInfo *TII = ST.getInstrInfo();
+ bool KillSrcReg = false;
+
+ if (Offset.getScalable()) {
+ unsigned ScalableAdjOpc = RISCV::ADD;
+ int64_t ScalableValue = Offset.getScalable();
+ if (ScalableValue < 0) {
+ ScalableValue = -ScalableValue;
+ ScalableAdjOpc = RISCV::SUB;
+ }
+ // Get vlenb and multiply vlen with the number of vector registers.
+ Register ScratchReg = DestReg;
+ if (DestReg == SrcReg)
+ ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+ TII->getVLENFactoredAmount(MF, MBB, II, DL, ScratchReg, ScalableValue, Flag);
+ BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), DestReg)
+ .addReg(SrcReg).addReg(ScratchReg, RegState::Kill)
+ .setMIFlag(Flag);
+ SrcReg = DestReg;
+ KillSrcReg = true;
+ }
+
+ int64_t Val = Offset.getFixed();
if (DestReg == SrcReg && Val == 0)
return;
+ const uint64_t Align = RequiredAlign.valueOrOne().value();
+
if (isInt<12>(Val)) {
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)
+ BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg)
.addReg(SrcReg, getKillRegState(KillSrcReg))
.addImm(Val)
.setMIFlag(Flag);
@@ -195,11 +222,11 @@ void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
if (Val > -4096 && Val <= (2 * MaxPosAdjStep)) {
int64_t FirstAdj = Val < 0 ? -2048 : MaxPosAdjStep;
Val -= FirstAdj;
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)
+ BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg)
.addReg(SrcReg, getKillRegState(KillSrcReg))
.addImm(FirstAdj)
.setMIFlag(Flag);
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)
+ BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg)
.addReg(DestReg, RegState::Kill)
.addImm(Val)
.setMIFlag(Flag);
@@ -213,53 +240,13 @@ void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
}
Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
- TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag);
- BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
+ TII->movImm(MBB, II, DL, ScratchReg, Val, Flag);
+ BuildMI(MBB, II, DL, TII->get(Opc), DestReg)
.addReg(SrcReg, getKillRegState(KillSrcReg))
.addReg(ScratchReg, RegState::Kill)
.setMIFlag(Flag);
}
-void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator II,
- const DebugLoc &DL, Register DestReg,
- Register SrcReg, StackOffset Offset,
- MachineInstr::MIFlag Flag) const {
-
- if (DestReg == SrcReg && !Offset.getFixed() && !Offset.getScalable())
- return;
-
- MachineFunction &MF = *MBB.getParent();
- MachineRegisterInfo &MRI = MF.getRegInfo();
- const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
- const RISCVInstrInfo *TII = ST.getInstrInfo();
-
- bool SrcRegIsKill = false;
-
- if (Offset.getScalable()) {
- unsigned ScalableAdjOpc = RISCV::ADD;
- int64_t ScalableValue = Offset.getScalable();
- if (ScalableValue < 0) {
- ScalableValue = -ScalableValue;
- ScalableAdjOpc = RISCV::SUB;
- }
- // Get vlenb and multiply vlen with the number of vector registers.
- Register ScratchReg = DestReg;
- if (DestReg == SrcReg)
- ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
- TII->getVLENFactoredAmount(MF, MBB, II, DL, ScratchReg, ScalableValue, Flag);
- BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), DestReg)
- .addReg(SrcReg).addReg(ScratchReg, RegState::Kill)
- .setMIFlag(Flag);
- SrcReg = DestReg;
- SrcRegIsKill = true;
- }
-
- if (Offset.getFixed())
- adjustReg(MBB, II, DL, DestReg, SrcReg, Offset.getFixed(),
- Flag, None, SrcRegIsKill);
-}
-
bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
@@ -319,7 +306,7 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
else
DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
adjustReg(*II->getParent(), II, DL, DestReg, FrameReg, Offset,
- MachineInstr::NoFlags);
+ MachineInstr::NoFlags, None);
MI.getOperand(FIOperandNum).ChangeToRegister(DestReg, /*IsDef*/false,
/*IsImp*/false,
/*IsKill*/true);
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
index e1880d1ce092..b90ee780a089 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -41,17 +41,11 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
// Update DestReg to have the value SrcReg plus an offset. This is
// used during frame layout, and we may need to ensure that if we
// split the offset internally that the DestReg is always aligned,
- // assuming that source reg was. KillSrcReg means that this is the
- // last use of SrcReg, and that the register can be killed internally.
- void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- const DebugLoc &DL, Register DestReg, Register SrcReg,
- int64_t Val, MachineInstr::MIFlag Flag,
- MaybeAlign RequiredAlign, bool KillSrcReg) const;
-
- // Update DestReg to have the value of SrcReg plus an Offset.
+ // assuming that source reg was.
void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator II,
const DebugLoc &DL, Register DestReg, Register SrcReg,
- StackOffset Offset, MachineInstr::MIFlag Flag) const;
+ StackOffset Offset, MachineInstr::MIFlag Flag,
+ MaybeAlign RequiredAlign) const;
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
unsigned FIOperandNum,
More information about the llvm-commits
mailing list