[PATCH] D134792: [PowerPC][GISel] support 64 bit load/store

[Amy Kwan via Phabricator via llvm-commits]

amyk added inline comments.


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Comment at: llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp:133
+                                  unsigned OpSize) {
+  const bool isStore = GenericOpc == TargetOpcode::G_STORE;
+  switch (RegBankID) {
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Minor nit: Capitalize the first word of the variable to adhere to the LLVM coding guidelines. 


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Comment at: llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp:124
+    assert(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() == 64 &&
+           "Unsupported types!\n");
+    // Check if that load feeds fp instructions.
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nit: Maybe we can say `Unsupported load type!`

But also a question - I know there was a comment earlier stating that the assert in the instruction selector wasn't needed because the verifier checks that kind of stuff, but is this the same for the register bank selection pass?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134792/new/

https://reviews.llvm.org/D134792