[llvm] 5ec9403 - InstCombine: Add baseline checks for is_fpclass
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 30 06:05:43 PST 2022
Author: Matt Arsenault
Date: 2022-11-30T09:05:37-05:00
New Revision: 5ec9403e79887d68899c7451db11b3fc5f51692b
URL: https://github.com/llvm/llvm-project/commit/5ec9403e79887d68899c7451db11b3fc5f51692b
DIFF: https://github.com/llvm/llvm-project/commit/5ec9403e79887d68899c7451db11b3fc5f51692b.diff
LOG: InstCombine: Add baseline checks for is_fpclass
Added:
llvm/test/Transforms/InstCombine/is_fpclass.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/is_fpclass.ll b/llvm/test/Transforms/InstCombine/is_fpclass.ll
new file mode 100644
index 0000000000000..6edaa124cb96e
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/is_fpclass.ll
@@ -0,0 +1,397 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -passes=instcombine < %s | FileCheck %s
+
+; --------------------------------------------------------------------
+; llvm.is.fpclass
+; --------------------------------------------------------------------
+
+; FIXME: Should this really be immarg?
+; define i1 @test_class_undef_mask_f32(float %x) {
+; %val = call i1 @llvm.is.fpclass.f32(float %x, i32 undef)
+; ret i1 %val
+; }
+
+define i1 @test_class_over_max_mask_f32(float %x) {
+; CHECK-LABEL: @test_class_over_max_mask_f32(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 1025)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f32(float %x, i32 1025)
+ ret i1 %val
+}
+
+define i1 @test_class_no_mask_f32(float %x) {
+; CHECK-LABEL: @test_class_no_mask_f32(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 0)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f32(float %x, i32 0)
+ ret i1 %val
+}
+
+define i1 @test_class_full_mask_f32(float %x) {
+; CHECK-LABEL: @test_class_full_mask_f32(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 1023)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f32(float %x, i32 1023)
+ ret i1 %val
+}
+
+define i1 @test_class_undef_no_mask_f32() {
+; CHECK-LABEL: @test_class_undef_no_mask_f32(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float undef, i32 0)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f32(float undef, i32 0)
+ ret i1 %val
+}
+
+define i1 @test_class_undef_full_mask_f32() {
+; CHECK-LABEL: @test_class_undef_full_mask_f32(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float undef, i32 1023)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f32(float undef, i32 1023)
+ ret i1 %val
+}
+
+define i1 @test_class_poison_no_mask_f32() {
+; CHECK-LABEL: @test_class_poison_no_mask_f32(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float poison, i32 0)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f32(float poison, i32 0)
+ ret i1 %val
+}
+
+define i1 @test_class_poison_full_mask_f32() {
+; CHECK-LABEL: @test_class_poison_full_mask_f32(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float poison, i32 1023)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f32(float poison, i32 1023)
+ ret i1 %val
+}
+
+define i1 @test_class_undef_val_f32() {
+; CHECK-LABEL: @test_class_undef_val_f32(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float undef, i32 4)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f32(float undef, i32 4)
+ ret i1 %val
+}
+
+define i1 @test_class_poison_val_f32() {
+; CHECK-LABEL: @test_class_poison_val_f32(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float poison, i32 4)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f32(float poison, i32 4)
+ ret i1 %val
+}
+
+; FIXME: Should this really be immarg?
+; define i1 @test_class_undef_undef_f32() {
+; %val = call i1 @llvm.is.fpclass.f32(float undef, i32 undef)
+; ret i1 %val
+; }
+
+; FIXME: Should this really be immarg?
+; define i1 @test_class_var_mask_f32(float %x, i32 %mask) {
+; %val = call i1 @llvm.is.fpclass.f32(float %x, i32 %mask)
+; ret i1 %val
+; }
+
+define i1 @test_class_isnan_f32(float %x) {
+; CHECK-LABEL: @test_class_isnan_f32(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 3)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f32(float %x, i32 3)
+ ret i1 %val
+}
+
+define i1 @test_class_isnan_f32_strict(float %x) {
+; CHECK-LABEL: @test_class_isnan_f32_strict(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 3) #[[ATTR2:[0-9]+]]
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f32(float %x, i32 3) strictfp
+ ret i1 %val
+}
+
+define i1 @test_class_is_p0_n0_f32(float %x) {
+; CHECK-LABEL: @test_class_is_p0_n0_f32(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 96)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f32(float %x, i32 96)
+ ret i1 %val
+}
+
+define i1 @test_class_is_p0_n0_f32_strict(float %x) {
+; CHECK-LABEL: @test_class_is_p0_n0_f32_strict(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f32(float [[X:%.*]], i32 96) #[[ATTR2]]
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f32(float %x, i32 96) strictfp
+ ret i1 %val
+}
+
+define i1 @test_constant_class_snan_test_snan_f64() {
+; CHECK-LABEL: @test_constant_class_snan_test_snan_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000001, i32 1)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000001, i32 1)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_qnan_test_qnan_f64() {
+; CHECK-LABEL: @test_constant_class_qnan_test_qnan_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x7FF8000000000000, i32 2)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double 0x7FF8000000000000, i32 2)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_qnan_test_snan_f64() {
+; CHECK-LABEL: @test_constant_class_qnan_test_snan_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x7FF8000000000000, i32 1)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double 0x7FF8000000000000, i32 1)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_ninf_test_ninf_f64() {
+; CHECK-LABEL: @test_constant_class_ninf_test_ninf_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0xFFF0000000000000, i32 4)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double 0xFFF0000000000000, i32 4)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_pinf_test_ninf_f64() {
+; CHECK-LABEL: @test_constant_class_pinf_test_ninf_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000000, i32 4)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000000, i32 4)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_qnan_test_ninf_f64() {
+; CHECK-LABEL: @test_constant_class_qnan_test_ninf_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x7FF8000000000000, i32 4)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double 0x7FF8000000000000, i32 4)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_snan_test_ninf_f64() {
+; CHECK-LABEL: @test_constant_class_snan_test_ninf_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000001, i32 4)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000001, i32 4)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_nnormal_test_nnormal_f64() {
+; CHECK-LABEL: @test_constant_class_nnormal_test_nnormal_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double -1.000000e+00, i32 8)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double -1.0, i32 8)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_pnormal_test_nnormal_f64() {
+; CHECK-LABEL: @test_constant_class_pnormal_test_nnormal_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 1.000000e+00, i32 8)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double 1.0, i32 8)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_nsubnormal_test_nsubnormal_f64() {
+; CHECK-LABEL: @test_constant_class_nsubnormal_test_nsubnormal_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x800FFFFFFFFFFFFF, i32 16)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double 0x800fffffffffffff, i32 16)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_psubnormal_test_nsubnormal_f64() {
+; CHECK-LABEL: @test_constant_class_psubnormal_test_nsubnormal_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0xFFFFFFFFFFFFF, i32 16)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double 0x000fffffffffffff, i32 16)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_nzero_test_nzero_f64() {
+; CHECK-LABEL: @test_constant_class_nzero_test_nzero_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double -0.000000e+00, i32 32)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double -0.0, i32 32)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_pzero_test_nzero_f64() {
+; CHECK-LABEL: @test_constant_class_pzero_test_nzero_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0.000000e+00, i32 32)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double 0.0, i32 32)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_pzero_test_pzero_f64() {
+; CHECK-LABEL: @test_constant_class_pzero_test_pzero_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0.000000e+00, i32 64)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double 0.0, i32 64)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_nzero_test_pzero_f64() {
+; CHECK-LABEL: @test_constant_class_nzero_test_pzero_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double -0.000000e+00, i32 64)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double -0.0, i32 64)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_psubnormal_test_psubnormal_f64() {
+; CHECK-LABEL: @test_constant_class_psubnormal_test_psubnormal_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0xFFFFFFFFFFFFF, i32 128)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double 0x000fffffffffffff, i32 128)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_nsubnormal_test_psubnormal_f64() {
+; CHECK-LABEL: @test_constant_class_nsubnormal_test_psubnormal_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x800FFFFFFFFFFFFF, i32 128)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double 0x800fffffffffffff, i32 128)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_pnormal_test_pnormal_f64() {
+; CHECK-LABEL: @test_constant_class_pnormal_test_pnormal_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 1.000000e+00, i32 256)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double 1.0, i32 256)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_nnormal_test_pnormal_f64() {
+; CHECK-LABEL: @test_constant_class_nnormal_test_pnormal_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double -1.000000e+00, i32 256)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double -1.0, i32 256)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_pinf_test_pinf_f64() {
+; CHECK-LABEL: @test_constant_class_pinf_test_pinf_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000000, i32 512)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000000, i32 512)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_ninf_test_pinf_f64() {
+; CHECK-LABEL: @test_constant_class_ninf_test_pinf_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0xFFF0000000000000, i32 512)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double 0xFFF0000000000000, i32 512)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_qnan_test_pinf_f64() {
+; CHECK-LABEL: @test_constant_class_qnan_test_pinf_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x7FF8000000000000, i32 512)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double 0x7FF8000000000000, i32 512)
+ ret i1 %val
+}
+
+define i1 @test_constant_class_snan_test_pinf_f64() {
+; CHECK-LABEL: @test_constant_class_snan_test_pinf_f64(
+; CHECK-NEXT: [[VAL:%.*]] = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000001, i32 512)
+; CHECK-NEXT: ret i1 [[VAL]]
+;
+ %val = call i1 @llvm.is.fpclass.f64(double 0x7FF0000000000001, i32 512)
+ ret i1 %val
+}
+
+define i1 @test_class_is_snan_nnan_src(float %x) {
+; CHECK-LABEL: @test_class_is_snan_nnan_src(
+; CHECK-NEXT: [[NNAN:%.*]] = fadd nnan float [[X:%.*]], 1.000000e+00
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NNAN]], i32 1)
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %nnan = fadd nnan float %x, 1.0
+ %class = call i1 @llvm.is.fpclass.f32(float %nnan, i32 1)
+ ret i1 %class
+}
+
+define i1 @test_class_is_qnan_nnan_src(float %x) {
+; CHECK-LABEL: @test_class_is_qnan_nnan_src(
+; CHECK-NEXT: [[NNAN:%.*]] = fadd nnan float [[X:%.*]], 1.000000e+00
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NNAN]], i32 2)
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %nnan = fadd nnan float %x, 1.0
+ %class = call i1 @llvm.is.fpclass.f32(float %nnan, i32 2)
+ ret i1 %class
+}
+
+define i1 @test_class_is_nan_nnan_src(float %x) {
+; CHECK-LABEL: @test_class_is_nan_nnan_src(
+; CHECK-NEXT: [[NNAN:%.*]] = fadd nnan float [[X:%.*]], 1.000000e+00
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NNAN]], i32 3)
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %nnan = fadd nnan float %x, 1.0
+ %class = call i1 @llvm.is.fpclass.f32(float %nnan, i32 3)
+ ret i1 %class
+}
+
+define i1 @test_class_is_nan_other_nnan_src(float %x) {
+; CHECK-LABEL: @test_class_is_nan_other_nnan_src(
+; CHECK-NEXT: [[NNAN:%.*]] = fadd nnan float [[X:%.*]], 1.000000e+00
+; CHECK-NEXT: [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f32(float [[NNAN]], i32 267)
+; CHECK-NEXT: ret i1 [[CLASS]]
+;
+ %nnan = fadd nnan float %x, 1.0
+ %class = call i1 @llvm.is.fpclass.f32(float %nnan, i32 267)
+ ret i1 %class
+}
+
+
+
+declare i1 @llvm.is.fpclass.f32(float, i32 immarg)
+declare i1 @llvm.is.fpclass.f64(double, i32 immarg)
More information about the llvm-commits
mailing list