[llvm] 53efce3 - [AMDGPU] Remove todo about vector types

[Sebastian Neubauer via llvm-commits]

Author: Sebastian Neubauer
Date: 2022-11-30T14:13:12+01:00
New Revision: 53efce306497ffe7080fdac6123d8f643fc009ea

URL: https://github.com/llvm/llvm-project/commit/53efce306497ffe7080fdac6123d8f643fc009ea
DIFF: https://github.com/llvm/llvm-project/commit/53efce306497ffe7080fdac6123d8f643fc009ea.diff

LOG: [AMDGPU] Remove todo about vector types

D138205 added all the new vector types, so the todo is fixed now.

Differential Revision: https://reviews.llvm.org/D139002

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/MIMGInstructions.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index d018fd88b71a..0085a313497e 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -1133,8 +1133,6 @@ multiclass MIMG_Gather_WQM <mimgopc op, AMDGPUSampleVariant sample>
 
 class MIMG_IntersectRay_Helper<bit Is64, bit A16> {
   int num_addrs = !if(Is64, !if(A16, 9, 12), !if(A16, 8, 11));
-  // TODO: MIMGAddrSize will choose VReg_512 which is a 16 register tuple,
-  // when we only need 9, 11 or 12 depending on A16 field and ptr size.
   RegisterClass RegClass = MIMGAddrSize<num_addrs, 0>.RegClass;
   int VAddrDwords = !srl(RegClass.Size, 5);