[PATCH] D129735: [RISCV] Add new pass to transform undef to pseudo for vector values.

[Piyou Chen via Phabricator via llvm-commits]

BeMg updated this revision to Diff 478877.
BeMg added a comment.

1. Fix spell
2. Update isVectorRegClass


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129735/new/

https://reviews.llvm.org/D129735

Files:
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/O3-pipeline.ll
  llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
  llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber-vrm4.mir
  llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber_vrm8.mir
  llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
  llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D129735.478877.patch
Type: text/x-patch
Size: 37696 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221130/bd07d7f0/attachment.bin>