[PATCH] D137426: [RISCV][Codegen] Account for LMUL in Vector floating-point instructions
Wang Pengcheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 30 00:19:37 PST 2022
pcwang-thead added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:15
defvar SchedMxListW = ["UpperBound", "MF8", "MF4", "MF2", "M1", "M2", "M4"];
+defvar SchedMxListFW = ["UpperBound", "MF4", "MF2", "M1", "M2", "M4"];
----------------
D138640 was landed, so I think we should define variants with postfix "FW" here.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D137426/new/
https://reviews.llvm.org/D137426
More information about the llvm-commits
mailing list