[PATCH] D137426: [RISCV][Codegen] Account for LMUL in Vector floating-point instructions

Wang Pengcheng via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Nov 30 00:19:37 PST 2022


pcwang-thead added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:15
 defvar SchedMxListW = ["UpperBound", "MF8", "MF4", "MF2", "M1", "M2", "M4"];
+defvar SchedMxListFW = ["UpperBound", "MF4", "MF2", "M1", "M2", "M4"];
 
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D138640 was landed, so I think we should define variants with postfix "FW" here.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D137426/new/

https://reviews.llvm.org/D137426



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