[PATCH] D138904: [AArch64] Transform shift+and to shift+shift to select more shifted register

[chenglin.bi via Phabricator via llvm-commits]

bcl5980 updated this revision to Diff 478790.
bcl5980 marked 2 inline comments as done.
bcl5980 added a comment.

remove redundant condition


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138904/new/

https://reviews.llvm.org/D138904

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/test/CodeGen/AArch64/shiftregister-from-and.ll

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