[llvm] 26e44d4 - [RISCV][CodeGen] Account for LMUL for Vector Fixed-Point Arithmetic Instructions
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 29 16:21:10 PST 2022
Author: Michael Maitland
Date: 2022-11-29T16:20:58-08:00
New Revision: 26e44d4aeada0cbbde09701c6b470f7eb313fd41
URL: https://github.com/llvm/llvm-project/commit/26e44d4aeada0cbbde09701c6b470f7eb313fd41
DIFF: https://github.com/llvm/llvm-project/commit/26e44d4aeada0cbbde09701c6b470f7eb313fd41.diff
LOG: [RISCV][CodeGen] Account for LMUL for Vector Fixed-Point Arithmetic Instructions
It is likley that subtargets act differently for vector fixed-point arithmetic instructions based on the LMUL.
This patch creates seperate SchedRead, SchedWrite, WriteRes, ReadAdvance for each relevant LMUL.
Differential Revision: https://reviews.llvm.org/D137342
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVScheduleV.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 462faf1f227c9..76a15e7dff83a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -782,50 +782,65 @@ multiclass VDIV_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
multiclass VSALU_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
- Sched<[WriteVSALUV, ReadVSALUV, ReadVSALUV, ReadVMask]>;
+ Sched<[WriteVSALUV_UpperBound, ReadVSALUV_UpperBound,
+ ReadVSALUV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVSALUX, ReadVSALUV, ReadVSALUX, ReadVMask]>;
+ Sched<[WriteVSALUX_UpperBound, ReadVSALUV_UpperBound,
+ ReadVSALUX_UpperBound, ReadVMask]>;
def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
- Sched<[WriteVSALUI, ReadVSALUV, ReadVMask]>;
+ Sched<[WriteVSALUI_UpperBound, ReadVSALUV_UpperBound,
+ ReadVMask]>;
}
multiclass VSALU_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
- Sched<[WriteVSALUV, ReadVSALUV, ReadVSALUV, ReadVMask]>;
+ Sched<[WriteVSALUV_UpperBound, ReadVSALUV_UpperBound,
+ ReadVSALUV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVSALUX, ReadVSALUV, ReadVSALUX, ReadVMask]>;
+ Sched<[WriteVSALUX_UpperBound, ReadVSALUV_UpperBound,
+ ReadVSALUX_UpperBound, ReadVMask]>;
}
multiclass VAALU_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">,
- Sched<[WriteVAALUV, ReadVAALUV, ReadVAALUV, ReadVMask]>;
+ Sched<[WriteVAALUV_UpperBound, ReadVAALUV_UpperBound,
+ ReadVAALUV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVAALUX, ReadVAALUV, ReadVAALUX, ReadVMask]>;
+ Sched<[WriteVAALUX_UpperBound, ReadVAALUV_UpperBound,
+ ReadVAALUX_UpperBound, ReadVMask]>;
}
multiclass VSMUL_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
- Sched<[WriteVSMulV, ReadVSMulV, ReadVSMulV, ReadVMask]>;
+ Sched<[WriteVSMulV_UpperBound, ReadVSMulV_UpperBound,
+ ReadVSMulV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVSMulX, ReadVSMulV, ReadVSMulX, ReadVMask]>;
+ Sched<[WriteVSMulX_UpperBound, ReadVSMulV_UpperBound,
+ ReadVSMulX_UpperBound, ReadVMask]>;
}
multiclass VSSHF_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
- Sched<[WriteVSShiftV, ReadVSShiftV, ReadVSShiftV, ReadVMask]>;
+ Sched<[WriteVSShiftV_UpperBound, ReadVSShiftV_UpperBound,
+ ReadVSShiftV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVSShiftX, ReadVSShiftV, ReadVSShiftX, ReadVMask]>;
+ Sched<[WriteVSShiftX_UpperBound, ReadVSShiftV_UpperBound,
+ ReadVSShiftX_UpperBound, ReadVMask]>;
def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
- Sched<[WriteVSShiftI, ReadVSShiftV, ReadVMask]>;
+ Sched<[WriteVSShiftI_UpperBound, ReadVSShiftV_UpperBound,
+ ReadVMask]>;
}
multiclass VNCLP_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
- Sched<[WriteVNClipV, ReadVNClipV, ReadVNClipV, ReadVMask]>;
+ Sched<[WriteVNClipV_UpperBound, ReadVNClipV_UpperBound,
+ ReadVNClipV_UpperBound, ReadVMask]>;
def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
- Sched<[WriteVNClipX, ReadVNClipV, ReadVNClipX, ReadVMask]>;
+ Sched<[WriteVNClipX_UpperBound, ReadVNClipV_UpperBound,
+ ReadVNClipX_UpperBound, ReadVMask]>;
def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
- Sched<[WriteVNClipI, ReadVNClipV, ReadVMask]>;
+ Sched<[WriteVNClipI_UpperBound, ReadVNClipV_UpperBound,
+ ReadVMask]>;
}
multiclass VSLD_IV_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 23a42d91a3c80..39dff1178fd3c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -2379,12 +2379,21 @@ multiclass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = "">
}
multiclass VPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
- defm "" : VPseudoBinaryV_VV<Constraint>,
- Sched<[WriteVSALUV, ReadVSALUV, ReadVSALUV, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX<Constraint>,
- Sched<[WriteVSALUX, ReadVSALUV, ReadVSALUX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VI<ImmType, Constraint>,
- Sched<[WriteVSALUI, ReadVSALUV, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVSALUV_MX = !cast<SchedWrite>("WriteVSALUV_" # mx);
+ defvar WriteVSALUX_MX = !cast<SchedWrite>("WriteVSALUX_" # mx);
+ defvar WriteVSALUI_MX = !cast<SchedWrite>("WriteVSALUI_" # mx);
+ defvar ReadVSALUV_MX = !cast<SchedRead>("ReadVSALUV_" # mx);
+ defvar ReadVSALUX_MX = !cast<SchedRead>("ReadVSALUX_" # mx);
+
+ defm "" : VPseudoBinaryV_VV_LMUL<m, Constraint>,
+ Sched<[WriteVSALUV_MX, ReadVSALUV_MX, ReadVSALUV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_VX_LMUL<m, Constraint>,
+ Sched<[WriteVSALUX_MX, ReadVSALUV_MX, ReadVSALUX_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_VI_LMUL<ImmType, m, Constraint>,
+ Sched<[WriteVSALUI_MX, ReadVSALUV_MX, ReadVMask]>;
+ }
}
@@ -2407,12 +2416,21 @@ multiclass VPseudoVSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = "">
}
multiclass VPseudoVSSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
- defm "" : VPseudoBinaryV_VV<Constraint>,
- Sched<[WriteVSShiftV, ReadVSShiftV, ReadVSShiftV, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX<Constraint>,
- Sched<[WriteVSShiftX, ReadVSShiftV, ReadVSShiftX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VI<ImmType, Constraint>,
- Sched<[WriteVSShiftI, ReadVSShiftV, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVSShiftV_MX = !cast<SchedWrite>("WriteVSShiftV_" # mx);
+ defvar WriteVSShiftX_MX = !cast<SchedWrite>("WriteVSShiftX_" # mx);
+ defvar WriteVSShiftI_MX = !cast<SchedWrite>("WriteVSShiftI_" # mx);
+ defvar ReadVSShiftV_MX = !cast<SchedRead>("ReadVSShiftV_" # mx);
+ defvar ReadVSShiftX_MX = !cast<SchedRead>("ReadVSShiftX_" # mx);
+
+ defm "" : VPseudoBinaryV_VV_LMUL<m, Constraint>,
+ Sched<[WriteVSShiftV_MX, ReadVSShiftV_MX, ReadVSShiftV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_VX_LMUL<m, Constraint>,
+ Sched<[WriteVSShiftX_MX, ReadVSShiftV_MX, ReadVSShiftX_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_VI_LMUL<ImmType, m, Constraint>,
+ Sched<[WriteVSShiftI_MX, ReadVSShiftV_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
@@ -2434,24 +2452,48 @@ multiclass VPseudoVALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = "">
}
multiclass VPseudoVSALU_VV_VX {
- defm "" : VPseudoBinaryV_VV,
- Sched<[WriteVSALUV, ReadVSALUV, ReadVSALUV, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX,
- Sched<[WriteVSALUX, ReadVSALUV, ReadVSALUX, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVSALUV_MX = !cast<SchedWrite>("WriteVSALUV_" # mx);
+ defvar WriteVSALUX_MX = !cast<SchedWrite>("WriteVSALUX_" # mx);
+ defvar ReadVSALUV_MX = !cast<SchedRead>("ReadVSALUV_" # mx);
+ defvar ReadVSALUX_MX = !cast<SchedRead>("ReadVSALUX_" # mx);
+
+ defm "" : VPseudoBinaryV_VV_LMUL<m>,
+ Sched<[WriteVSALUV_MX, ReadVSALUV_MX, ReadVSALUV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_VX_LMUL<m>,
+ Sched<[WriteVSALUX_MX, ReadVSALUV_MX, ReadVSALUX_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVSMUL_VV_VX {
- defm "" : VPseudoBinaryV_VV,
- Sched<[WriteVSMulV, ReadVSMulV, ReadVSMulV, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX,
- Sched<[WriteVSMulX, ReadVSMulV, ReadVSMulX, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVSMulV_MX = !cast<SchedWrite>("WriteVSMulV_" # mx);
+ defvar WriteVSMulX_MX = !cast<SchedWrite>("WriteVSMulX_" # mx);
+ defvar ReadVSMulV_MX = !cast<SchedRead>("ReadVSMulV_" # mx);
+ defvar ReadVSMulX_MX = !cast<SchedRead>("ReadVSMulX_" # mx);
+
+ defm "" : VPseudoBinaryV_VV_LMUL<m>,
+ Sched<[WriteVSMulV_MX, ReadVSMulV_MX, ReadVSMulV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_VX_LMUL<m>,
+ Sched<[WriteVSMulX_MX, ReadVSMulV_MX, ReadVSMulX_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVAALU_VV_VX {
- defm "" : VPseudoBinaryV_VV,
- Sched<[WriteVAALUV, ReadVAALUV, ReadVAALUV, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX,
- Sched<[WriteVAALUX, ReadVAALUV, ReadVAALUX, ReadVMask]>;
+ foreach m = MxList in {
+ defvar mx = m.MX;
+ defvar WriteVAALUV_MX = !cast<SchedWrite>("WriteVAALUV_" # mx);
+ defvar WriteVAALUX_MX = !cast<SchedWrite>("WriteVAALUX_" # mx);
+ defvar ReadVAALUV_MX = !cast<SchedRead>("ReadVAALUV_" # mx);
+ defvar ReadVAALUX_MX = !cast<SchedRead>("ReadVAALUX_" # mx);
+
+ defm "" : VPseudoBinaryV_VV_LMUL<m>,
+ Sched<[WriteVAALUV_MX, ReadVAALUV_MX, ReadVAALUV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_VX_LMUL<m>,
+ Sched<[WriteVAALUX_MX, ReadVAALUV_MX, ReadVAALUX_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVMINMAX_VV_VX {
@@ -2777,12 +2819,21 @@ multiclass VPseudoVCALUM_V_X<string Constraint> {
}
multiclass VPseudoVNCLP_WV_WX_WI {
- defm "" : VPseudoBinaryV_WV,
- Sched<[WriteVNClipV, ReadVNClipV, ReadVNClipV, ReadVMask]>;
- defm "" : VPseudoBinaryV_WX,
- Sched<[WriteVNClipX, ReadVNClipV, ReadVNClipX, ReadVMask]>;
- defm "" : VPseudoBinaryV_WI,
- Sched<[WriteVNClipI, ReadVNClipV, ReadVMask]>;
+ foreach m = MxListW in {
+ defvar mx = m.MX;
+ defvar WriteVNClipV_MX = !cast<SchedWrite>("WriteVNClipV_" # mx);
+ defvar WriteVNClipX_MX = !cast<SchedWrite>("WriteVNClipX_" # mx);
+ defvar WriteVNClipI_MX = !cast<SchedWrite>("WriteVNClipI_" # mx);
+ defvar ReadVNClipV_MX = !cast<SchedRead>("ReadVNClipV_" # mx);
+ defvar ReadVNClipX_MX = !cast<SchedRead>("ReadVNClipX_" # mx);
+
+ defm "" : VPseudoBinaryV_WV_LMUL<m>,
+ Sched<[WriteVNClipV_MX, ReadVNClipV_MX, ReadVNClipV_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_WX_LMUL<m>,
+ Sched<[WriteVNClipX_MX, ReadVNClipV_MX, ReadVNClipX_MX, ReadVMask]>;
+ defm "" : VPseudoBinaryV_WI_LMUL<m>,
+ Sched<[WriteVNClipI_MX, ReadVNClipV_MX, ReadVMask]>;
+ }
}
multiclass VPseudoVNSHT_WV_WX_WI {
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index 616c6d2833340..2be04906419f5 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -166,23 +166,23 @@ defm "" : LMULSchedWrites<"WriteVIMovI">;
// 12. Vector Fixed-Point Arithmetic Instructions
// 12.1. Vector Single-Width Saturating Add and Subtract
-def WriteVSALUV : SchedWrite;
-def WriteVSALUX : SchedWrite;
-def WriteVSALUI : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVSALUV">;
+defm "" : LMULSchedWrites<"WriteVSALUX">;
+defm "" : LMULSchedWrites<"WriteVSALUI">;
// 12.2. Vector Single-Width Averaging Add and Subtract
-def WriteVAALUV : SchedWrite;
-def WriteVAALUX : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVAALUV">;
+defm "" : LMULSchedWrites<"WriteVAALUX">;
// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
-def WriteVSMulV : SchedWrite;
-def WriteVSMulX : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVSMulV">;
+defm "" : LMULSchedWrites<"WriteVSMulX">;
// 12.4. Vector Single-Width Scaling Shift Instructions
-def WriteVSShiftV : SchedWrite;
-def WriteVSShiftX : SchedWrite;
-def WriteVSShiftI : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVSShiftV">;
+defm "" : LMULSchedWrites<"WriteVSShiftX">;
+defm "" : LMULSchedWrites<"WriteVSShiftI">;
// 12.5. Vector Narrowing Fixed-Point Clip Instructions
-def WriteVNClipV : SchedWrite;
-def WriteVNClipX : SchedWrite;
-def WriteVNClipI : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVNClipV", SchedMxListW>;
+defm "" : LMULSchedWrites<"WriteVNClipX", SchedMxListW>;
+defm "" : LMULSchedWrites<"WriteVNClipI", SchedMxListW>;
// 13. Vector Floating-Point Instructions
// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
@@ -382,20 +382,20 @@ defm "" : LMULSchedReads<"ReadVIMovX">;
// 12. Vector Fixed-Point Arithmetic Instructions
// 12.1. Vector Single-Width Saturating Add and Subtract
-def ReadVSALUV : SchedRead;
-def ReadVSALUX : SchedRead;
+defm "" : LMULSchedReads<"ReadVSALUV">;
+defm "" : LMULSchedReads<"ReadVSALUX">;
// 12.2. Vector Single-Width Averaging Add and Subtract
-def ReadVAALUV : SchedRead;
-def ReadVAALUX : SchedRead;
+defm "" : LMULSchedReads<"ReadVAALUV">;
+defm "" : LMULSchedReads<"ReadVAALUX">;
// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
-def ReadVSMulV : SchedRead;
-def ReadVSMulX : SchedRead;
+defm "" : LMULSchedReads<"ReadVSMulV">;
+defm "" : LMULSchedReads<"ReadVSMulX">;
// 12.4. Vector Single-Width Scaling Shift Instructions
-def ReadVSShiftV : SchedRead;
-def ReadVSShiftX : SchedRead;
+defm "" : LMULSchedReads<"ReadVSShiftV">;
+defm "" : LMULSchedReads<"ReadVSShiftX">;
// 12.5. Vector Narrowing Fixed-Point Clip Instructions
-def ReadVNClipV : SchedRead;
-def ReadVNClipX : SchedRead;
+defm "" : LMULSchedReads<"ReadVNClipV", SchedMxListW>;
+defm "" : LMULSchedReads<"ReadVNClipX", SchedMxListW>;
// 13. Vector Floating-Point Instructions
// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
@@ -614,19 +614,19 @@ defm "" : LMULWriteRes<"WriteVIMovX", []>;
defm "" : LMULWriteRes<"WriteVIMovI", []>;
// 12. Vector Fixed-Point Arithmetic Instructions
-def : WriteRes<WriteVSALUV, []>;
-def : WriteRes<WriteVSALUX, []>;
-def : WriteRes<WriteVSALUI, []>;
-def : WriteRes<WriteVAALUV, []>;
-def : WriteRes<WriteVAALUX, []>;
-def : WriteRes<WriteVSMulV, []>;
-def : WriteRes<WriteVSMulX, []>;
-def : WriteRes<WriteVSShiftV, []>;
-def : WriteRes<WriteVSShiftX, []>;
-def : WriteRes<WriteVSShiftI, []>;
-def : WriteRes<WriteVNClipV, []>;
-def : WriteRes<WriteVNClipX, []>;
-def : WriteRes<WriteVNClipI, []>;
+defm "" : LMULWriteRes<"WriteVSALUV", []>;
+defm "" : LMULWriteRes<"WriteVSALUX", []>;
+defm "" : LMULWriteRes<"WriteVSALUI", []>;
+defm "" : LMULWriteRes<"WriteVAALUV", []>;
+defm "" : LMULWriteRes<"WriteVAALUX", []>;
+defm "" : LMULWriteRes<"WriteVSMulV", []>;
+defm "" : LMULWriteRes<"WriteVSMulX", []>;
+defm "" : LMULWriteRes<"WriteVSShiftV", []>;
+defm "" : LMULWriteRes<"WriteVSShiftX", []>;
+defm "" : LMULWriteRes<"WriteVSShiftI", []>;
+defm "" : LMULWriteRes<"WriteVNClipV", [], SchedMxListW>;
+defm "" : LMULWriteRes<"WriteVNClipX", [], SchedMxListW>;
+defm "" : LMULWriteRes<"WriteVNClipI", [], SchedMxListW>;
// 13. Vector Floating-Point Instructions
def : WriteRes<WriteVFALUV, []>;
@@ -765,16 +765,16 @@ defm "" : LMULReadAdvance<"ReadVIMovV", 0>;
defm "" : LMULReadAdvance<"ReadVIMovX", 0>;
// 12. Vector Fixed-Point Arithmetic Instructions
-def : ReadAdvance<ReadVSALUV, 0>;
-def : ReadAdvance<ReadVSALUX, 0>;
-def : ReadAdvance<ReadVAALUV, 0>;
-def : ReadAdvance<ReadVAALUX, 0>;
-def : ReadAdvance<ReadVSMulV, 0>;
-def : ReadAdvance<ReadVSMulX, 0>;
-def : ReadAdvance<ReadVSShiftV, 0>;
-def : ReadAdvance<ReadVSShiftX, 0>;
-def : ReadAdvance<ReadVNClipV, 0>;
-def : ReadAdvance<ReadVNClipX, 0>;
+defm "" : LMULReadAdvance<"ReadVSALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVSALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulV", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulX", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;
+defm "" : LMULReadAdvance<"ReadVNClipV", 0, SchedMxListW>;
+defm "" : LMULReadAdvance<"ReadVNClipX", 0, SchedMxListW>;
// 13. Vector Floating-Point Instructions
def : ReadAdvance<ReadVFALUV, 0>;
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