[PATCH] D138941: [RISCV][TTI] Account for constant materialization cost when costing airthmetic operations

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp:1028
+      // Two sub-cases:
+      // * Has a 12 bit immediate operand which can be splatted.
+      // * Has a larger immediate which must be materialized in scalar register
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Why 12 bit? If we're referring to vector instructions its 5 bits isn't it?


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  https://reviews.llvm.org/D138941/new/

https://reviews.llvm.org/D138941