[llvm] fac34c0 - AMDGPU: Bulk update some call tests to use opaque pointers
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 29 15:23:26 PST 2022
Author: Matt Arsenault
Date: 2022-11-29T18:10:38-05:00
New Revision: fac34c01f69f3591b6304953a15048ce6c5bd2b5
URL: https://github.com/llvm/llvm-project/commit/fac34c01f69f3591b6304953a15048ce6c5bd2b5
DIFF: https://github.com/llvm/llvm-project/commit/fac34c01f69f3591b6304953a15048ce6c5bd2b5.diff
LOG: AMDGPU: Bulk update some call tests to use opaque pointers
Added:
Modified:
llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll
llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
llvm/test/CodeGen/AMDGPU/call-argument-types.ll
llvm/test/CodeGen/AMDGPU/call-constant.ll
llvm/test/CodeGen/AMDGPU/call-constexpr.ll
llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
llvm/test/CodeGen/AMDGPU/call-return-types.ll
llvm/test/CodeGen/AMDGPU/call-to-kernel-undefined.ll
llvm/test/CodeGen/AMDGPU/call-to-kernel.ll
llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
llvm/test/CodeGen/AMDGPU/calling-conventions.ll
llvm/test/CodeGen/AMDGPU/inline-calls.ll
llvm/test/CodeGen/AMDGPU/nested-calls.ll
llvm/test/CodeGen/AMDGPU/sibling-call.ll
llvm/test/CodeGen/AMDGPU/stress-calls.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll
index 7d02f393dc6e..9bd0e3907bdf 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll
@@ -13,30 +13,30 @@ entry:
ret float %cond
}
-define coldcc void @foo_private_ptr(float addrspace(5)* nocapture %p) {
+define coldcc void @foo_private_ptr(ptr addrspace(5) nocapture %p) {
entry:
- %tmp1 = load float, float addrspace(5)* %p, align 4
+ %tmp1 = load float, ptr addrspace(5) %p, align 4
%cmp = fcmp ogt float %tmp1, 1.000000e+00
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
%div = fdiv float 1.000000e+00, %tmp1
- store float %div, float addrspace(5)* %p, align 4
+ store float %div, ptr addrspace(5) %p, align 4
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
-define coldcc void @foo_private_ptr2(float addrspace(5)* nocapture %p1, float addrspace(5)* nocapture %p2) {
+define coldcc void @foo_private_ptr2(ptr addrspace(5) nocapture %p1, ptr addrspace(5) nocapture %p2) {
entry:
- %tmp1 = load float, float addrspace(5)* %p1, align 4
+ %tmp1 = load float, ptr addrspace(5) %p1, align 4
%cmp = fcmp ogt float %tmp1, 1.000000e+00
br i1 %cmp, label %if.then, label %if.end
if.then:
%div = fdiv float 2.000000e+00, %tmp1
- store float %div, float addrspace(5)* %p2, align 4
+ store float %div, ptr addrspace(5) %p2, align 4
br label %if.end
if.end:
@@ -49,11 +49,11 @@ bb:
ret float %call
}
-define void @foo_noinline(float addrspace(5)* nocapture %p) #0 {
+define void @foo_noinline(ptr addrspace(5) nocapture %p) #0 {
entry:
- %tmp1 = load float, float addrspace(5)* %p, align 4
+ %tmp1 = load float, ptr addrspace(5) %p, align 4
%mul = fmul float %tmp1, 2.000000e+00
- store float %mul, float addrspace(5)* %p, align 4
+ store float %mul, ptr addrspace(5) %p, align 4
ret void
}
@@ -66,106 +66,106 @@ entry:
; GCN-MAXBB1: call coldcc void @foo_private_ptr2
; GCN: call void @foo_noinline(
; GCN: tail call float @_Z3sinf(
-define amdgpu_kernel void @test_inliner(float addrspace(1)* nocapture %a, i32 %n) {
+define amdgpu_kernel void @test_inliner(ptr addrspace(1) nocapture %a, i32 %n) {
entry:
%pvt_arr = alloca [64 x float], align 4, addrspace(5)
%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
- %arrayidx = getelementptr inbounds float, float addrspace(1)* %a, i32 %tid
- %tmp2 = load float, float addrspace(1)* %arrayidx, align 4
+ %arrayidx = getelementptr inbounds float, ptr addrspace(1) %a, i32 %tid
+ %tmp2 = load float, ptr addrspace(1) %arrayidx, align 4
%add = add i32 %tid, 1
- %arrayidx2 = getelementptr inbounds float, float addrspace(1)* %a, i32 %add
- %tmp5 = load float, float addrspace(1)* %arrayidx2, align 4
+ %arrayidx2 = getelementptr inbounds float, ptr addrspace(1) %a, i32 %add
+ %tmp5 = load float, ptr addrspace(1) %arrayidx2, align 4
%c1 = tail call coldcc float @foo(float %tmp2, float %tmp5)
%or = or i32 %tid, %n
- %arrayidx5 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %or
- store float %c1, float addrspace(5)* %arrayidx5, align 4
- %arrayidx7 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %or
- call coldcc void @foo_private_ptr(float addrspace(5)* %arrayidx7)
- %arrayidx8 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 1
- %arrayidx9 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 2
- call coldcc void @foo_private_ptr2(float addrspace(5)* %arrayidx8, float addrspace(5)* %arrayidx9)
- call void @foo_noinline(float addrspace(5)* %arrayidx7)
+ %arrayidx5 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 %or
+ store float %c1, ptr addrspace(5) %arrayidx5, align 4
+ %arrayidx7 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 %or
+ call coldcc void @foo_private_ptr(ptr addrspace(5) %arrayidx7)
+ %arrayidx8 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 1
+ %arrayidx9 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 2
+ call coldcc void @foo_private_ptr2(ptr addrspace(5) %arrayidx8, ptr addrspace(5) %arrayidx9)
+ call void @foo_noinline(ptr addrspace(5) %arrayidx7)
%and = and i32 %tid, %n
- %arrayidx11 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %and
- %tmp12 = load float, float addrspace(5)* %arrayidx11, align 4
+ %arrayidx11 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 %and
+ %tmp12 = load float, ptr addrspace(5) %arrayidx11, align 4
%c2 = call float @sin_wrapper(float %tmp12)
- store float %c2, float addrspace(5)* %arrayidx7, align 4
+ store float %c2, ptr addrspace(5) %arrayidx7, align 4
%xor = xor i32 %tid, %n
- %arrayidx16 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %xor
- %tmp16 = load float, float addrspace(5)* %arrayidx16, align 4
- store float %tmp16, float addrspace(1)* %arrayidx, align 4
+ %arrayidx16 = getelementptr inbounds [64 x float], ptr addrspace(5) %pvt_arr, i32 0, i32 %xor
+ %tmp16 = load float, ptr addrspace(5) %arrayidx16, align 4
+ store float %tmp16, ptr addrspace(1) %arrayidx, align 4
ret void
}
; GCN: define amdgpu_kernel void @test_inliner_multi_pvt_ptr(
; GCN-MAXBBDEF: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i
; GCN-MAXBB1: call coldcc void @foo_private_ptr2
-define amdgpu_kernel void @test_inliner_multi_pvt_ptr(float addrspace(1)* nocapture %a, i32 %n, float %v) {
+define amdgpu_kernel void @test_inliner_multi_pvt_ptr(ptr addrspace(1) nocapture %a, i32 %n, float %v) {
entry:
%pvt_arr1 = alloca [32 x float], align 4, addrspace(5)
%pvt_arr2 = alloca [32 x float], align 4, addrspace(5)
%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
- %arrayidx = getelementptr inbounds float, float addrspace(1)* %a, i32 %tid
+ %arrayidx = getelementptr inbounds float, ptr addrspace(1) %a, i32 %tid
%or = or i32 %tid, %n
- %arrayidx4 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %or
- %arrayidx5 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %or
- store float %v, float addrspace(5)* %arrayidx4, align 4
- store float %v, float addrspace(5)* %arrayidx5, align 4
- %arrayidx8 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 1
- %arrayidx9 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr2, i32 0, i32 2
- call coldcc void @foo_private_ptr2(float addrspace(5)* %arrayidx8, float addrspace(5)* %arrayidx9)
+ %arrayidx4 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr1, i32 0, i32 %or
+ %arrayidx5 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr2, i32 0, i32 %or
+ store float %v, ptr addrspace(5) %arrayidx4, align 4
+ store float %v, ptr addrspace(5) %arrayidx5, align 4
+ %arrayidx8 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr1, i32 0, i32 1
+ %arrayidx9 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr2, i32 0, i32 2
+ call coldcc void @foo_private_ptr2(ptr addrspace(5) %arrayidx8, ptr addrspace(5) %arrayidx9)
%xor = xor i32 %tid, %n
- %arrayidx15 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %xor
- %arrayidx16 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %xor
- %tmp15 = load float, float addrspace(5)* %arrayidx15, align 4
- %tmp16 = load float, float addrspace(5)* %arrayidx16, align 4
+ %arrayidx15 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr1, i32 0, i32 %xor
+ %arrayidx16 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr2, i32 0, i32 %xor
+ %tmp15 = load float, ptr addrspace(5) %arrayidx15, align 4
+ %tmp16 = load float, ptr addrspace(5) %arrayidx16, align 4
%tmp17 = fadd float %tmp15, %tmp16
- store float %tmp17, float addrspace(1)* %arrayidx, align 4
+ store float %tmp17, ptr addrspace(1) %arrayidx, align 4
ret void
}
; GCN: define amdgpu_kernel void @test_inliner_multi_pvt_ptr_cutoff(
; GCN-INL1: call coldcc void @foo_private_ptr2
; GCN-INLDEF: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i
-define amdgpu_kernel void @test_inliner_multi_pvt_ptr_cutoff(float addrspace(1)* nocapture %a, i32 %n, float %v) {
+define amdgpu_kernel void @test_inliner_multi_pvt_ptr_cutoff(ptr addrspace(1) nocapture %a, i32 %n, float %v) {
entry:
%pvt_arr1 = alloca [32 x float], align 4, addrspace(5)
%pvt_arr2 = alloca [33 x float], align 4, addrspace(5)
%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
- %arrayidx = getelementptr inbounds float, float addrspace(1)* %a, i32 %tid
+ %arrayidx = getelementptr inbounds float, ptr addrspace(1) %a, i32 %tid
%or = or i32 %tid, %n
- %arrayidx4 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %or
- %arrayidx5 = getelementptr inbounds [33 x float], [33 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %or
- store float %v, float addrspace(5)* %arrayidx4, align 4
- store float %v, float addrspace(5)* %arrayidx5, align 4
- %arrayidx8 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 1
- %arrayidx9 = getelementptr inbounds [33 x float], [33 x float] addrspace(5)* %pvt_arr2, i32 0, i32 2
- call coldcc void @foo_private_ptr2(float addrspace(5)* %arrayidx8, float addrspace(5)* %arrayidx9)
+ %arrayidx4 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr1, i32 0, i32 %or
+ %arrayidx5 = getelementptr inbounds [33 x float], ptr addrspace(5) %pvt_arr2, i32 0, i32 %or
+ store float %v, ptr addrspace(5) %arrayidx4, align 4
+ store float %v, ptr addrspace(5) %arrayidx5, align 4
+ %arrayidx8 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr1, i32 0, i32 1
+ %arrayidx9 = getelementptr inbounds [33 x float], ptr addrspace(5) %pvt_arr2, i32 0, i32 2
+ call coldcc void @foo_private_ptr2(ptr addrspace(5) %arrayidx8, ptr addrspace(5) %arrayidx9)
%xor = xor i32 %tid, %n
- %arrayidx15 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %xor
- %arrayidx16 = getelementptr inbounds [33 x float], [33 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %xor
- %tmp15 = load float, float addrspace(5)* %arrayidx15, align 4
- %tmp16 = load float, float addrspace(5)* %arrayidx16, align 4
+ %arrayidx15 = getelementptr inbounds [32 x float], ptr addrspace(5) %pvt_arr1, i32 0, i32 %xor
+ %arrayidx16 = getelementptr inbounds [33 x float], ptr addrspace(5) %pvt_arr2, i32 0, i32 %xor
+ %tmp15 = load float, ptr addrspace(5) %arrayidx15, align 4
+ %tmp16 = load float, ptr addrspace(5) %arrayidx16, align 4
%tmp17 = fadd float %tmp15, %tmp16
- store float %tmp17, float addrspace(1)* %arrayidx, align 4
+ store float %tmp17, ptr addrspace(1) %arrayidx, align 4
ret void
}
; GCN: define amdgpu_kernel void @test_inliner_maxbb_singlebb(
; GCN: tail call float @_Z3sinf
-define amdgpu_kernel void @test_inliner_maxbb_singlebb(float addrspace(1)* nocapture %a, i32 %n) {
+define amdgpu_kernel void @test_inliner_maxbb_singlebb(ptr addrspace(1) nocapture %a, i32 %n) {
entry:
%cmp = icmp eq i32 %n, 1
br i1 %cmp, label %bb.1, label %bb.2
br label %bb.1
bb.1:
- store float 1.0, float* undef
+ store float 1.0, ptr undef
br label %bb.2
bb.2:
%c = call float @sin_wrapper(float 1.0)
- store float %c, float addrspace(1)* %a
+ store float %c, ptr addrspace(1) %a
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
index 996d18c236c8..4d55d4974be7 100644
--- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
@@ -5,7 +5,7 @@
; through aliases. If GlobalOpt is never run, we do not see direct
; calls,
- at alias = hidden alias void (), void ()* @aliasee_default
+ at alias = hidden alias void (), ptr @aliasee_default
; ALL-LABEL: {{^}}kernel:
; GFX908: .amdhsa_next_free_vgpr 41
diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
index 38e97266d070..f3974844e0be 100644
--- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
@@ -4,7 +4,7 @@
; through aliases. If GlobalOpt is never run, we do not see direct
; calls,
- at alias0 = hidden alias void (), void ()* @aliasee_default_vgpr64_sgpr102
+ at alias0 = hidden alias void (), ptr @aliasee_default_vgpr64_sgpr102
; CHECK-LABEL: {{^}}kernel0:
; CHECK: .amdhsa_next_free_vgpr 53
diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
index 729e6dfc1cb7..5672cbb3f94f 100644
--- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
@@ -4,7 +4,7 @@
; through aliases. If GlobalOpt is never run, we do not see direct
; calls,
- at alias1 = hidden alias void (), void ()* @aliasee_vgpr32_sgpr76
+ at alias1 = hidden alias void (), ptr @aliasee_vgpr32_sgpr76
; The parent kernel has a higher VGPR usage than the possible callees.
diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
index c4c1c34e023a..6800cc42eb59 100644
--- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
@@ -4,7 +4,7 @@
; through aliases. If GlobalOpt is never run, we do not see direct
; calls,
- at alias2 = hidden alias void (), void()* @aliasee_vgpr64_sgpr102
+ at alias2 = hidden alias void (), ptr @aliasee_vgpr64_sgpr102
; CHECK-LABEL: {{^}}kernel2:
; CHECK: .amdhsa_next_free_vgpr 53
diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
index 39994929db56..deed0052a9a3 100644
--- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
@@ -4,7 +4,7 @@
; through aliases. If GlobalOpt is never run, we do not see direct
; calls,
- at alias3 = hidden alias void (), void ()* @aliasee_vgpr256_sgpr102
+ at alias3 = hidden alias void (), ptr @aliasee_vgpr256_sgpr102
; CHECK-LABEL: {{^}}kernel3:
; CHECK: .amdhsa_next_free_vgpr 253
diff --git a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
index 09c4633431dc..6f16dcb3c47d 100644
--- a/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-argument-types.ll
@@ -52,8 +52,8 @@ declare hidden i32 @external_i32_func_i32(i32) #0
; Structs
declare hidden void @external_void_func_struct_i8_i32({ i8, i32 }) #0
-declare hidden void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 })) #0
-declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret({ i8, i32 }), { i8, i32 } addrspace(5)* byval({ i8, i32 })) #0
+declare hidden void @external_void_func_byval_struct_i8_i32(ptr addrspace(5) byval({ i8, i32 })) #0
+declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32(ptr addrspace(5) sret({ i8, i32 }), ptr addrspace(5) byval({ i8, i32 })) #0
declare hidden void @external_void_func_v16i8(<16 x i8>) #0
@@ -91,7 +91,7 @@ define amdgpu_kernel void @test_call_external_void_func_i1_imm() #0 {
; GCN-NEXT: s_swappc_b64 s[30:31], s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 {
- %var = load volatile i1, i1 addrspace(1)* undef
+ %var = load volatile i1, ptr addrspace(1) undef
call void @external_void_func_i1_signext(i1 signext %var)
ret void
}
@@ -112,7 +112,7 @@ define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 {
; GCN-NEXT: s_swappc_b64 s[30:31], s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 {
- %var = load volatile i1, i1 addrspace(1)* undef
+ %var = load volatile i1, ptr addrspace(1) undef
call void @external_void_func_i1_zeroext(i1 zeroext %var)
ret void
}
@@ -147,7 +147,7 @@ define amdgpu_kernel void @test_call_external_void_func_i8_imm(i32) #0 {
; GCN: s_swappc_b64 s[30:31], s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i8_signext(i32) #0 {
- %var = load volatile i8, i8 addrspace(1)* undef
+ %var = load volatile i8, ptr addrspace(1) undef
call void @external_void_func_i8_signext(i8 signext %var)
ret void
}
@@ -165,7 +165,7 @@ define amdgpu_kernel void @test_call_external_void_func_i8_signext(i32) #0 {
; GCN: s_swappc_b64 s[30:31], s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i8_zeroext(i32) #0 {
- %var = load volatile i8, i8 addrspace(1)* undef
+ %var = load volatile i8, ptr addrspace(1) undef
call void @external_void_func_i8_zeroext(i8 zeroext %var)
ret void
}
@@ -194,7 +194,7 @@ define amdgpu_kernel void @test_call_external_void_func_i16_imm() #0 {
; GCN: s_swappc_b64 s[30:31], s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i16_signext(i32) #0 {
- %var = load volatile i16, i16 addrspace(1)* undef
+ %var = load volatile i16, ptr addrspace(1) undef
call void @external_void_func_i16_signext(i16 signext %var)
ret void
}
@@ -211,7 +211,7 @@ define amdgpu_kernel void @test_call_external_void_func_i16_signext(i32) #0 {
; GCN: s_swappc_b64 s[30:31], s[[[PC_LO]]:[[PC_HI]]]
; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i16_zeroext(i32) #0 {
- %var = load volatile i16, i16 addrspace(1)* undef
+ %var = load volatile i16, ptr addrspace(1) undef
call void @external_void_func_i16_zeroext(i16 zeroext %var)
ret void
}
@@ -249,7 +249,7 @@ define amdgpu_kernel void @test_call_external_void_func_i64_imm() #0 {
; GCN-NOT: s_waitcnt
; GCN: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_v2i64() #0 {
- %val = load <2 x i64>, <2 x i64> addrspace(1)* null
+ %val = load <2 x i64>, ptr addrspace(1) null
call void @external_void_func_v2i64(<2 x i64> %val)
ret void
}
@@ -272,7 +272,7 @@ define amdgpu_kernel void @test_call_external_void_func_v2i64_imm() #0 {
; GCN-NOT: s_waitcnt
; GCN: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_v3i64() #0 {
- %load = load <2 x i64>, <2 x i64> addrspace(1)* null
+ %load = load <2 x i64>, ptr addrspace(1) null
%val = shufflevector <2 x i64> %load, <2 x i64> <i64 8589934593, i64 undef>, <3 x i32> <i32 0, i32 1, i32 2>
call void @external_void_func_v3i64(<3 x i64> %val)
@@ -289,7 +289,7 @@ define amdgpu_kernel void @test_call_external_void_func_v3i64() #0 {
; GCN-NOT: s_waitcnt
; GCN: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_v4i64() #0 {
- %load = load <2 x i64>, <2 x i64> addrspace(1)* null
+ %load = load <2 x i64>, ptr addrspace(1) null
%val = shufflevector <2 x i64> %load, <2 x i64> <i64 8589934593, i64 17179869187>, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
call void @external_void_func_v4i64(<4 x i64> %val)
ret void
@@ -385,7 +385,7 @@ define amdgpu_kernel void @test_call_external_void_func_v3f64_imm() #0 {
; GFX9-NOT: v0
; GFX9: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_v2i16() #0 {
- %val = load <2 x i16>, <2 x i16> addrspace(1)* undef
+ %val = load <2 x i16>, ptr addrspace(1) undef
call void @external_void_func_v2i16(<2 x i16> %val)
ret void
}
@@ -396,7 +396,7 @@ define amdgpu_kernel void @test_call_external_void_func_v2i16() #0 {
; GFX9-NOT: v1
; GFX9: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_v3i16() #0 {
- %val = load <3 x i16>, <3 x i16> addrspace(1)* undef
+ %val = load <3 x i16>, ptr addrspace(1) undef
call void @external_void_func_v3i16(<3 x i16> %val)
ret void
}
@@ -407,7 +407,7 @@ define amdgpu_kernel void @test_call_external_void_func_v3i16() #0 {
; GFX9-NOT: v1
; GFX9: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_v3f16() #0 {
- %val = load <3 x half>, <3 x half> addrspace(1)* undef
+ %val = load <3 x half>, ptr addrspace(1) undef
call void @external_void_func_v3f16(<3 x half> %val)
ret void
}
@@ -436,7 +436,7 @@ define amdgpu_kernel void @test_call_external_void_func_v3f16_imm() #0 {
; GFX9-NOT: v1
; GFX9: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_v4i16() #0 {
- %val = load <4 x i16>, <4 x i16> addrspace(1)* undef
+ %val = load <4 x i16>, ptr addrspace(1) undef
call void @external_void_func_v4i16(<4 x i16> %val)
ret void
}
@@ -455,7 +455,7 @@ define amdgpu_kernel void @test_call_external_void_func_v4i16_imm() #0 {
; GFX9-NOT: v0
; GFX9: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_v2f16() #0 {
- %val = load <2 x half>, <2 x half> addrspace(1)* undef
+ %val = load <2 x half>, ptr addrspace(1) undef
call void @external_void_func_v2f16(<2 x half> %val)
ret void
}
@@ -465,7 +465,7 @@ define amdgpu_kernel void @test_call_external_void_func_v2f16() #0 {
; GCN-NOT: s_waitcnt
; GCN: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_v2i32() #0 {
- %val = load <2 x i32>, <2 x i32> addrspace(1)* undef
+ %val = load <2 x i32>, ptr addrspace(1) undef
call void @external_void_func_v2i32(<2 x i32> %val)
ret void
}
@@ -507,7 +507,7 @@ define amdgpu_kernel void @test_call_external_void_func_v3i32_i32(i32) #0 {
; GCN-NOT: s_waitcnt
; GCN: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_v4i32() #0 {
- %val = load <4 x i32>, <4 x i32> addrspace(1)* undef
+ %val = load <4 x i32>, ptr addrspace(1) undef
call void @external_void_func_v4i32(<4 x i32> %val)
ret void
}
@@ -542,8 +542,8 @@ define amdgpu_kernel void @test_call_external_void_func_v5i32_imm() #0 {
; GCN-NOT: s_waitcnt
; GCN: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_v8i32() #0 {
- %ptr = load <8 x i32> addrspace(1)*, <8 x i32> addrspace(1)* addrspace(4)* undef
- %val = load <8 x i32>, <8 x i32> addrspace(1)* %ptr
+ %ptr = load ptr addrspace(1), ptr addrspace(4) undef
+ %val = load <8 x i32>, ptr addrspace(1) %ptr
call void @external_void_func_v8i32(<8 x i32> %val)
ret void
}
@@ -571,8 +571,8 @@ define amdgpu_kernel void @test_call_external_void_func_v8i32_imm() #0 {
; GCN-NOT: s_waitcnt
; GCN: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_v16i32() #0 {
- %ptr = load <16 x i32> addrspace(1)*, <16 x i32> addrspace(1)* addrspace(4)* undef
- %val = load <16 x i32>, <16 x i32> addrspace(1)* %ptr
+ %ptr = load ptr addrspace(1), ptr addrspace(4) undef
+ %val = load <16 x i32>, ptr addrspace(1) %ptr
call void @external_void_func_v16i32(<16 x i32> %val)
ret void
}
@@ -589,8 +589,8 @@ define amdgpu_kernel void @test_call_external_void_func_v16i32() #0 {
; GCN: buffer_store_dword v31, off, s{{\[[0-9]+:[0-9]+\]}}, s32
; GCN: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_v32i32() #0 {
- %ptr = load <32 x i32> addrspace(1)*, <32 x i32> addrspace(1)* addrspace(4)* undef
- %val = load <32 x i32>, <32 x i32> addrspace(1)* %ptr
+ %ptr = load ptr addrspace(1), ptr addrspace(4) undef
+ %val = load <32 x i32>, ptr addrspace(1) %ptr
call void @external_void_func_v32i32(<32 x i32> %val)
ret void
}
@@ -616,9 +616,9 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32() #0 {
; GCN: s_swappc_b64
; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 {
- %ptr0 = load <32 x i32> addrspace(1)*, <32 x i32> addrspace(1)* addrspace(4)* undef
- %val0 = load <32 x i32>, <32 x i32> addrspace(1)* %ptr0
- %val1 = load i32, i32 addrspace(1)* undef
+ %ptr0 = load ptr addrspace(1), ptr addrspace(4) undef
+ %val0 = load <32 x i32>, ptr addrspace(1) %ptr0
+ %val1 = load i32, ptr addrspace(1) undef
call void @external_void_func_v32i32_i32(<32 x i32> %val0, i32 %val1)
ret void
}
@@ -628,9 +628,9 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 {
; GCN: s_swappc_b64 s[30:31],
; GCN-NOT: s_waitcnt
; GCN: buffer_store_dword v0, off, s[36:39], 0
-define amdgpu_kernel void @test_call_external_i32_func_i32_imm(i32 addrspace(1)* %out) #0 {
+define amdgpu_kernel void @test_call_external_i32_func_i32_imm(ptr addrspace(1) %out) #0 {
%val = call i32 @external_i32_func_i32(i32 42)
- store volatile i32 %val, i32 addrspace(1)* %out
+ store volatile i32 %val, ptr addrspace(1) %out
ret void
}
@@ -639,8 +639,8 @@ define amdgpu_kernel void @test_call_external_i32_func_i32_imm(i32 addrspace(1)*
; GCN: buffer_load_dword v1, off
; GCN: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 {
- %ptr0 = load { i8, i32 } addrspace(1)*, { i8, i32 } addrspace(1)* addrspace(4)* undef
- %val = load { i8, i32 }, { i8, i32 } addrspace(1)* %ptr0
+ %ptr0 = load ptr addrspace(1), ptr addrspace(4) undef
+ %val = load { i8, i32 }, ptr addrspace(1) %ptr0
call void @external_void_func_struct_i8_i32({ i8, i32 } %val)
ret void
}
@@ -672,11 +672,11 @@ define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 {
; GCN-NOT: [[SP]]
define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0 {
%val = alloca { i8, i32 }, align 4, addrspace(5)
- %gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %val, i32 0, i32 0
- %gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %val, i32 0, i32 1
- store i8 3, i8 addrspace(5)* %gep0
- store i32 8, i32 addrspace(5)* %gep1
- call void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %val)
+ %gep0 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %val, i32 0, i32 0
+ %gep1 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %val, i32 0, i32 1
+ store i8 3, ptr addrspace(5) %gep0
+ store i32 8, ptr addrspace(5) %gep1
+ call void @external_void_func_byval_struct_i8_i32(ptr addrspace(5) byval({ i8, i32 }) %val)
ret void
}
@@ -704,25 +704,25 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0
define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32(i32) #0 {
%in.val = alloca { i8, i32 }, align 4, addrspace(5)
%out.val = alloca { i8, i32 }, align 4, addrspace(5)
- %in.gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %in.val, i32 0, i32 0
- %in.gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %in.val, i32 0, i32 1
- store i8 3, i8 addrspace(5)* %in.gep0
- store i32 8, i32 addrspace(5)* %in.gep1
- call void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* %out.val, { i8, i32 } addrspace(5)* byval({ i8, i32 }) %in.val)
- %out.gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %out.val, i32 0, i32 0
- %out.gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %out.val, i32 0, i32 1
- %out.val0 = load i8, i8 addrspace(5)* %out.gep0
- %out.val1 = load i32, i32 addrspace(5)* %out.gep1
+ %in.gep0 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %in.val, i32 0, i32 0
+ %in.gep1 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %in.val, i32 0, i32 1
+ store i8 3, ptr addrspace(5) %in.gep0
+ store i32 8, ptr addrspace(5) %in.gep1
+ call void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32(ptr addrspace(5) %out.val, ptr addrspace(5) byval({ i8, i32 }) %in.val)
+ %out.gep0 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %out.val, i32 0, i32 0
+ %out.gep1 = getelementptr inbounds { i8, i32 }, ptr addrspace(5) %out.val, i32 0, i32 1
+ %out.val0 = load i8, ptr addrspace(5) %out.gep0
+ %out.val1 = load i32, ptr addrspace(5) %out.gep1
- store volatile i8 %out.val0, i8 addrspace(1)* undef
- store volatile i32 %out.val1, i32 addrspace(1)* undef
+ store volatile i8 %out.val0, ptr addrspace(1) undef
+ store volatile i32 %out.val1, ptr addrspace(1) undef
ret void
}
; GCN-LABEL: {{^}}test_call_external_void_func_v16i8:
define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {
- %ptr = load <16 x i8> addrspace(1)*, <16 x i8> addrspace(1)* addrspace(4)* undef
- %val = load <16 x i8>, <16 x i8> addrspace(1)* %ptr
+ %ptr = load ptr addrspace(1), ptr addrspace(4) undef
+ %val = load <16 x i8>, ptr addrspace(1) %ptr
call void @external_void_func_v16i8(<16 x i8> %val)
ret void
}
@@ -753,7 +753,7 @@ entry:
define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
entry:
%alloca = alloca double, align 8, addrspace(5)
- tail call void @byval_align16_f64_arg(<32 x i32> %val, double addrspace(5)* byval(double) align 16 %alloca)
+ tail call void @byval_align16_f64_arg(<32 x i32> %val, ptr addrspace(5) byval(double) align 16 %alloca)
ret void
}
@@ -902,7 +902,7 @@ entry:
ret void
}
-declare hidden void @byval_align16_f64_arg(<32 x i32>, double addrspace(5)* byval(double) align 16) #0
+declare hidden void @byval_align16_f64_arg(<32 x i32>, ptr addrspace(5) byval(double) align 16) #0
declare hidden void @stack_passed_f64_arg(<32 x i32>, double) #0
declare hidden void @external_void_func_12xv3i32(<3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>,
<3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>, <3 x i32>) #0
diff --git a/llvm/test/CodeGen/AMDGPU/call-constant.ll b/llvm/test/CodeGen/AMDGPU/call-constant.ll
index 1baa9fe259f0..90a52f89b6a8 100644
--- a/llvm/test/CodeGen/AMDGPU/call-constant.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-constant.ll
@@ -6,7 +6,7 @@
define amdgpu_kernel void @test_call_undef() #0 {
%val = call i32 undef(i32 1)
%op = add i32 %val, 1
- store volatile i32 %op, i32 addrspace(1)* undef
+ store volatile i32 %op, ptr addrspace(1) undef
ret void
}
@@ -26,7 +26,7 @@ define i32 @test_tail_call_undef() #0 {
define amdgpu_kernel void @test_call_null() #0 {
%val = call i32 null(i32 1)
%op = add i32 %val, 1
- store volatile i32 %op, i32 addrspace(1)* null
+ store volatile i32 %op, ptr addrspace(1) null
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/call-constexpr.ll b/llvm/test/CodeGen/AMDGPU/call-constexpr.ll
index 6de7928167a3..f1992d71eb1d 100644
--- a/llvm/test/CodeGen/AMDGPU/call-constexpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-constexpr.ll
@@ -6,18 +6,18 @@
; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ret_i32_noinline at rel32@hi+12
; GCN: s_swappc_b64
define amdgpu_kernel void @test_bitcast_return_type_noinline() #0 {
- %val = call float bitcast (i32()* @ret_i32_noinline to float()*)()
+ %val = call float @ret_i32_noinline()
%op = fadd float %val, 1.0
- store volatile float %op, float addrspace(1)* undef
+ store volatile float %op, ptr addrspace(1) undef
ret void
}
; GCN-LABEL: {{^}}test_bitcast_return_type_alwaysinline:
; GCN: s_swappc_b64
define amdgpu_kernel void @test_bitcast_return_type_alwaysinline() #0 {
- %val = call float bitcast (i32()* @ret_i32_alwaysinline to float()*)()
+ %val = call float @ret_i32_alwaysinline()
%op = fadd float %val, 1.0
- store volatile float %op, float addrspace(1)* undef
+ store volatile float %op, ptr addrspace(1) undef
ret void
}
@@ -27,9 +27,9 @@ define amdgpu_kernel void @test_bitcast_return_type_alwaysinline() #0 {
; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32 at rel32@hi+12
; GCN: s_swappc_b64
define amdgpu_kernel void @test_bitcast_argument_type() #0 {
- %val = call i32 bitcast (i32(i32)* @ident_i32 to i32(float)*)(float 2.0)
+ %val = call i32 @ident_i32(float 2.0)
%op = add i32 %val, 1
- store volatile i32 %op, i32 addrspace(1)* undef
+ store volatile i32 %op, ptr addrspace(1) undef
ret void
}
@@ -39,9 +39,9 @@ define amdgpu_kernel void @test_bitcast_argument_type() #0 {
; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32 at rel32@hi+12
; GCN: s_swappc_b64
define amdgpu_kernel void @test_bitcast_argument_and_return_types() #0 {
- %val = call float bitcast (i32(i32)* @ident_i32 to float(float)*)(float 2.0)
+ %val = call float @ident_i32(float 2.0)
%op = fadd float %val, 1.0
- store volatile float %op, float addrspace(1)* undef
+ store volatile float %op, ptr addrspace(1) undef
ret void
}
@@ -65,9 +65,9 @@ define hidden i32 @use_workitem_id_x(i32 %arg0) #0 {
; GCN: s_swappc_b64
; GCN: v_add_f32_e32
define amdgpu_kernel void @test_bitcast_use_workitem_id_x() #0 {
- %val = call float bitcast (i32(i32)* @use_workitem_id_x to float(i32)*)(i32 9)
+ %val = call float @use_workitem_id_x(i32 9)
%op = fadd float %val, 1.0
- store volatile float %op, float addrspace(1)* undef
+ store volatile float %op, ptr addrspace(1) undef
ret void
}
@@ -76,19 +76,19 @@ define amdgpu_kernel void @test_bitcast_use_workitem_id_x() #0 {
; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32 at rel32@lo+4
; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, ident_i32 at rel32@hi+12
; GCN: s_swappc_b64
- at _ZTIi = external global i8*
+ at _ZTIi = external global ptr
declare i32 @__gxx_personality_v0(...)
-define amdgpu_kernel void @test_invoke() #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
- %val = invoke float bitcast (i32(i32)* @ident_i32 to float(float)*)(float 2.0)
+define amdgpu_kernel void @test_invoke() #0 personality ptr @__gxx_personality_v0 {
+ %val = invoke float @ident_i32(float 2.0)
to label %continue unwind label %broken
broken:
- landingpad { i8*, i32 } catch i8** @_ZTIi
+ landingpad { ptr, i32 } catch ptr @_ZTIi
ret void
continue:
%op = fadd float %val, 1.0
- store volatile float %op, float addrspace(1)* undef
+ store volatile float %op, ptr addrspace(1) undef
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll b/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
index fe9743bc690c..faa83251f16c 100644
--- a/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
@@ -35,7 +35,7 @@ define void @indirect_use_vcc() #1 {
; VI-NOBUG: ; NumSgprs: 40
; VI-BUG: ; NumSgprs: 96
; GCN: ; NumVgprs: 41
-define amdgpu_kernel void @indirect_2level_use_vcc_kernel(i32 addrspace(1)* %out) #0 {
+define amdgpu_kernel void @indirect_2level_use_vcc_kernel(ptr addrspace(1) %out) #0 {
call void @indirect_use_vcc()
ret void
}
@@ -64,7 +64,7 @@ define void @indirect_use_flat_scratch() #1 {
; VI-NOBUG: ; NumSgprs: 40
; VI-BUG: ; NumSgprs: 96
; GCN: ; NumVgprs: 41
-define amdgpu_kernel void @indirect_2level_use_flat_scratch_kernel(i32 addrspace(1)* %out) #0 {
+define amdgpu_kernel void @indirect_2level_use_flat_scratch_kernel(ptr addrspace(1) %out) #0 {
call void @indirect_use_flat_scratch()
ret void
}
@@ -135,7 +135,7 @@ define amdgpu_kernel void @indirect_2_level_use_80_sgpr() #0 {
; GCN: ScratchSize: 2052
define void @use_stack0() #1 {
%alloca = alloca [512 x i32], align 4, addrspace(5)
- call void asm sideeffect "; use $0", "v"([512 x i32] addrspace(5)* %alloca) #0
+ call void asm sideeffect "; use $0", "v"(ptr addrspace(5) %alloca) #0
ret void
}
@@ -143,7 +143,7 @@ define void @use_stack0() #1 {
; GCN: ScratchSize: 404
define void @use_stack1() #1 {
%alloca = alloca [100 x i32], align 4, addrspace(5)
- call void asm sideeffect "; use $0", "v"([100 x i32] addrspace(5)* %alloca) #0
+ call void asm sideeffect "; use $0", "v"(ptr addrspace(5) %alloca) #0
ret void
}
@@ -151,7 +151,7 @@ define void @use_stack1() #1 {
; GCN: ScratchSize: 2132
define void @indirect_use_stack() #1 {
%alloca = alloca [16 x i32], align 4, addrspace(5)
- call void asm sideeffect "; use $0", "v"([16 x i32] addrspace(5)* %alloca) #0
+ call void asm sideeffect "; use $0", "v"(ptr addrspace(5) %alloca) #0
call void @use_stack0()
ret void
}
@@ -213,7 +213,7 @@ define amdgpu_kernel void @usage_external_recurse() #0 {
; GCN-V5: ScratchSize: 2064{{$}}
define void @direct_recursion_use_stack(i32 %val) #2 {
%alloca = alloca [512 x i32], align 4, addrspace(5)
- call void asm sideeffect "; use $0", "v"([512 x i32] addrspace(5)* %alloca) #0
+ call void asm sideeffect "; use $0", "v"(ptr addrspace(5) %alloca) #0
%cmp = icmp eq i32 %val, 0
br i1 %cmp, label %ret, label %call
diff --git a/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll b/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
index c32354dd7f12..e9a82ebae7a8 100644
--- a/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
@@ -104,11 +104,11 @@ define hidden void @void_func_void_clobber_vcc() #2 {
; GCN-NEXT: s_addc_u32
; GCN-NEXT: s_swappc_b64
; GCN: s_mov_b64 vcc, s[34:35]
-define amdgpu_kernel void @test_call_void_func_void_clobber_vcc(i32 addrspace(1)* %out) #0 {
+define amdgpu_kernel void @test_call_void_func_void_clobber_vcc(ptr addrspace(1) %out) #0 {
%vcc = call i64 asm sideeffect "; def $0", "={vcc}"()
call void @void_func_void_clobber_vcc()
- %val0 = load volatile i32, i32 addrspace(1)* undef
- %val1 = load volatile i32, i32 addrspace(1)* undef
+ %val0 = load volatile i32, ptr addrspace(1) undef
+ %val1 = load volatile i32, ptr addrspace(1) undef
call void asm sideeffect "; use $0", "{vcc}"(i64 %vcc)
ret void
}
@@ -117,7 +117,7 @@ define amdgpu_kernel void @test_call_void_func_void_clobber_vcc(i32 addrspace(1)
; GCN: s_mov_b32 s33, s31
; GCN: s_swappc_b64
; GCN-NEXT: s_mov_b32 s31, s33
-define amdgpu_kernel void @test_call_void_func_void_mayclobber_s31(i32 addrspace(1)* %out) #0 {
+define amdgpu_kernel void @test_call_void_func_void_mayclobber_s31(ptr addrspace(1) %out) #0 {
%s31 = call i32 asm sideeffect "; def $0", "={s31}"()
call void @external_void_func_void()
call void asm sideeffect "; use $0", "{s31}"(i32 %s31)
@@ -128,7 +128,7 @@ define amdgpu_kernel void @test_call_void_func_void_mayclobber_s31(i32 addrspace
; GCN: v_mov_b32_e32 v40, v31
; GCN: s_swappc_b64
; GCN-NEXT: v_mov_b32_e32 v31, v40
-define amdgpu_kernel void @test_call_void_func_void_mayclobber_v31(i32 addrspace(1)* %out) #0 {
+define amdgpu_kernel void @test_call_void_func_void_mayclobber_v31(ptr addrspace(1) %out) #0 {
%v31 = call i32 asm sideeffect "; def $0", "={v31}"()
call void @external_void_func_void()
call void asm sideeffect "; use $0", "{v31}"(i32 %v31)
@@ -154,7 +154,7 @@ define amdgpu_kernel void @test_call_void_func_void_mayclobber_v31(i32 addrspace
; GCN-NEXT: ;;#ASMEND
; GCN-NOT: s33
; GCN-NEXT: s_endpgm
-define amdgpu_kernel void @test_call_void_func_void_preserves_s33(i32 addrspace(1)* %out) #0 {
+define amdgpu_kernel void @test_call_void_func_void_preserves_s33(ptr addrspace(1) %out) #0 {
%s33 = call i32 asm sideeffect "; def $0", "={s33}"()
call void @external_void_func_void()
call void asm sideeffect "; use $0", "{s33}"(i32 %s33)
@@ -187,7 +187,7 @@ define amdgpu_kernel void @test_call_void_func_void_preserves_s33(i32 addrspace(
; GCN-NEXT: ; use s34
; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: s_endpgm
-define amdgpu_kernel void @test_call_void_func_void_preserves_s34(i32 addrspace(1)* %out) #0 {
+define amdgpu_kernel void @test_call_void_func_void_preserves_s34(ptr addrspace(1) %out) #0 {
%s34 = call i32 asm sideeffect "; def $0", "={s34}"()
call void @external_void_func_void()
call void asm sideeffect "; use $0", "{s34}"(i32 %s34)
@@ -219,7 +219,7 @@ define amdgpu_kernel void @test_call_void_func_void_preserves_s34(i32 addrspace(
; GCN-NEXT: ; use v40
; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: s_endpgm
-define amdgpu_kernel void @test_call_void_func_void_preserves_v40(i32 addrspace(1)* %out) #0 {
+define amdgpu_kernel void @test_call_void_func_void_preserves_v40(ptr addrspace(1) %out) #0 {
%v40 = call i32 asm sideeffect "; def $0", "={v40}"()
call void @external_void_func_void()
call void asm sideeffect "; use $0", "{v40}"(i32 %v40)
diff --git a/llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll b/llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
index d198c0a6fa7c..c62a08245910 100644
--- a/llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
@@ -7,7 +7,7 @@
declare hidden void @callee() #0
-define amdgpu_kernel void @known_x_0(i32 addrspace(1)* %out) !reqd_work_group_size !0 {
+define amdgpu_kernel void @known_x_0(ptr addrspace(1) %out) !reqd_work_group_size !0 {
; CHECK-LABEL: known_x_0:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_add_u32 flat_scratch_lo, s6, s9
@@ -27,7 +27,7 @@ define amdgpu_kernel void @known_x_0(i32 addrspace(1)* %out) !reqd_work_group_si
}
; CHECK: .amdhsa_system_vgpr_workitem_id 2
-define amdgpu_kernel void @known_y_0(i32 addrspace(1)* %out) !reqd_work_group_size !1 {
+define amdgpu_kernel void @known_y_0(ptr addrspace(1) %out) !reqd_work_group_size !1 {
; CHECK-LABEL: known_y_0:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_add_u32 flat_scratch_lo, s6, s9
@@ -46,7 +46,7 @@ define amdgpu_kernel void @known_y_0(i32 addrspace(1)* %out) !reqd_work_group_si
}
; CHECK: .amdhsa_system_vgpr_workitem_id 2
-define amdgpu_kernel void @known_z_0(i32 addrspace(1)* %out) !reqd_work_group_size !2 {
+define amdgpu_kernel void @known_z_0(ptr addrspace(1) %out) !reqd_work_group_size !2 {
; CHECK-LABEL: known_z_0:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_add_u32 flat_scratch_lo, s6, s9
@@ -65,7 +65,7 @@ define amdgpu_kernel void @known_z_0(i32 addrspace(1)* %out) !reqd_work_group_si
}
; CHECK: .amdhsa_system_vgpr_workitem_id 1
-define amdgpu_kernel void @known_yz_0(i32 addrspace(1)* %out) !reqd_work_group_size !3 {
+define amdgpu_kernel void @known_yz_0(ptr addrspace(1) %out) !reqd_work_group_size !3 {
; CHECK-LABEL: known_yz_0:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_add_u32 flat_scratch_lo, s6, s9
@@ -84,7 +84,7 @@ define amdgpu_kernel void @known_yz_0(i32 addrspace(1)* %out) !reqd_work_group_s
}
; CHECK: .amdhsa_system_vgpr_workitem_id 0
-define amdgpu_kernel void @known_xz_0(i32 addrspace(1)* %out) !reqd_work_group_size !4 {
+define amdgpu_kernel void @known_xz_0(ptr addrspace(1) %out) !reqd_work_group_size !4 {
; CHECK-LABEL: known_xz_0:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_add_u32 flat_scratch_lo, s6, s9
@@ -104,7 +104,7 @@ define amdgpu_kernel void @known_xz_0(i32 addrspace(1)* %out) !reqd_work_group_s
; CHECK: .amdhsa_system_vgpr_workitem_id 1
-define amdgpu_kernel void @known_xyz_0(i32 addrspace(1)* %out) !reqd_work_group_size !5 {
+define amdgpu_kernel void @known_xyz_0(ptr addrspace(1) %out) !reqd_work_group_size !5 {
; CHECK-LABEL: known_xyz_0:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_add_u32 flat_scratch_lo, s6, s9
diff --git a/llvm/test/CodeGen/AMDGPU/call-return-types.ll b/llvm/test/CodeGen/AMDGPU/call-return-types.ll
index 33b201bbe6d8..faa20f732b1a 100644
--- a/llvm/test/CodeGen/AMDGPU/call-return-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-return-types.ll
@@ -59,7 +59,7 @@ define amdgpu_kernel void @test_call_external_void_func_void_x2() #0 {
; GCN-LABEL: {{^}}test_call_external_i1_func_void:
define amdgpu_kernel void @test_call_external_i1_func_void() #0 {
%val = call i1 @external_i1_func_void()
- store volatile i1 %val, i1 addrspace(1)* undef
+ store volatile i1 %val, ptr addrspace(1) undef
ret void
}
@@ -67,7 +67,7 @@ define amdgpu_kernel void @test_call_external_i1_func_void() #0 {
define amdgpu_kernel void @test_call_external_i1_zeroext_func_void() #0 {
%val = call i1 @external_i1_zeroext_func_void()
%val.ext = zext i1 %val to i32
- store volatile i32 %val.ext, i32 addrspace(1)* undef
+ store volatile i32 %val.ext, ptr addrspace(1) undef
ret void
}
@@ -75,14 +75,14 @@ define amdgpu_kernel void @test_call_external_i1_zeroext_func_void() #0 {
define amdgpu_kernel void @test_call_external_i1_signext_func_void() #0 {
%val = call i1 @external_i1_signext_func_void()
%val.ext = zext i1 %val to i32
- store volatile i32 %val.ext, i32 addrspace(1)* undef
+ store volatile i32 %val.ext, ptr addrspace(1) undef
ret void
}
; GCN-LABEL: {{^}}test_call_external_i8_func_void:
define amdgpu_kernel void @test_call_external_i8_func_void() #0 {
%val = call i8 @external_i8_func_void()
- store volatile i8 %val, i8 addrspace(1)* undef
+ store volatile i8 %val, ptr addrspace(1) undef
ret void
}
@@ -90,7 +90,7 @@ define amdgpu_kernel void @test_call_external_i8_func_void() #0 {
define amdgpu_kernel void @test_call_external_i8_zeroext_func_void() #0 {
%val = call i8 @external_i8_zeroext_func_void()
%val.ext = zext i8 %val to i32
- store volatile i32 %val.ext, i32 addrspace(1)* undef
+ store volatile i32 %val.ext, ptr addrspace(1) undef
ret void
}
@@ -98,14 +98,14 @@ define amdgpu_kernel void @test_call_external_i8_zeroext_func_void() #0 {
define amdgpu_kernel void @test_call_external_i8_signext_func_void() #0 {
%val = call i8 @external_i8_signext_func_void()
%val.ext = zext i8 %val to i32
- store volatile i32 %val.ext, i32 addrspace(1)* undef
+ store volatile i32 %val.ext, ptr addrspace(1) undef
ret void
}
; GCN-LABEL: {{^}}test_call_external_i16_func_void:
define amdgpu_kernel void @test_call_external_i16_func_void() #0 {
%val = call i16 @external_i16_func_void()
- store volatile i16 %val, i16 addrspace(1)* undef
+ store volatile i16 %val, ptr addrspace(1) undef
ret void
}
@@ -113,7 +113,7 @@ define amdgpu_kernel void @test_call_external_i16_func_void() #0 {
define amdgpu_kernel void @test_call_external_i16_zeroext_func_void() #0 {
%val = call i16 @external_i16_zeroext_func_void()
%val.ext = zext i16 %val to i32
- store volatile i32 %val.ext, i32 addrspace(1)* undef
+ store volatile i32 %val.ext, ptr addrspace(1) undef
ret void
}
@@ -121,56 +121,56 @@ define amdgpu_kernel void @test_call_external_i16_zeroext_func_void() #0 {
define amdgpu_kernel void @test_call_external_i16_signext_func_void() #0 {
%val = call i16 @external_i16_signext_func_void()
%val.ext = zext i16 %val to i32
- store volatile i32 %val.ext, i32 addrspace(1)* undef
+ store volatile i32 %val.ext, ptr addrspace(1) undef
ret void
}
; GCN-LABEL: {{^}}test_call_external_i32_func_void:
define amdgpu_kernel void @test_call_external_i32_func_void() #0 {
%val = call i32 @external_i32_func_void()
- store volatile i32 %val, i32 addrspace(1)* undef
+ store volatile i32 %val, ptr addrspace(1) undef
ret void
}
; GCN-LABEL: {{^}}test_call_external_i64_func_void:
define amdgpu_kernel void @test_call_external_i64_func_void() #0 {
%val = call i64 @external_i64_func_void()
- store volatile i64 %val, i64 addrspace(1)* undef
+ store volatile i64 %val, ptr addrspace(1) undef
ret void
}
; GCN-LABEL: {{^}}test_call_external_f16_func_void:
define amdgpu_kernel void @test_call_external_f16_func_void() #0 {
%val = call half @external_f16_func_void()
- store volatile half %val, half addrspace(1)* undef
+ store volatile half %val, ptr addrspace(1) undef
ret void
}
; GCN-LABEL: {{^}}test_call_external_f32_func_void:
define amdgpu_kernel void @test_call_external_f32_func_void() #0 {
%val = call float @external_f32_func_void()
- store volatile float %val, float addrspace(1)* undef
+ store volatile float %val, ptr addrspace(1) undef
ret void
}
; GCN-LABEL: {{^}}test_call_external_f64_func_void:
define amdgpu_kernel void @test_call_external_f64_func_void() #0 {
%val = call double @external_f64_func_void()
- store volatile double %val, double addrspace(1)* undef
+ store volatile double %val, ptr addrspace(1) undef
ret void
}
; GCN-LABEL: {{^}}test_call_external_v2f64_func_void:
define amdgpu_kernel void @test_call_external_v2f64_func_void() #0 {
%val = call <2 x double> @external_v2f64_func_void()
- store volatile <2 x double> %val, <2 x double> addrspace(1)* undef
+ store volatile <2 x double> %val, ptr addrspace(1) undef
ret void
}
; GCN-LABEL: {{^}}test_call_external_v2i32_func_void:
define amdgpu_kernel void @test_call_external_v2i32_func_void() #0 {
%val = call <2 x i32> @external_v2i32_func_void()
- store volatile <2 x i32> %val, <2 x i32> addrspace(1)* undef
+ store volatile <2 x i32> %val, ptr addrspace(1) undef
ret void
}
@@ -180,14 +180,14 @@ define amdgpu_kernel void @test_call_external_v2i32_func_void() #0 {
; GFX89-DAG: buffer_store_dwordx3 v[0:2]
define amdgpu_kernel void @test_call_external_v3i32_func_void() #0 {
%val = call <3 x i32> @external_v3i32_func_void()
- store volatile <3 x i32> %val, <3 x i32> addrspace(1)* undef, align 8
+ store volatile <3 x i32> %val, ptr addrspace(1) undef, align 8
ret void
}
; GCN-LABEL: {{^}}test_call_external_v4i32_func_void:
define amdgpu_kernel void @test_call_external_v4i32_func_void() #0 {
%val = call <4 x i32> @external_v4i32_func_void()
- store volatile <4 x i32> %val, <4 x i32> addrspace(1)* undef, align 8
+ store volatile <4 x i32> %val, ptr addrspace(1) undef, align 8
ret void
}
@@ -199,56 +199,56 @@ define amdgpu_kernel void @test_call_external_v4i32_func_void() #0 {
; GFX89-DAG: buffer_store_dword v4
define amdgpu_kernel void @test_call_external_v5i32_func_void() #0 {
%val = call <5 x i32> @external_v5i32_func_void()
- store volatile <5 x i32> %val, <5 x i32> addrspace(1)* undef, align 8
+ store volatile <5 x i32> %val, ptr addrspace(1) undef, align 8
ret void
}
; GCN-LABEL: {{^}}test_call_external_v8i32_func_void:
define amdgpu_kernel void @test_call_external_v8i32_func_void() #0 {
%val = call <8 x i32> @external_v8i32_func_void()
- store volatile <8 x i32> %val, <8 x i32> addrspace(1)* undef, align 8
+ store volatile <8 x i32> %val, ptr addrspace(1) undef, align 8
ret void
}
; GCN-LABEL: {{^}}test_call_external_v16i32_func_void:
define amdgpu_kernel void @test_call_external_v16i32_func_void() #0 {
%val = call <16 x i32> @external_v16i32_func_void()
- store volatile <16 x i32> %val, <16 x i32> addrspace(1)* undef, align 8
+ store volatile <16 x i32> %val, ptr addrspace(1) undef, align 8
ret void
}
; GCN-LABEL: {{^}}test_call_external_v32i32_func_void:
define amdgpu_kernel void @test_call_external_v32i32_func_void() #0 {
%val = call <32 x i32> @external_v32i32_func_void()
- store volatile <32 x i32> %val, <32 x i32> addrspace(1)* undef, align 8
+ store volatile <32 x i32> %val, ptr addrspace(1) undef, align 8
ret void
}
; GCN-LABEL: {{^}}test_call_external_v2i16_func_void:
define amdgpu_kernel void @test_call_external_v2i16_func_void() #0 {
%val = call <2 x i16> @external_v2i16_func_void()
- store volatile <2 x i16> %val, <2 x i16> addrspace(1)* undef
+ store volatile <2 x i16> %val, ptr addrspace(1) undef
ret void
}
; GCN-LABEL: {{^}}test_call_external_v4i16_func_void:
define amdgpu_kernel void @test_call_external_v4i16_func_void() #0 {
%val = call <4 x i16> @external_v4i16_func_void()
- store volatile <4 x i16> %val, <4 x i16> addrspace(1)* undef
+ store volatile <4 x i16> %val, ptr addrspace(1) undef
ret void
}
; GCN-LABEL: {{^}}test_call_external_v2f16_func_void:
define amdgpu_kernel void @test_call_external_v2f16_func_void() #0 {
%val = call <2 x half> @external_v2f16_func_void()
- store volatile <2 x half> %val, <2 x half> addrspace(1)* undef
+ store volatile <2 x half> %val, ptr addrspace(1) undef
ret void
}
; GCN-LABEL: {{^}}test_call_external_v4f16_func_void:
define amdgpu_kernel void @test_call_external_v4f16_func_void() #0 {
%val = call <4 x half> @external_v4f16_func_void()
- store volatile <4 x half> %val, <4 x half> addrspace(1)* undef
+ store volatile <4 x half> %val, ptr addrspace(1) undef
ret void
}
@@ -260,7 +260,7 @@ define amdgpu_kernel void @test_call_external_v2i24_func_void() #0 {
%elt0 = extractelement <2 x i24> %val, i32 0
%elt1 = extractelement <2 x i24> %val, i32 1
%add = add i24 %elt0, %elt1
- store volatile i24 %add, i24 addrspace(1)* undef
+ store volatile i24 %add, ptr addrspace(1) undef
ret void
}
@@ -270,7 +270,7 @@ define amdgpu_kernel void @test_call_external_v2i24_func_void() #0 {
; GFX89-DAG: buffer_store_dwordx3 v[0:2]
define amdgpu_kernel void @test_call_external_v3f32_func_void() #0 {
%val = call <3 x float> @external_v3f32_func_void()
- store volatile <3 x float> %val, <3 x float> addrspace(1)* undef
+ store volatile <3 x float> %val, ptr addrspace(1) undef
ret void
}
@@ -282,7 +282,7 @@ define amdgpu_kernel void @test_call_external_v3f32_func_void() #0 {
; GFX89-DAG: buffer_store_dword v4
define amdgpu_kernel void @test_call_external_v5f32_func_void() #0 {
%val = call <5 x float> @external_v5f32_func_void()
- store volatile <5 x float> %val, <5 x float> addrspace(1)* undef
+ store volatile <5 x float> %val, ptr addrspace(1) undef
ret void
}
@@ -291,8 +291,8 @@ define amdgpu_kernel void @test_call_external_i32_i64_func_void() #0 {
%val = call { i32, i64 } @external_i32_i64_func_void()
%val.0 = extractvalue { i32, i64 } %val, 0
%val.1 = extractvalue { i32, i64 } %val, 1
- store volatile i32 %val.0, i32 addrspace(1)* undef
- store volatile i64 %val.1, i64 addrspace(1)* undef
+ store volatile i32 %val.0, ptr addrspace(1) undef
+ store volatile i64 %val.1, ptr addrspace(1) undef
ret void
}
@@ -302,8 +302,8 @@ define amdgpu_kernel void @test_call_external_v32i32_i32_func_void() #0 {
%val = call { <32 x i32>, i32 } @external_v32i32_i32_func_void()
%val0 = extractvalue { <32 x i32>, i32 } %val, 0
%val1 = extractvalue { <32 x i32>, i32 } %val, 1
- store volatile <32 x i32> %val0, <32 x i32> addrspace(1)* undef, align 8
- store volatile i32 %val1, i32 addrspace(1)* undef
+ store volatile <32 x i32> %val0, ptr addrspace(1) undef, align 8
+ store volatile i32 %val1, ptr addrspace(1) undef
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/call-to-kernel-undefined.ll b/llvm/test/CodeGen/AMDGPU/call-to-kernel-undefined.ll
index 1c5da794a5f3..4a0fa85be443 100644
--- a/llvm/test/CodeGen/AMDGPU/call-to-kernel-undefined.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-to-kernel-undefined.ll
@@ -2,18 +2,18 @@
; FIXME: It should be invalid IR to have a call to a kernel, but this
; is currently relied on, but should be eliminated before codegen.
-define amdgpu_kernel void @callee_kernel(i32 addrspace(1)* %out) #0 {
+define amdgpu_kernel void @callee_kernel(ptr addrspace(1) %out) #0 {
entry:
- store volatile i32 0, i32 addrspace(1)* %out
+ store volatile i32 0, ptr addrspace(1) %out
ret void
}
; Make sure there's no crash when the callsite calling convention
; doesn't match.
; CHECK: LLVM ERROR: invalid call to entry function
-define amdgpu_kernel void @caller_kernel(i32 addrspace(1)* %out) #0 {
+define amdgpu_kernel void @caller_kernel(ptr addrspace(1) %out) #0 {
entry:
- call void @callee_kernel(i32 addrspace(1)* %out)
+ call void @callee_kernel(ptr addrspace(1) %out)
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/call-to-kernel.ll b/llvm/test/CodeGen/AMDGPU/call-to-kernel.ll
index 24b019ccefe3..1ff00717080c 100644
--- a/llvm/test/CodeGen/AMDGPU/call-to-kernel.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-to-kernel.ll
@@ -2,16 +2,16 @@
; FIXME: It should be invalid IR to have a call to a kernel, but this
; is currently relied on, but should be eliminated before codegen.
-define amdgpu_kernel void @callee_kernel(i32 addrspace(1)* %out) #0 {
+define amdgpu_kernel void @callee_kernel(ptr addrspace(1) %out) #0 {
entry:
- store volatile i32 0, i32 addrspace(1)* %out
+ store volatile i32 0, ptr addrspace(1) %out
ret void
}
; CHECK: LLVM ERROR: Unsupported calling convention for call
-define amdgpu_kernel void @caller_kernel(i32 addrspace(1)* %out) #0 {
+define amdgpu_kernel void @caller_kernel(ptr addrspace(1) %out) #0 {
entry:
- call amdgpu_kernel void @callee_kernel(i32 addrspace(1)* %out)
+ call amdgpu_kernel void @callee_kernel(ptr addrspace(1) %out)
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/call-waitcnt.ll b/llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
index 516657b9560e..c0ba343d1dd3 100644
--- a/llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; Load argument depends on waitcnt which should be skipped.
-define amdgpu_kernel void @call_memory_arg_load(i32 addrspace(3)* %ptr, i32) #0 {
+define amdgpu_kernel void @call_memory_arg_load(ptr addrspace(3) %ptr, i32) #0 {
; GCN-LABEL: call_memory_arg_load:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dword s6, s[6:7], 0x0
@@ -20,13 +20,13 @@ define amdgpu_kernel void @call_memory_arg_load(i32 addrspace(3)* %ptr, i32) #0
; GCN-NEXT: s_addc_u32 s9, s9, func at rel32@hi+12
; GCN-NEXT: s_swappc_b64 s[30:31], s[8:9]
; GCN-NEXT: s_endpgm
- %vgpr = load volatile i32, i32 addrspace(3)* %ptr
+ %vgpr = load volatile i32, ptr addrspace(3) %ptr
call void @func(i32 %vgpr)
ret void
}
; Memory waitcnt with no register dependence on the call
-define amdgpu_kernel void @call_memory_no_dep(i32 addrspace(1)* %ptr, i32) #0 {
+define amdgpu_kernel void @call_memory_no_dep(ptr addrspace(1) %ptr, i32) #0 {
; GCN-LABEL: call_memory_no_dep:
; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0
@@ -45,13 +45,13 @@ define amdgpu_kernel void @call_memory_no_dep(i32 addrspace(1)* %ptr, i32) #0 {
; GCN-NEXT: s_addc_u32 s9, s9, func at rel32@hi+12
; GCN-NEXT: s_swappc_b64 s[30:31], s[8:9]
; GCN-NEXT: s_endpgm
- store i32 0, i32 addrspace(1)* %ptr
+ store i32 0, ptr addrspace(1) %ptr
call void @func(i32 0)
ret void
}
; Should not wait after the call before memory
-define amdgpu_kernel void @call_no_wait_after_call(i32 addrspace(1)* %ptr, i32) #0 {
+define amdgpu_kernel void @call_no_wait_after_call(ptr addrspace(1) %ptr, i32) #0 {
; GCN-LABEL: call_no_wait_after_call:
; GCN: ; %bb.0:
; GCN-NEXT: s_add_u32 flat_scratch_lo, s8, s11
@@ -70,11 +70,11 @@ define amdgpu_kernel void @call_no_wait_after_call(i32 addrspace(1)* %ptr, i32)
; GCN-NEXT: global_store_dword v40, v40, s[34:35]
; GCN-NEXT: s_endpgm
call void @func(i32 0)
- store i32 0, i32 addrspace(1)* %ptr
+ store i32 0, ptr addrspace(1) %ptr
ret void
}
-define amdgpu_kernel void @call_no_wait_after_call_return_val(i32 addrspace(1)* %ptr, i32) #0 {
+define amdgpu_kernel void @call_no_wait_after_call_return_val(ptr addrspace(1) %ptr, i32) #0 {
; GCN-LABEL: call_no_wait_after_call_return_val:
; GCN: ; %bb.0:
; GCN-NEXT: s_add_u32 flat_scratch_lo, s8, s11
@@ -93,12 +93,12 @@ define amdgpu_kernel void @call_no_wait_after_call_return_val(i32 addrspace(1)*
; GCN-NEXT: global_store_dword v40, v0, s[34:35]
; GCN-NEXT: s_endpgm
%rv = call i32 @func.return(i32 0)
- store i32 %rv, i32 addrspace(1)* %ptr
+ store i32 %rv, ptr addrspace(1) %ptr
ret void
}
; Need to wait for the address dependency
-define amdgpu_kernel void @call_got_load(i32 addrspace(1)* %ptr, i32) #0 {
+define amdgpu_kernel void @call_got_load(ptr addrspace(1) %ptr, i32) #0 {
; GCN-LABEL: call_got_load:
; GCN: ; %bb.0:
; GCN-NEXT: s_add_u32 flat_scratch_lo, s8, s11
@@ -120,7 +120,7 @@ define amdgpu_kernel void @call_got_load(i32 addrspace(1)* %ptr, i32) #0 {
}
; Need to wait for the address dependency
-define void @tailcall_got_load(i32 addrspace(1)* %ptr, i32) #0 {
+define void @tailcall_got_load(ptr addrspace(1) %ptr, i32) #0 {
; GCN-LABEL: tailcall_got_load:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -136,7 +136,7 @@ define void @tailcall_got_load(i32 addrspace(1)* %ptr, i32) #0 {
}
; No need to wait for the load.
-define void @tail_call_memory_arg_load(i32 addrspace(3)* %ptr, i32) #0 {
+define void @tail_call_memory_arg_load(ptr addrspace(3) %ptr, i32) #0 {
; GCN-LABEL: tail_call_memory_arg_load:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -145,7 +145,7 @@ define void @tail_call_memory_arg_load(i32 addrspace(3)* %ptr, i32) #0 {
; GCN-NEXT: s_add_u32 s4, s4, func at rel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, func at rel32@hi+12
; GCN-NEXT: s_setpc_b64 s[4:5]
- %vgpr = load volatile i32, i32 addrspace(3)* %ptr
+ %vgpr = load volatile i32, ptr addrspace(3) %ptr
tail call void @func(i32 %vgpr)
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll b/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
index 6439b0dcfc9a..f0af8f0d733f 100644
--- a/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
+++ b/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
@@ -40,7 +40,7 @@ define void @callee_no_stack_no_fp_elim_nonleaf() #2 {
; GCN-NEXT: s_setpc_b64
define void @callee_with_stack() #0 {
%alloca = alloca i32, addrspace(5)
- store volatile i32 0, i32 addrspace(5)* %alloca
+ store volatile i32 0, ptr addrspace(5) %alloca
ret void
}
@@ -64,7 +64,7 @@ define void @callee_with_stack() #0 {
; GCN-NEXT: s_setpc_b64
define void @callee_with_stack_no_fp_elim_all() #1 {
%alloca = alloca i32, addrspace(5)
- store volatile i32 0, i32 addrspace(5)* %alloca
+ store volatile i32 0, ptr addrspace(5) %alloca
ret void
}
@@ -78,7 +78,7 @@ define void @callee_with_stack_no_fp_elim_all() #1 {
; GCN-NEXT: s_setpc_b64
define void @callee_with_stack_no_fp_elim_non_leaf() #2 {
%alloca = alloca i32, addrspace(5)
- store volatile i32 0, i32 addrspace(5)* %alloca
+ store volatile i32 0, ptr addrspace(5) %alloca
ret void
}
@@ -117,7 +117,7 @@ define void @callee_with_stack_no_fp_elim_non_leaf() #2 {
; GCN-NEXT: s_setpc_b64 s[30:31]
define void @callee_with_stack_and_call() #0 {
%alloca = alloca i32, addrspace(5)
- store volatile i32 0, i32 addrspace(5)* %alloca
+ store volatile i32 0, ptr addrspace(5) %alloca
call void @external_void_func_void()
ret void
}
@@ -257,7 +257,7 @@ define void @spill_only_csr_sgpr() {
; GCN-NEXT: s_setpc_b64
define void @callee_with_stack_no_fp_elim_csr_vgpr() #1 {
%alloca = alloca i32, addrspace(5)
- store volatile i32 0, i32 addrspace(5)* %alloca
+ store volatile i32 0, ptr addrspace(5) %alloca
call void asm sideeffect "; clobber v41", "~{v41}"()
ret void
}
@@ -294,7 +294,7 @@ define void @callee_with_stack_no_fp_elim_csr_vgpr() #1 {
; GCN-NEXT: s_setpc_b64
define void @last_lane_vgpr_for_fp_csr() #1 {
%alloca = alloca i32, addrspace(5)
- store volatile i32 0, i32 addrspace(5)* %alloca
+ store volatile i32 0, ptr addrspace(5) %alloca
call void asm sideeffect "; clobber v41", "~{v41}"()
call void asm sideeffect "",
"~{s40},~{s41},~{s42},~{s43},~{s44},~{s45},~{s46},~{s47},~{s48},~{s49}
@@ -343,7 +343,7 @@ define void @last_lane_vgpr_for_fp_csr() #1 {
; GCN-NEXT: s_setpc_b64
define void @no_new_vgpr_for_fp_csr() #1 {
%alloca = alloca i32, addrspace(5)
- store volatile i32 0, i32 addrspace(5)* %alloca
+ store volatile i32 0, ptr addrspace(5) %alloca
call void asm sideeffect "; clobber v41", "~{v41}"()
call void asm sideeffect "",
"~{s39},~{s40},~{s41},~{s42},~{s43},~{s44},~{s45},~{s46},~{s47},~{s48},~{s49}
@@ -379,7 +379,7 @@ define void @no_new_vgpr_for_fp_csr() #1 {
; GCN-NEXT: s_setpc_b64
define void @realign_stack_no_fp_elim() #1 {
%alloca = alloca i32, align 8192, addrspace(5)
- store volatile i32 0, i32 addrspace(5)* %alloca
+ store volatile i32 0, ptr addrspace(5) %alloca
ret void
}
@@ -413,7 +413,7 @@ define void @realign_stack_no_fp_elim() #1 {
; GCN-NEXT: s_setpc_b64 s[30:31]
define void @no_unused_non_csr_sgpr_for_fp() #1 {
%alloca = alloca i32, addrspace(5)
- store volatile i32 0, i32 addrspace(5)* %alloca
+ store volatile i32 0, ptr addrspace(5) %alloca
; Use all clobberable registers, so FP has to spill to a VGPR.
call void asm sideeffect "",
@@ -452,7 +452,7 @@ define void @no_unused_non_csr_sgpr_for_fp() #1 {
; GCN-NEXT: s_setpc_b64 s[30:31]
define void @no_unused_non_csr_sgpr_for_fp_no_scratch_vgpr() #1 {
%alloca = alloca i32, addrspace(5)
- store volatile i32 0, i32 addrspace(5)* %alloca
+ store volatile i32 0, ptr addrspace(5) %alloca
; Use all clobberable registers, so FP has to spill to a VGPR.
call void asm sideeffect "",
@@ -499,9 +499,9 @@ define void @no_unused_non_csr_sgpr_for_fp_no_scratch_vgpr() #1 {
; GCN-NEXT: s_mov_b64 exec, [[COPY_EXEC1]]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
-define void @scratch_reg_needed_mubuf_offset([4096 x i8] addrspace(5)* byval([4096 x i8]) align 4 %arg) #1 {
+define void @scratch_reg_needed_mubuf_offset(ptr addrspace(5) byval([4096 x i8]) align 4 %arg) #1 {
%alloca = alloca i32, addrspace(5)
- store volatile i32 0, i32 addrspace(5)* %alloca
+ store volatile i32 0, ptr addrspace(5) %alloca
; Use all clobberable registers, so FP has to spill to a VGPR.
call void asm sideeffect "; clobber nonpreserved SGPRs",
@@ -542,7 +542,7 @@ define internal void @local_empty_func() #0 {
; GCN: v_readlane_b32 s33, v0, 2
define void @ipra_call_with_stack() #0 {
%alloca = alloca i32, addrspace(5)
- store volatile i32 0, i32 addrspace(5)* %alloca
+ store volatile i32 0, ptr addrspace(5) %alloca
call void @local_empty_func()
ret void
}
@@ -661,9 +661,9 @@ define void @callee_need_to_spill_fp_to_reg() #1 {
; FLATSCR: v_mov_b32_e32 v0, 0
; FLATSCR: s_add_i32 [[SOFF:s[0-9]+]], s33, 0x1000
; FLATSCR: scratch_store_dword off, v0, [[SOFF]]
-define void @spill_fp_to_memory_scratch_reg_needed_mubuf_offset([4096 x i8] addrspace(5)* byval([4096 x i8]) align 4 %arg) #3 {
+define void @spill_fp_to_memory_scratch_reg_needed_mubuf_offset(ptr addrspace(5) byval([4096 x i8]) align 4 %arg) #3 {
%alloca = alloca i32, addrspace(5)
- store volatile i32 0, i32 addrspace(5)* %alloca
+ store volatile i32 0, ptr addrspace(5) %alloca
call void asm sideeffect "; clobber nonpreserved SGPRs and 64 CSRs",
"~{s4},~{s5},~{s6},~{s7},~{s8},~{s9}
diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
index 3f0c627641ac..e510328bf176 100644
--- a/llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
+++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs-fixed-abi.ll
@@ -4,9 +4,8 @@
; GCN-LABEL: {{^}}use_dispatch_ptr:
; GCN: s_load_dword s{{[0-9]+}}, s[4:5]
define hidden void @use_dispatch_ptr() #1 {
- %dispatch_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
- %header_ptr = bitcast i8 addrspace(4)* %dispatch_ptr to i32 addrspace(4)*
- %value = load volatile i32, i32 addrspace(4)* %header_ptr
+ %dispatch_ptr = call noalias ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() #0
+ %value = load volatile i32, ptr addrspace(4) %dispatch_ptr
ret void
}
@@ -23,9 +22,8 @@ define amdgpu_kernel void @kern_indirect_use_dispatch_ptr(i32) #1 {
; GCN-LABEL: {{^}}use_queue_ptr:
; GCN: s_load_dword s{{[0-9]+}}, s[6:7]
define hidden void @use_queue_ptr() #1 {
- %queue_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
- %header_ptr = bitcast i8 addrspace(4)* %queue_ptr to i32 addrspace(4)*
- %value = load volatile i32, i32 addrspace(4)* %header_ptr
+ %queue_ptr = call noalias ptr addrspace(4) @llvm.amdgcn.queue.ptr() #0
+ %value = load volatile i32, ptr addrspace(4) %queue_ptr
ret void
}
@@ -45,8 +43,8 @@ define amdgpu_kernel void @kern_indirect_use_queue_ptr(i32) #1 {
; GFX9: {{flat|global}}_store_dword v{{\[[0-9]+}}:[[HI]]]
; CIVI: {{flat|global}}_store_dword v[[[LO]]:[[HI]]]
define hidden void @use_queue_ptr_addrspacecast() #1 {
- %asc = addrspacecast i32 addrspace(3)* inttoptr (i32 16 to i32 addrspace(3)*) to i32*
- store volatile i32 0, i32* %asc
+ %asc = addrspacecast ptr addrspace(3) inttoptr (i32 16 to ptr addrspace(3)) to ptr
+ store volatile i32 0, ptr %asc
ret void
}
@@ -66,18 +64,16 @@ define amdgpu_kernel void @kern_indirect_use_queue_ptr_addrspacecast(i32) #1 {
; GCN: s_mov_b64 [[PTR:s\[[0-9]+:[0-9]+\]]], 0
; GCN: s_load_dword s{{[0-9]+}}, [[PTR]], 0x0
define hidden void @use_kernarg_segment_ptr() #1 {
- %kernarg_segment_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
- %header_ptr = bitcast i8 addrspace(4)* %kernarg_segment_ptr to i32 addrspace(4)*
- %value = load volatile i32, i32 addrspace(4)* %header_ptr
+ %kernarg_segment_ptr = call noalias ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() #0
+ %value = load volatile i32, ptr addrspace(4) %kernarg_segment_ptr
ret void
}
; GCN-LABEL: {{^}}use_implicitarg_ptr:
; GCN: s_load_dword s{{[0-9]+}}, s[8:9]
define hidden void @use_implicitarg_ptr() #1 {
- %implicit.arg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
- %header_ptr = bitcast i8 addrspace(4)* %implicit.arg.ptr to i32 addrspace(4)*
- %value = load volatile i32, i32 addrspace(4)* %header_ptr
+ %implicit.arg.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #0
+ %value = load volatile i32, ptr addrspace(4) %implicit.arg.ptr
ret void
}
@@ -124,7 +120,7 @@ define hidden void @use_workgroup_id_x() #1 {
; GCN: s_setpc_b64
define hidden void @use_stack_workgroup_id_x() #1 {
%alloca = alloca i32, addrspace(5)
- store volatile i32 0, i32 addrspace(5)* %alloca
+ store volatile i32 0, ptr addrspace(5) %alloca
%val = call i32 @llvm.amdgcn.workgroup.id.x()
call void asm sideeffect "; use $0", "s"(i32 %val)
ret void
@@ -349,7 +345,7 @@ define hidden void @func_indirect_use_workgroup_id_z() #1 {
; GCN: ; use s12
define hidden void @other_arg_use_workgroup_id_x(i32 %arg0) #1 {
%val = call i32 @llvm.amdgcn.workgroup.id.x()
- store volatile i32 %arg0, i32 addrspace(1)* undef
+ store volatile i32 %arg0, ptr addrspace(1) undef
call void asm sideeffect "; use $0", "s"(i32 %val)
ret void
}
@@ -360,7 +356,7 @@ define hidden void @other_arg_use_workgroup_id_x(i32 %arg0) #1 {
; GCN: ; use s13
define hidden void @other_arg_use_workgroup_id_y(i32 %arg0) #1 {
%val = call i32 @llvm.amdgcn.workgroup.id.y()
- store volatile i32 %arg0, i32 addrspace(1)* undef
+ store volatile i32 %arg0, ptr addrspace(1) undef
call void asm sideeffect "; use $0", "s"(i32 %val)
ret void
}
@@ -371,7 +367,7 @@ define hidden void @other_arg_use_workgroup_id_y(i32 %arg0) #1 {
; GCN: ; use s14
define hidden void @other_arg_use_workgroup_id_z(i32 %arg0) #1 {
%val = call i32 @llvm.amdgcn.workgroup.id.z()
- store volatile i32 %arg0, i32 addrspace(1)* undef
+ store volatile i32 %arg0, ptr addrspace(1) undef
call void asm sideeffect "; use $0", "s"(i32 %val)
ret void
}
@@ -437,19 +433,16 @@ define amdgpu_kernel void @kern_indirect_other_arg_use_workgroup_id_z() #1 {
; GCN: ; use s14
define hidden void @use_every_sgpr_input() #1 {
%alloca = alloca i32, align 4, addrspace(5)
- store volatile i32 0, i32 addrspace(5)* %alloca
+ store volatile i32 0, ptr addrspace(5) %alloca
- %dispatch_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
- %dispatch_ptr.bc = bitcast i8 addrspace(4)* %dispatch_ptr to i32 addrspace(4)*
- %val0 = load volatile i32, i32 addrspace(4)* %dispatch_ptr.bc
+ %dispatch_ptr = call noalias ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() #0
+ %val0 = load volatile i32, ptr addrspace(4) %dispatch_ptr
- %queue_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
- %queue_ptr.bc = bitcast i8 addrspace(4)* %queue_ptr to i32 addrspace(4)*
- %val1 = load volatile i32, i32 addrspace(4)* %queue_ptr.bc
+ %queue_ptr = call noalias ptr addrspace(4) @llvm.amdgcn.queue.ptr() #0
+ %val1 = load volatile i32, ptr addrspace(4) %queue_ptr
- %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
- %implicitarg.ptr.bc = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
- %val2 = load volatile i32, i32 addrspace(4)* %implicitarg.ptr.bc
+ %implicitarg.ptr = call noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #0
+ %val2 = load volatile i32, ptr addrspace(4) %implicitarg.ptr
%val3 = call i64 @llvm.amdgcn.dispatch.id()
call void asm sideeffect "; use $0", "s"(i64 %val3)
@@ -549,19 +542,16 @@ define hidden void @func_indirect_use_every_sgpr_input() #1 {
; GCN: s_swappc_b64
define hidden void @func_use_every_sgpr_input_call_use_workgroup_id_xyz() #1 {
%alloca = alloca i32, align 4, addrspace(5)
- store volatile i32 0, i32 addrspace(5)* %alloca
+ store volatile i32 0, ptr addrspace(5) %alloca
- %dispatch_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
- %dispatch_ptr.bc = bitcast i8 addrspace(4)* %dispatch_ptr to i32 addrspace(4)*
- %val0 = load volatile i32, i32 addrspace(4)* %dispatch_ptr.bc
+ %dispatch_ptr = call noalias ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() #0
+ %val0 = load volatile i32, ptr addrspace(4) %dispatch_ptr
- %queue_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
- %queue_ptr.bc = bitcast i8 addrspace(4)* %queue_ptr to i32 addrspace(4)*
- %val1 = load volatile i32, i32 addrspace(4)* %queue_ptr.bc
+ %queue_ptr = call noalias ptr addrspace(4) @llvm.amdgcn.queue.ptr() #0
+ %val1 = load volatile i32, ptr addrspace(4) %queue_ptr
- %kernarg_segment_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
- %kernarg_segment_ptr.bc = bitcast i8 addrspace(4)* %kernarg_segment_ptr to i32 addrspace(4)*
- %val2 = load volatile i32, i32 addrspace(4)* %kernarg_segment_ptr.bc
+ %kernarg_segment_ptr = call noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #0
+ %val2 = load volatile i32, ptr addrspace(4) %kernarg_segment_ptr
%val3 = call i64 @llvm.amdgcn.dispatch.id()
call void asm sideeffect "; use $0", "s"(i64 %val3)
@@ -582,11 +572,11 @@ define hidden void @func_use_every_sgpr_input_call_use_workgroup_id_xyz() #1 {
declare i32 @llvm.amdgcn.workgroup.id.x() #0
declare i32 @llvm.amdgcn.workgroup.id.y() #0
declare i32 @llvm.amdgcn.workgroup.id.z() #0
-declare noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
-declare noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
-declare noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
+declare noalias ptr addrspace(4) @llvm.amdgcn.queue.ptr() #0
+declare noalias ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() #0
+declare noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #0
declare i64 @llvm.amdgcn.dispatch.id() #0
-declare noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
+declare noalias ptr addrspace(4) @llvm.amdgcn.dispatch.ptr() #0
attributes #0 = { nounwind readnone speculatable }
attributes #1 = { nounwind noinline }
diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
index eb4ed8b2acef..1f7199445044 100644
--- a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
+++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
@@ -9,7 +9,7 @@
; GCN-NEXT: s_setpc_b64
define void @use_workitem_id_x() #1 {
%val = call i32 @llvm.amdgcn.workitem.id.x()
- store volatile i32 %val, i32 addrspace(1)* undef
+ store volatile i32 %val, ptr addrspace(1) undef
ret void
}
@@ -21,7 +21,7 @@ define void @use_workitem_id_x() #1 {
; GCN-NEXT: s_setpc_b64
define void @use_workitem_id_y() #1 {
%val = call i32 @llvm.amdgcn.workitem.id.y()
- store volatile i32 %val, i32 addrspace(1)* undef
+ store volatile i32 %val, ptr addrspace(1) undef
ret void
}
@@ -33,7 +33,7 @@ define void @use_workitem_id_y() #1 {
; GCN-NEXT: s_setpc_b64
define void @use_workitem_id_z() #1 {
%val = call i32 @llvm.amdgcn.workitem.id.z()
- store volatile i32 %val, i32 addrspace(1)* undef
+ store volatile i32 %val, ptr addrspace(1) undef
ret void
}
@@ -48,8 +48,8 @@ define void @use_workitem_id_z() #1 {
define void @use_workitem_id_xy() #1 {
%val0 = call i32 @llvm.amdgcn.workitem.id.x()
%val1 = call i32 @llvm.amdgcn.workitem.id.y()
- store volatile i32 %val0, i32 addrspace(1)* undef
- store volatile i32 %val1, i32 addrspace(1)* undef
+ store volatile i32 %val0, ptr addrspace(1) undef
+ store volatile i32 %val1, ptr addrspace(1) undef
ret void
}
@@ -67,9 +67,9 @@ define void @use_workitem_id_xyz() #1 {
%val0 = call i32 @llvm.amdgcn.workitem.id.x()
%val1 = call i32 @llvm.amdgcn.workitem.id.y()
%val2 = call i32 @llvm.amdgcn.workitem.id.z()
- store volatile i32 %val0, i32 addrspace(1)* undef
- store volatile i32 %val1, i32 addrspace(1)* undef
- store volatile i32 %val2, i32 addrspace(1)* undef
+ store volatile i32 %val0, ptr addrspace(1) undef
+ store volatile i32 %val1, ptr addrspace(1) undef
+ store volatile i32 %val2, ptr addrspace(1) undef
ret void
}
@@ -84,8 +84,8 @@ define void @use_workitem_id_xyz() #1 {
define void @use_workitem_id_xz() #1 {
%val0 = call i32 @llvm.amdgcn.workitem.id.x()
%val1 = call i32 @llvm.amdgcn.workitem.id.z()
- store volatile i32 %val0, i32 addrspace(1)* undef
- store volatile i32 %val1, i32 addrspace(1)* undef
+ store volatile i32 %val0, ptr addrspace(1) undef
+ store volatile i32 %val1, ptr addrspace(1) undef
ret void
}
@@ -100,8 +100,8 @@ define void @use_workitem_id_xz() #1 {
define void @use_workitem_id_yz() #1 {
%val0 = call i32 @llvm.amdgcn.workitem.id.y()
%val1 = call i32 @llvm.amdgcn.workitem.id.z()
- store volatile i32 %val0, i32 addrspace(1)* undef
- store volatile i32 %val1, i32 addrspace(1)* undef
+ store volatile i32 %val0, ptr addrspace(1) undef
+ store volatile i32 %val1, ptr addrspace(1) undef
ret void
}
@@ -248,8 +248,8 @@ define void @func_indirect_use_workitem_id_z() #1 {
; GCN-DAG: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[ID]]
define void @other_arg_use_workitem_id_x(i32 %arg0) #1 {
%val = call i32 @llvm.amdgcn.workitem.id.x()
- store volatile i32 %arg0, i32 addrspace(1)* undef
- store volatile i32 %val, i32 addrspace(1)* undef
+ store volatile i32 %arg0, ptr addrspace(1) undef
+ store volatile i32 %val, ptr addrspace(1) undef
ret void
}
@@ -260,8 +260,8 @@ define void @other_arg_use_workitem_id_x(i32 %arg0) #1 {
; GCN-DAG: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[ID]]
define void @other_arg_use_workitem_id_y(i32 %arg0) #1 {
%val = call i32 @llvm.amdgcn.workitem.id.y()
- store volatile i32 %arg0, i32 addrspace(1)* undef
- store volatile i32 %val, i32 addrspace(1)* undef
+ store volatile i32 %arg0, ptr addrspace(1) undef
+ store volatile i32 %val, ptr addrspace(1) undef
ret void
}
@@ -272,8 +272,8 @@ define void @other_arg_use_workitem_id_y(i32 %arg0) #1 {
; GCN-DAG: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[ID]]
define void @other_arg_use_workitem_id_z(i32 %arg0) #1 {
%val = call i32 @llvm.amdgcn.workitem.id.z()
- store volatile i32 %arg0, i32 addrspace(1)* undef
- store volatile i32 %val, i32 addrspace(1)* undef
+ store volatile i32 %arg0, ptr addrspace(1) undef
+ store volatile i32 %val, ptr addrspace(1) undef
ret void
}
@@ -333,43 +333,43 @@ define void @too_many_args_use_workitem_id_x(
i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31) #1 {
%val = call i32 @llvm.amdgcn.workitem.id.x()
- store volatile i32 %val, i32 addrspace(1)* undef
-
- store volatile i32 %arg0, i32 addrspace(1)* undef
- store volatile i32 %arg1, i32 addrspace(1)* undef
- store volatile i32 %arg2, i32 addrspace(1)* undef
- store volatile i32 %arg3, i32 addrspace(1)* undef
- store volatile i32 %arg4, i32 addrspace(1)* undef
- store volatile i32 %arg5, i32 addrspace(1)* undef
- store volatile i32 %arg6, i32 addrspace(1)* undef
- store volatile i32 %arg7, i32 addrspace(1)* undef
-
- store volatile i32 %arg8, i32 addrspace(1)* undef
- store volatile i32 %arg9, i32 addrspace(1)* undef
- store volatile i32 %arg10, i32 addrspace(1)* undef
- store volatile i32 %arg11, i32 addrspace(1)* undef
- store volatile i32 %arg12, i32 addrspace(1)* undef
- store volatile i32 %arg13, i32 addrspace(1)* undef
- store volatile i32 %arg14, i32 addrspace(1)* undef
- store volatile i32 %arg15, i32 addrspace(1)* undef
-
- store volatile i32 %arg16, i32 addrspace(1)* undef
- store volatile i32 %arg17, i32 addrspace(1)* undef
- store volatile i32 %arg18, i32 addrspace(1)* undef
- store volatile i32 %arg19, i32 addrspace(1)* undef
- store volatile i32 %arg20, i32 addrspace(1)* undef
- store volatile i32 %arg21, i32 addrspace(1)* undef
- store volatile i32 %arg22, i32 addrspace(1)* undef
- store volatile i32 %arg23, i32 addrspace(1)* undef
-
- store volatile i32 %arg24, i32 addrspace(1)* undef
- store volatile i32 %arg25, i32 addrspace(1)* undef
- store volatile i32 %arg26, i32 addrspace(1)* undef
- store volatile i32 %arg27, i32 addrspace(1)* undef
- store volatile i32 %arg28, i32 addrspace(1)* undef
- store volatile i32 %arg29, i32 addrspace(1)* undef
- store volatile i32 %arg30, i32 addrspace(1)* undef
- store volatile i32 %arg31, i32 addrspace(1)* undef
+ store volatile i32 %val, ptr addrspace(1) undef
+
+ store volatile i32 %arg0, ptr addrspace(1) undef
+ store volatile i32 %arg1, ptr addrspace(1) undef
+ store volatile i32 %arg2, ptr addrspace(1) undef
+ store volatile i32 %arg3, ptr addrspace(1) undef
+ store volatile i32 %arg4, ptr addrspace(1) undef
+ store volatile i32 %arg5, ptr addrspace(1) undef
+ store volatile i32 %arg6, ptr addrspace(1) undef
+ store volatile i32 %arg7, ptr addrspace(1) undef
+
+ store volatile i32 %arg8, ptr addrspace(1) undef
+ store volatile i32 %arg9, ptr addrspace(1) undef
+ store volatile i32 %arg10, ptr addrspace(1) undef
+ store volatile i32 %arg11, ptr addrspace(1) undef
+ store volatile i32 %arg12, ptr addrspace(1) undef
+ store volatile i32 %arg13, ptr addrspace(1) undef
+ store volatile i32 %arg14, ptr addrspace(1) undef
+ store volatile i32 %arg15, ptr addrspace(1) undef
+
+ store volatile i32 %arg16, ptr addrspace(1) undef
+ store volatile i32 %arg17, ptr addrspace(1) undef
+ store volatile i32 %arg18, ptr addrspace(1) undef
+ store volatile i32 %arg19, ptr addrspace(1) undef
+ store volatile i32 %arg20, ptr addrspace(1) undef
+ store volatile i32 %arg21, ptr addrspace(1) undef
+ store volatile i32 %arg22, ptr addrspace(1) undef
+ store volatile i32 %arg23, ptr addrspace(1) undef
+
+ store volatile i32 %arg24, ptr addrspace(1) undef
+ store volatile i32 %arg25, ptr addrspace(1) undef
+ store volatile i32 %arg26, ptr addrspace(1) undef
+ store volatile i32 %arg27, ptr addrspace(1) undef
+ store volatile i32 %arg28, ptr addrspace(1) undef
+ store volatile i32 %arg29, ptr addrspace(1) undef
+ store volatile i32 %arg30, ptr addrspace(1) undef
+ store volatile i32 %arg31, ptr addrspace(1) undef
ret void
}
@@ -403,7 +403,7 @@ define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x() #1 {
; GCN: s_swappc_b64
; GCN-NOT: v31
define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 {
- store volatile i32 %arg0, i32 addrspace(1)* undef
+ store volatile i32 %arg0, ptr addrspace(1) undef
call void @too_many_args_use_workitem_id_x(
i32 10, i32 20, i32 30, i32 40,
i32 50, i32 60, i32 70, i32 80,
@@ -458,46 +458,46 @@ define void @too_many_args_use_workitem_id_x_byval(
i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7,
i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
- i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31, i32 addrspace(5)* byval(i32) %arg32) #1 {
+ i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31, ptr addrspace(5) byval(i32) %arg32) #1 {
%val = call i32 @llvm.amdgcn.workitem.id.x()
- store volatile i32 %val, i32 addrspace(1)* undef
-
- store volatile i32 %arg0, i32 addrspace(1)* undef
- store volatile i32 %arg1, i32 addrspace(1)* undef
- store volatile i32 %arg2, i32 addrspace(1)* undef
- store volatile i32 %arg3, i32 addrspace(1)* undef
- store volatile i32 %arg4, i32 addrspace(1)* undef
- store volatile i32 %arg5, i32 addrspace(1)* undef
- store volatile i32 %arg6, i32 addrspace(1)* undef
- store volatile i32 %arg7, i32 addrspace(1)* undef
-
- store volatile i32 %arg8, i32 addrspace(1)* undef
- store volatile i32 %arg9, i32 addrspace(1)* undef
- store volatile i32 %arg10, i32 addrspace(1)* undef
- store volatile i32 %arg11, i32 addrspace(1)* undef
- store volatile i32 %arg12, i32 addrspace(1)* undef
- store volatile i32 %arg13, i32 addrspace(1)* undef
- store volatile i32 %arg14, i32 addrspace(1)* undef
- store volatile i32 %arg15, i32 addrspace(1)* undef
-
- store volatile i32 %arg16, i32 addrspace(1)* undef
- store volatile i32 %arg17, i32 addrspace(1)* undef
- store volatile i32 %arg18, i32 addrspace(1)* undef
- store volatile i32 %arg19, i32 addrspace(1)* undef
- store volatile i32 %arg20, i32 addrspace(1)* undef
- store volatile i32 %arg21, i32 addrspace(1)* undef
- store volatile i32 %arg22, i32 addrspace(1)* undef
- store volatile i32 %arg23, i32 addrspace(1)* undef
-
- store volatile i32 %arg24, i32 addrspace(1)* undef
- store volatile i32 %arg25, i32 addrspace(1)* undef
- store volatile i32 %arg26, i32 addrspace(1)* undef
- store volatile i32 %arg27, i32 addrspace(1)* undef
- store volatile i32 %arg28, i32 addrspace(1)* undef
- store volatile i32 %arg29, i32 addrspace(1)* undef
- store volatile i32 %arg30, i32 addrspace(1)* undef
- store volatile i32 %arg31, i32 addrspace(1)* undef
- %private = load volatile i32, i32 addrspace(5)* %arg32
+ store volatile i32 %val, ptr addrspace(1) undef
+
+ store volatile i32 %arg0, ptr addrspace(1) undef
+ store volatile i32 %arg1, ptr addrspace(1) undef
+ store volatile i32 %arg2, ptr addrspace(1) undef
+ store volatile i32 %arg3, ptr addrspace(1) undef
+ store volatile i32 %arg4, ptr addrspace(1) undef
+ store volatile i32 %arg5, ptr addrspace(1) undef
+ store volatile i32 %arg6, ptr addrspace(1) undef
+ store volatile i32 %arg7, ptr addrspace(1) undef
+
+ store volatile i32 %arg8, ptr addrspace(1) undef
+ store volatile i32 %arg9, ptr addrspace(1) undef
+ store volatile i32 %arg10, ptr addrspace(1) undef
+ store volatile i32 %arg11, ptr addrspace(1) undef
+ store volatile i32 %arg12, ptr addrspace(1) undef
+ store volatile i32 %arg13, ptr addrspace(1) undef
+ store volatile i32 %arg14, ptr addrspace(1) undef
+ store volatile i32 %arg15, ptr addrspace(1) undef
+
+ store volatile i32 %arg16, ptr addrspace(1) undef
+ store volatile i32 %arg17, ptr addrspace(1) undef
+ store volatile i32 %arg18, ptr addrspace(1) undef
+ store volatile i32 %arg19, ptr addrspace(1) undef
+ store volatile i32 %arg20, ptr addrspace(1) undef
+ store volatile i32 %arg21, ptr addrspace(1) undef
+ store volatile i32 %arg22, ptr addrspace(1) undef
+ store volatile i32 %arg23, ptr addrspace(1) undef
+
+ store volatile i32 %arg24, ptr addrspace(1) undef
+ store volatile i32 %arg25, ptr addrspace(1) undef
+ store volatile i32 %arg26, ptr addrspace(1) undef
+ store volatile i32 %arg27, ptr addrspace(1) undef
+ store volatile i32 %arg28, ptr addrspace(1) undef
+ store volatile i32 %arg29, ptr addrspace(1) undef
+ store volatile i32 %arg30, ptr addrspace(1) undef
+ store volatile i32 %arg31, ptr addrspace(1) undef
+ %private = load volatile i32, ptr addrspace(5) %arg32
ret void
}
@@ -523,7 +523,7 @@ define void @too_many_args_use_workitem_id_x_byval(
; GCN: .amdhsa_system_vgpr_workitem_id 0
define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_byval() #1 {
%alloca = alloca i32, align 4, addrspace(5)
- store volatile i32 999, i32 addrspace(5)* %alloca
+ store volatile i32 999, ptr addrspace(5) %alloca
call void @too_many_args_use_workitem_id_x_byval(
i32 10, i32 20, i32 30, i32 40,
i32 50, i32 60, i32 70, i32 80,
@@ -533,7 +533,7 @@ define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_byval() #1
i32 210, i32 220, i32 230, i32 240,
i32 250, i32 260, i32 270, i32 280,
i32 290, i32 300, i32 310, i32 320,
- i32 addrspace(5)* byval(i32) %alloca)
+ ptr addrspace(5) byval(i32) %alloca)
ret void
}
@@ -547,7 +547,7 @@ define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_byval() #1
; GCN: s_swappc_b64
define void @func_call_too_many_args_use_workitem_id_x_byval() #1 {
%alloca = alloca i32, align 4, addrspace(5)
- store volatile i32 999, i32 addrspace(5)* %alloca
+ store volatile i32 999, ptr addrspace(5) %alloca
call void @too_many_args_use_workitem_id_x_byval(
i32 10, i32 20, i32 30, i32 40,
i32 50, i32 60, i32 70, i32 80,
@@ -557,7 +557,7 @@ define void @func_call_too_many_args_use_workitem_id_x_byval() #1 {
i32 210, i32 220, i32 230, i32 240,
i32 250, i32 260, i32 270, i32 280,
i32 290, i32 300, i32 310, i32 320,
- i32 addrspace(5)* byval(i32) %alloca)
+ ptr addrspace(5) byval(i32) %alloca)
ret void
}
@@ -588,47 +588,47 @@ define void @too_many_args_use_workitem_id_xyz(
i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31) #1 {
%val0 = call i32 @llvm.amdgcn.workitem.id.x()
- store volatile i32 %val0, i32 addrspace(1)* undef
+ store volatile i32 %val0, ptr addrspace(1) undef
%val1 = call i32 @llvm.amdgcn.workitem.id.y()
- store volatile i32 %val1, i32 addrspace(1)* undef
+ store volatile i32 %val1, ptr addrspace(1) undef
%val2 = call i32 @llvm.amdgcn.workitem.id.z()
- store volatile i32 %val2, i32 addrspace(1)* undef
-
- store volatile i32 %arg0, i32 addrspace(1)* undef
- store volatile i32 %arg1, i32 addrspace(1)* undef
- store volatile i32 %arg2, i32 addrspace(1)* undef
- store volatile i32 %arg3, i32 addrspace(1)* undef
- store volatile i32 %arg4, i32 addrspace(1)* undef
- store volatile i32 %arg5, i32 addrspace(1)* undef
- store volatile i32 %arg6, i32 addrspace(1)* undef
- store volatile i32 %arg7, i32 addrspace(1)* undef
-
- store volatile i32 %arg8, i32 addrspace(1)* undef
- store volatile i32 %arg9, i32 addrspace(1)* undef
- store volatile i32 %arg10, i32 addrspace(1)* undef
- store volatile i32 %arg11, i32 addrspace(1)* undef
- store volatile i32 %arg12, i32 addrspace(1)* undef
- store volatile i32 %arg13, i32 addrspace(1)* undef
- store volatile i32 %arg14, i32 addrspace(1)* undef
- store volatile i32 %arg15, i32 addrspace(1)* undef
-
- store volatile i32 %arg16, i32 addrspace(1)* undef
- store volatile i32 %arg17, i32 addrspace(1)* undef
- store volatile i32 %arg18, i32 addrspace(1)* undef
- store volatile i32 %arg19, i32 addrspace(1)* undef
- store volatile i32 %arg20, i32 addrspace(1)* undef
- store volatile i32 %arg21, i32 addrspace(1)* undef
- store volatile i32 %arg22, i32 addrspace(1)* undef
- store volatile i32 %arg23, i32 addrspace(1)* undef
-
- store volatile i32 %arg24, i32 addrspace(1)* undef
- store volatile i32 %arg25, i32 addrspace(1)* undef
- store volatile i32 %arg26, i32 addrspace(1)* undef
- store volatile i32 %arg27, i32 addrspace(1)* undef
- store volatile i32 %arg28, i32 addrspace(1)* undef
- store volatile i32 %arg29, i32 addrspace(1)* undef
- store volatile i32 %arg30, i32 addrspace(1)* undef
- store volatile i32 %arg31, i32 addrspace(1)* undef
+ store volatile i32 %val2, ptr addrspace(1) undef
+
+ store volatile i32 %arg0, ptr addrspace(1) undef
+ store volatile i32 %arg1, ptr addrspace(1) undef
+ store volatile i32 %arg2, ptr addrspace(1) undef
+ store volatile i32 %arg3, ptr addrspace(1) undef
+ store volatile i32 %arg4, ptr addrspace(1) undef
+ store volatile i32 %arg5, ptr addrspace(1) undef
+ store volatile i32 %arg6, ptr addrspace(1) undef
+ store volatile i32 %arg7, ptr addrspace(1) undef
+
+ store volatile i32 %arg8, ptr addrspace(1) undef
+ store volatile i32 %arg9, ptr addrspace(1) undef
+ store volatile i32 %arg10, ptr addrspace(1) undef
+ store volatile i32 %arg11, ptr addrspace(1) undef
+ store volatile i32 %arg12, ptr addrspace(1) undef
+ store volatile i32 %arg13, ptr addrspace(1) undef
+ store volatile i32 %arg14, ptr addrspace(1) undef
+ store volatile i32 %arg15, ptr addrspace(1) undef
+
+ store volatile i32 %arg16, ptr addrspace(1) undef
+ store volatile i32 %arg17, ptr addrspace(1) undef
+ store volatile i32 %arg18, ptr addrspace(1) undef
+ store volatile i32 %arg19, ptr addrspace(1) undef
+ store volatile i32 %arg20, ptr addrspace(1) undef
+ store volatile i32 %arg21, ptr addrspace(1) undef
+ store volatile i32 %arg22, ptr addrspace(1) undef
+ store volatile i32 %arg23, ptr addrspace(1) undef
+
+ store volatile i32 %arg24, ptr addrspace(1) undef
+ store volatile i32 %arg25, ptr addrspace(1) undef
+ store volatile i32 %arg26, ptr addrspace(1) undef
+ store volatile i32 %arg27, ptr addrspace(1) undef
+ store volatile i32 %arg28, ptr addrspace(1) undef
+ store volatile i32 %arg29, ptr addrspace(1) undef
+ store volatile i32 %arg30, ptr addrspace(1) undef
+ store volatile i32 %arg31, ptr addrspace(1) undef
ret void
}
@@ -686,46 +686,46 @@ define void @too_many_args_use_workitem_id_x_stack_yz(
i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30) #1 {
%val0 = call i32 @llvm.amdgcn.workitem.id.x()
- store volatile i32 %val0, i32 addrspace(1)* undef
+ store volatile i32 %val0, ptr addrspace(1) undef
%val1 = call i32 @llvm.amdgcn.workitem.id.y()
- store volatile i32 %val1, i32 addrspace(1)* undef
+ store volatile i32 %val1, ptr addrspace(1) undef
%val2 = call i32 @llvm.amdgcn.workitem.id.z()
- store volatile i32 %val2, i32 addrspace(1)* undef
-
- store volatile i32 %arg0, i32 addrspace(1)* undef
- store volatile i32 %arg1, i32 addrspace(1)* undef
- store volatile i32 %arg2, i32 addrspace(1)* undef
- store volatile i32 %arg3, i32 addrspace(1)* undef
- store volatile i32 %arg4, i32 addrspace(1)* undef
- store volatile i32 %arg5, i32 addrspace(1)* undef
- store volatile i32 %arg6, i32 addrspace(1)* undef
- store volatile i32 %arg7, i32 addrspace(1)* undef
-
- store volatile i32 %arg8, i32 addrspace(1)* undef
- store volatile i32 %arg9, i32 addrspace(1)* undef
- store volatile i32 %arg10, i32 addrspace(1)* undef
- store volatile i32 %arg11, i32 addrspace(1)* undef
- store volatile i32 %arg12, i32 addrspace(1)* undef
- store volatile i32 %arg13, i32 addrspace(1)* undef
- store volatile i32 %arg14, i32 addrspace(1)* undef
- store volatile i32 %arg15, i32 addrspace(1)* undef
-
- store volatile i32 %arg16, i32 addrspace(1)* undef
- store volatile i32 %arg17, i32 addrspace(1)* undef
- store volatile i32 %arg18, i32 addrspace(1)* undef
- store volatile i32 %arg19, i32 addrspace(1)* undef
- store volatile i32 %arg20, i32 addrspace(1)* undef
- store volatile i32 %arg21, i32 addrspace(1)* undef
- store volatile i32 %arg22, i32 addrspace(1)* undef
- store volatile i32 %arg23, i32 addrspace(1)* undef
-
- store volatile i32 %arg24, i32 addrspace(1)* undef
- store volatile i32 %arg25, i32 addrspace(1)* undef
- store volatile i32 %arg26, i32 addrspace(1)* undef
- store volatile i32 %arg27, i32 addrspace(1)* undef
- store volatile i32 %arg28, i32 addrspace(1)* undef
- store volatile i32 %arg29, i32 addrspace(1)* undef
- store volatile i32 %arg30, i32 addrspace(1)* undef
+ store volatile i32 %val2, ptr addrspace(1) undef
+
+ store volatile i32 %arg0, ptr addrspace(1) undef
+ store volatile i32 %arg1, ptr addrspace(1) undef
+ store volatile i32 %arg2, ptr addrspace(1) undef
+ store volatile i32 %arg3, ptr addrspace(1) undef
+ store volatile i32 %arg4, ptr addrspace(1) undef
+ store volatile i32 %arg5, ptr addrspace(1) undef
+ store volatile i32 %arg6, ptr addrspace(1) undef
+ store volatile i32 %arg7, ptr addrspace(1) undef
+
+ store volatile i32 %arg8, ptr addrspace(1) undef
+ store volatile i32 %arg9, ptr addrspace(1) undef
+ store volatile i32 %arg10, ptr addrspace(1) undef
+ store volatile i32 %arg11, ptr addrspace(1) undef
+ store volatile i32 %arg12, ptr addrspace(1) undef
+ store volatile i32 %arg13, ptr addrspace(1) undef
+ store volatile i32 %arg14, ptr addrspace(1) undef
+ store volatile i32 %arg15, ptr addrspace(1) undef
+
+ store volatile i32 %arg16, ptr addrspace(1) undef
+ store volatile i32 %arg17, ptr addrspace(1) undef
+ store volatile i32 %arg18, ptr addrspace(1) undef
+ store volatile i32 %arg19, ptr addrspace(1) undef
+ store volatile i32 %arg20, ptr addrspace(1) undef
+ store volatile i32 %arg21, ptr addrspace(1) undef
+ store volatile i32 %arg22, ptr addrspace(1) undef
+ store volatile i32 %arg23, ptr addrspace(1) undef
+
+ store volatile i32 %arg24, ptr addrspace(1) undef
+ store volatile i32 %arg25, ptr addrspace(1) undef
+ store volatile i32 %arg26, ptr addrspace(1) undef
+ store volatile i32 %arg27, ptr addrspace(1) undef
+ store volatile i32 %arg28, ptr addrspace(1) undef
+ store volatile i32 %arg29, ptr addrspace(1) undef
+ store volatile i32 %arg30, ptr addrspace(1) undef
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
index c63830a00a01..343b96b4d3f2 100644
--- a/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
+++ b/llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
@@ -8,7 +8,7 @@
; GCN-NEXT: s_setpc_b64
define void @use_workitem_id_x() #1 {
%val = call i32 @llvm.amdgcn.workitem.id.x()
- store volatile i32 %val, i32 addrspace(1)* undef
+ store volatile i32 %val, ptr addrspace(1) undef
ret void
}
@@ -20,7 +20,7 @@ define void @use_workitem_id_x() #1 {
; GCN-NEXT: s_setpc_b64
define void @use_workitem_id_y() #1 {
%val = call i32 @llvm.amdgcn.workitem.id.y()
- store volatile i32 %val, i32 addrspace(1)* undef
+ store volatile i32 %val, ptr addrspace(1) undef
ret void
}
@@ -32,7 +32,7 @@ define void @use_workitem_id_y() #1 {
; GCN-NEXT: s_setpc_b64
define void @use_workitem_id_z() #1 {
%val = call i32 @llvm.amdgcn.workitem.id.z()
- store volatile i32 %val, i32 addrspace(1)* undef
+ store volatile i32 %val, ptr addrspace(1) undef
ret void
}
@@ -48,8 +48,8 @@ define void @use_workitem_id_z() #1 {
define void @use_workitem_id_xy() #1 {
%val0 = call i32 @llvm.amdgcn.workitem.id.x()
%val1 = call i32 @llvm.amdgcn.workitem.id.y()
- store volatile i32 %val0, i32 addrspace(1)* undef
- store volatile i32 %val1, i32 addrspace(1)* undef
+ store volatile i32 %val0, ptr addrspace(1) undef
+ store volatile i32 %val1, ptr addrspace(1) undef
ret void
}
@@ -70,9 +70,9 @@ define void @use_workitem_id_xyz() #1 {
%val0 = call i32 @llvm.amdgcn.workitem.id.x()
%val1 = call i32 @llvm.amdgcn.workitem.id.y()
%val2 = call i32 @llvm.amdgcn.workitem.id.z()
- store volatile i32 %val0, i32 addrspace(1)* undef
- store volatile i32 %val1, i32 addrspace(1)* undef
- store volatile i32 %val2, i32 addrspace(1)* undef
+ store volatile i32 %val0, ptr addrspace(1) undef
+ store volatile i32 %val1, ptr addrspace(1) undef
+ store volatile i32 %val2, ptr addrspace(1) undef
ret void
}
@@ -88,8 +88,8 @@ define void @use_workitem_id_xyz() #1 {
define void @use_workitem_id_xz() #1 {
%val0 = call i32 @llvm.amdgcn.workitem.id.x()
%val1 = call i32 @llvm.amdgcn.workitem.id.z()
- store volatile i32 %val0, i32 addrspace(1)* undef
- store volatile i32 %val1, i32 addrspace(1)* undef
+ store volatile i32 %val0, ptr addrspace(1) undef
+ store volatile i32 %val1, ptr addrspace(1) undef
ret void
}
@@ -105,8 +105,8 @@ define void @use_workitem_id_xz() #1 {
define void @use_workitem_id_yz() #1 {
%val0 = call i32 @llvm.amdgcn.workitem.id.y()
%val1 = call i32 @llvm.amdgcn.workitem.id.z()
- store volatile i32 %val0, i32 addrspace(1)* undef
- store volatile i32 %val1, i32 addrspace(1)* undef
+ store volatile i32 %val0, ptr addrspace(1) undef
+ store volatile i32 %val1, ptr addrspace(1) undef
ret void
}
@@ -253,8 +253,8 @@ define void @func_indirect_use_workitem_id_z() #1 {
; GCN-DAG: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[ID]]
define void @other_arg_use_workitem_id_x(i32 %arg0) #1 {
%val = call i32 @llvm.amdgcn.workitem.id.x()
- store volatile i32 %arg0, i32 addrspace(1)* undef
- store volatile i32 %val, i32 addrspace(1)* undef
+ store volatile i32 %arg0, ptr addrspace(1) undef
+ store volatile i32 %val, ptr addrspace(1) undef
ret void
}
@@ -265,8 +265,8 @@ define void @other_arg_use_workitem_id_x(i32 %arg0) #1 {
; GCN-DAG: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[ID]]
define void @other_arg_use_workitem_id_y(i32 %arg0) #1 {
%val = call i32 @llvm.amdgcn.workitem.id.y()
- store volatile i32 %arg0, i32 addrspace(1)* undef
- store volatile i32 %val, i32 addrspace(1)* undef
+ store volatile i32 %arg0, ptr addrspace(1) undef
+ store volatile i32 %val, ptr addrspace(1) undef
ret void
}
@@ -277,8 +277,8 @@ define void @other_arg_use_workitem_id_y(i32 %arg0) #1 {
; GCN-DAG: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[ID]]
define void @other_arg_use_workitem_id_z(i32 %arg0) #1 {
%val = call i32 @llvm.amdgcn.workitem.id.z()
- store volatile i32 %arg0, i32 addrspace(1)* undef
- store volatile i32 %val, i32 addrspace(1)* undef
+ store volatile i32 %arg0, ptr addrspace(1) undef
+ store volatile i32 %val, ptr addrspace(1) undef
ret void
}
@@ -332,43 +332,43 @@ define void @too_many_args_use_workitem_id_x(
i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31) #1 {
%val = call i32 @llvm.amdgcn.workitem.id.x()
- store volatile i32 %val, i32 addrspace(1)* undef
-
- store volatile i32 %arg0, i32 addrspace(1)* undef
- store volatile i32 %arg1, i32 addrspace(1)* undef
- store volatile i32 %arg2, i32 addrspace(1)* undef
- store volatile i32 %arg3, i32 addrspace(1)* undef
- store volatile i32 %arg4, i32 addrspace(1)* undef
- store volatile i32 %arg5, i32 addrspace(1)* undef
- store volatile i32 %arg6, i32 addrspace(1)* undef
- store volatile i32 %arg7, i32 addrspace(1)* undef
-
- store volatile i32 %arg8, i32 addrspace(1)* undef
- store volatile i32 %arg9, i32 addrspace(1)* undef
- store volatile i32 %arg10, i32 addrspace(1)* undef
- store volatile i32 %arg11, i32 addrspace(1)* undef
- store volatile i32 %arg12, i32 addrspace(1)* undef
- store volatile i32 %arg13, i32 addrspace(1)* undef
- store volatile i32 %arg14, i32 addrspace(1)* undef
- store volatile i32 %arg15, i32 addrspace(1)* undef
-
- store volatile i32 %arg16, i32 addrspace(1)* undef
- store volatile i32 %arg17, i32 addrspace(1)* undef
- store volatile i32 %arg18, i32 addrspace(1)* undef
- store volatile i32 %arg19, i32 addrspace(1)* undef
- store volatile i32 %arg20, i32 addrspace(1)* undef
- store volatile i32 %arg21, i32 addrspace(1)* undef
- store volatile i32 %arg22, i32 addrspace(1)* undef
- store volatile i32 %arg23, i32 addrspace(1)* undef
-
- store volatile i32 %arg24, i32 addrspace(1)* undef
- store volatile i32 %arg25, i32 addrspace(1)* undef
- store volatile i32 %arg26, i32 addrspace(1)* undef
- store volatile i32 %arg27, i32 addrspace(1)* undef
- store volatile i32 %arg28, i32 addrspace(1)* undef
- store volatile i32 %arg29, i32 addrspace(1)* undef
- store volatile i32 %arg30, i32 addrspace(1)* undef
- store volatile i32 %arg31, i32 addrspace(1)* undef
+ store volatile i32 %val, ptr addrspace(1) undef
+
+ store volatile i32 %arg0, ptr addrspace(1) undef
+ store volatile i32 %arg1, ptr addrspace(1) undef
+ store volatile i32 %arg2, ptr addrspace(1) undef
+ store volatile i32 %arg3, ptr addrspace(1) undef
+ store volatile i32 %arg4, ptr addrspace(1) undef
+ store volatile i32 %arg5, ptr addrspace(1) undef
+ store volatile i32 %arg6, ptr addrspace(1) undef
+ store volatile i32 %arg7, ptr addrspace(1) undef
+
+ store volatile i32 %arg8, ptr addrspace(1) undef
+ store volatile i32 %arg9, ptr addrspace(1) undef
+ store volatile i32 %arg10, ptr addrspace(1) undef
+ store volatile i32 %arg11, ptr addrspace(1) undef
+ store volatile i32 %arg12, ptr addrspace(1) undef
+ store volatile i32 %arg13, ptr addrspace(1) undef
+ store volatile i32 %arg14, ptr addrspace(1) undef
+ store volatile i32 %arg15, ptr addrspace(1) undef
+
+ store volatile i32 %arg16, ptr addrspace(1) undef
+ store volatile i32 %arg17, ptr addrspace(1) undef
+ store volatile i32 %arg18, ptr addrspace(1) undef
+ store volatile i32 %arg19, ptr addrspace(1) undef
+ store volatile i32 %arg20, ptr addrspace(1) undef
+ store volatile i32 %arg21, ptr addrspace(1) undef
+ store volatile i32 %arg22, ptr addrspace(1) undef
+ store volatile i32 %arg23, ptr addrspace(1) undef
+
+ store volatile i32 %arg24, ptr addrspace(1) undef
+ store volatile i32 %arg25, ptr addrspace(1) undef
+ store volatile i32 %arg26, ptr addrspace(1) undef
+ store volatile i32 %arg27, ptr addrspace(1) undef
+ store volatile i32 %arg28, ptr addrspace(1) undef
+ store volatile i32 %arg29, ptr addrspace(1) undef
+ store volatile i32 %arg30, ptr addrspace(1) undef
+ store volatile i32 %arg31, ptr addrspace(1) undef
ret void
}
@@ -409,7 +409,7 @@ define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x() #1 {
; GCN: s_swappc_b64
define void @func_call_too_many_args_use_workitem_id_x(i32 %arg0) #1 {
- store volatile i32 %arg0, i32 addrspace(1)* undef
+ store volatile i32 %arg0, ptr addrspace(1) undef
call void @too_many_args_use_workitem_id_x(
i32 10, i32 20, i32 30, i32 40,
i32 50, i32 60, i32 70, i32 80,
@@ -466,46 +466,46 @@ define void @too_many_args_use_workitem_id_x_byval(
i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7,
i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
- i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31, i32 addrspace(5)* byval(i32) %arg32) #1 {
+ i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31, ptr addrspace(5) byval(i32) %arg32) #1 {
%val = call i32 @llvm.amdgcn.workitem.id.x()
- store volatile i32 %val, i32 addrspace(1)* undef
-
- store volatile i32 %arg0, i32 addrspace(1)* undef
- store volatile i32 %arg1, i32 addrspace(1)* undef
- store volatile i32 %arg2, i32 addrspace(1)* undef
- store volatile i32 %arg3, i32 addrspace(1)* undef
- store volatile i32 %arg4, i32 addrspace(1)* undef
- store volatile i32 %arg5, i32 addrspace(1)* undef
- store volatile i32 %arg6, i32 addrspace(1)* undef
- store volatile i32 %arg7, i32 addrspace(1)* undef
-
- store volatile i32 %arg8, i32 addrspace(1)* undef
- store volatile i32 %arg9, i32 addrspace(1)* undef
- store volatile i32 %arg10, i32 addrspace(1)* undef
- store volatile i32 %arg11, i32 addrspace(1)* undef
- store volatile i32 %arg12, i32 addrspace(1)* undef
- store volatile i32 %arg13, i32 addrspace(1)* undef
- store volatile i32 %arg14, i32 addrspace(1)* undef
- store volatile i32 %arg15, i32 addrspace(1)* undef
-
- store volatile i32 %arg16, i32 addrspace(1)* undef
- store volatile i32 %arg17, i32 addrspace(1)* undef
- store volatile i32 %arg18, i32 addrspace(1)* undef
- store volatile i32 %arg19, i32 addrspace(1)* undef
- store volatile i32 %arg20, i32 addrspace(1)* undef
- store volatile i32 %arg21, i32 addrspace(1)* undef
- store volatile i32 %arg22, i32 addrspace(1)* undef
- store volatile i32 %arg23, i32 addrspace(1)* undef
-
- store volatile i32 %arg24, i32 addrspace(1)* undef
- store volatile i32 %arg25, i32 addrspace(1)* undef
- store volatile i32 %arg26, i32 addrspace(1)* undef
- store volatile i32 %arg27, i32 addrspace(1)* undef
- store volatile i32 %arg28, i32 addrspace(1)* undef
- store volatile i32 %arg29, i32 addrspace(1)* undef
- store volatile i32 %arg30, i32 addrspace(1)* undef
- store volatile i32 %arg31, i32 addrspace(1)* undef
- %private = load volatile i32, i32 addrspace(5)* %arg32
+ store volatile i32 %val, ptr addrspace(1) undef
+
+ store volatile i32 %arg0, ptr addrspace(1) undef
+ store volatile i32 %arg1, ptr addrspace(1) undef
+ store volatile i32 %arg2, ptr addrspace(1) undef
+ store volatile i32 %arg3, ptr addrspace(1) undef
+ store volatile i32 %arg4, ptr addrspace(1) undef
+ store volatile i32 %arg5, ptr addrspace(1) undef
+ store volatile i32 %arg6, ptr addrspace(1) undef
+ store volatile i32 %arg7, ptr addrspace(1) undef
+
+ store volatile i32 %arg8, ptr addrspace(1) undef
+ store volatile i32 %arg9, ptr addrspace(1) undef
+ store volatile i32 %arg10, ptr addrspace(1) undef
+ store volatile i32 %arg11, ptr addrspace(1) undef
+ store volatile i32 %arg12, ptr addrspace(1) undef
+ store volatile i32 %arg13, ptr addrspace(1) undef
+ store volatile i32 %arg14, ptr addrspace(1) undef
+ store volatile i32 %arg15, ptr addrspace(1) undef
+
+ store volatile i32 %arg16, ptr addrspace(1) undef
+ store volatile i32 %arg17, ptr addrspace(1) undef
+ store volatile i32 %arg18, ptr addrspace(1) undef
+ store volatile i32 %arg19, ptr addrspace(1) undef
+ store volatile i32 %arg20, ptr addrspace(1) undef
+ store volatile i32 %arg21, ptr addrspace(1) undef
+ store volatile i32 %arg22, ptr addrspace(1) undef
+ store volatile i32 %arg23, ptr addrspace(1) undef
+
+ store volatile i32 %arg24, ptr addrspace(1) undef
+ store volatile i32 %arg25, ptr addrspace(1) undef
+ store volatile i32 %arg26, ptr addrspace(1) undef
+ store volatile i32 %arg27, ptr addrspace(1) undef
+ store volatile i32 %arg28, ptr addrspace(1) undef
+ store volatile i32 %arg29, ptr addrspace(1) undef
+ store volatile i32 %arg30, ptr addrspace(1) undef
+ store volatile i32 %arg31, ptr addrspace(1) undef
+ %private = load volatile i32, ptr addrspace(5) %arg32
ret void
}
@@ -535,7 +535,7 @@ define void @too_many_args_use_workitem_id_x_byval(
; FIXEDABI: s_swappc_b64
define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_byval() #1 {
%alloca = alloca i32, align 4, addrspace(5)
- store volatile i32 999, i32 addrspace(5)* %alloca
+ store volatile i32 999, ptr addrspace(5) %alloca
call void @too_many_args_use_workitem_id_x_byval(
i32 10, i32 20, i32 30, i32 40,
i32 50, i32 60, i32 70, i32 80,
@@ -545,7 +545,7 @@ define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_byval() #1
i32 210, i32 220, i32 230, i32 240,
i32 250, i32 260, i32 270, i32 280,
i32 290, i32 300, i32 310, i32 320,
- i32 addrspace(5)* byval(i32) %alloca)
+ ptr addrspace(5) byval(i32) %alloca)
ret void
}
@@ -563,7 +563,7 @@ define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_byval() #1
; FIXEDABI: s_swappc_b64
define void @func_call_too_many_args_use_workitem_id_x_byval() #1 {
%alloca = alloca i32, align 4, addrspace(5)
- store volatile i32 999, i32 addrspace(5)* %alloca
+ store volatile i32 999, ptr addrspace(5) %alloca
call void @too_many_args_use_workitem_id_x_byval(
i32 10, i32 20, i32 30, i32 40,
i32 50, i32 60, i32 70, i32 80,
@@ -573,7 +573,7 @@ define void @func_call_too_many_args_use_workitem_id_x_byval() #1 {
i32 210, i32 220, i32 230, i32 240,
i32 250, i32 260, i32 270, i32 280,
i32 290, i32 300, i32 310, i32 320,
- i32 addrspace(5)* byval(i32) %alloca)
+ ptr addrspace(5) byval(i32) %alloca)
ret void
}
@@ -593,47 +593,47 @@ define void @too_many_args_use_workitem_id_xyz(
i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31) #1 {
%val0 = call i32 @llvm.amdgcn.workitem.id.x()
- store volatile i32 %val0, i32 addrspace(1)* undef
+ store volatile i32 %val0, ptr addrspace(1) undef
%val1 = call i32 @llvm.amdgcn.workitem.id.y()
- store volatile i32 %val1, i32 addrspace(1)* undef
+ store volatile i32 %val1, ptr addrspace(1) undef
%val2 = call i32 @llvm.amdgcn.workitem.id.z()
- store volatile i32 %val2, i32 addrspace(1)* undef
-
- store volatile i32 %arg0, i32 addrspace(1)* undef
- store volatile i32 %arg1, i32 addrspace(1)* undef
- store volatile i32 %arg2, i32 addrspace(1)* undef
- store volatile i32 %arg3, i32 addrspace(1)* undef
- store volatile i32 %arg4, i32 addrspace(1)* undef
- store volatile i32 %arg5, i32 addrspace(1)* undef
- store volatile i32 %arg6, i32 addrspace(1)* undef
- store volatile i32 %arg7, i32 addrspace(1)* undef
-
- store volatile i32 %arg8, i32 addrspace(1)* undef
- store volatile i32 %arg9, i32 addrspace(1)* undef
- store volatile i32 %arg10, i32 addrspace(1)* undef
- store volatile i32 %arg11, i32 addrspace(1)* undef
- store volatile i32 %arg12, i32 addrspace(1)* undef
- store volatile i32 %arg13, i32 addrspace(1)* undef
- store volatile i32 %arg14, i32 addrspace(1)* undef
- store volatile i32 %arg15, i32 addrspace(1)* undef
-
- store volatile i32 %arg16, i32 addrspace(1)* undef
- store volatile i32 %arg17, i32 addrspace(1)* undef
- store volatile i32 %arg18, i32 addrspace(1)* undef
- store volatile i32 %arg19, i32 addrspace(1)* undef
- store volatile i32 %arg20, i32 addrspace(1)* undef
- store volatile i32 %arg21, i32 addrspace(1)* undef
- store volatile i32 %arg22, i32 addrspace(1)* undef
- store volatile i32 %arg23, i32 addrspace(1)* undef
-
- store volatile i32 %arg24, i32 addrspace(1)* undef
- store volatile i32 %arg25, i32 addrspace(1)* undef
- store volatile i32 %arg26, i32 addrspace(1)* undef
- store volatile i32 %arg27, i32 addrspace(1)* undef
- store volatile i32 %arg28, i32 addrspace(1)* undef
- store volatile i32 %arg29, i32 addrspace(1)* undef
- store volatile i32 %arg30, i32 addrspace(1)* undef
- store volatile i32 %arg31, i32 addrspace(1)* undef
+ store volatile i32 %val2, ptr addrspace(1) undef
+
+ store volatile i32 %arg0, ptr addrspace(1) undef
+ store volatile i32 %arg1, ptr addrspace(1) undef
+ store volatile i32 %arg2, ptr addrspace(1) undef
+ store volatile i32 %arg3, ptr addrspace(1) undef
+ store volatile i32 %arg4, ptr addrspace(1) undef
+ store volatile i32 %arg5, ptr addrspace(1) undef
+ store volatile i32 %arg6, ptr addrspace(1) undef
+ store volatile i32 %arg7, ptr addrspace(1) undef
+
+ store volatile i32 %arg8, ptr addrspace(1) undef
+ store volatile i32 %arg9, ptr addrspace(1) undef
+ store volatile i32 %arg10, ptr addrspace(1) undef
+ store volatile i32 %arg11, ptr addrspace(1) undef
+ store volatile i32 %arg12, ptr addrspace(1) undef
+ store volatile i32 %arg13, ptr addrspace(1) undef
+ store volatile i32 %arg14, ptr addrspace(1) undef
+ store volatile i32 %arg15, ptr addrspace(1) undef
+
+ store volatile i32 %arg16, ptr addrspace(1) undef
+ store volatile i32 %arg17, ptr addrspace(1) undef
+ store volatile i32 %arg18, ptr addrspace(1) undef
+ store volatile i32 %arg19, ptr addrspace(1) undef
+ store volatile i32 %arg20, ptr addrspace(1) undef
+ store volatile i32 %arg21, ptr addrspace(1) undef
+ store volatile i32 %arg22, ptr addrspace(1) undef
+ store volatile i32 %arg23, ptr addrspace(1) undef
+
+ store volatile i32 %arg24, ptr addrspace(1) undef
+ store volatile i32 %arg25, ptr addrspace(1) undef
+ store volatile i32 %arg26, ptr addrspace(1) undef
+ store volatile i32 %arg27, ptr addrspace(1) undef
+ store volatile i32 %arg28, ptr addrspace(1) undef
+ store volatile i32 %arg29, ptr addrspace(1) undef
+ store volatile i32 %arg30, ptr addrspace(1) undef
+ store volatile i32 %arg31, ptr addrspace(1) undef
ret void
}
@@ -684,46 +684,46 @@ define void @too_many_args_use_workitem_id_x_stack_yz(
i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30) #1 {
%val0 = call i32 @llvm.amdgcn.workitem.id.x()
- store volatile i32 %val0, i32 addrspace(1)* undef
+ store volatile i32 %val0, ptr addrspace(1) undef
%val1 = call i32 @llvm.amdgcn.workitem.id.y()
- store volatile i32 %val1, i32 addrspace(1)* undef
+ store volatile i32 %val1, ptr addrspace(1) undef
%val2 = call i32 @llvm.amdgcn.workitem.id.z()
- store volatile i32 %val2, i32 addrspace(1)* undef
-
- store volatile i32 %arg0, i32 addrspace(1)* undef
- store volatile i32 %arg1, i32 addrspace(1)* undef
- store volatile i32 %arg2, i32 addrspace(1)* undef
- store volatile i32 %arg3, i32 addrspace(1)* undef
- store volatile i32 %arg4, i32 addrspace(1)* undef
- store volatile i32 %arg5, i32 addrspace(1)* undef
- store volatile i32 %arg6, i32 addrspace(1)* undef
- store volatile i32 %arg7, i32 addrspace(1)* undef
-
- store volatile i32 %arg8, i32 addrspace(1)* undef
- store volatile i32 %arg9, i32 addrspace(1)* undef
- store volatile i32 %arg10, i32 addrspace(1)* undef
- store volatile i32 %arg11, i32 addrspace(1)* undef
- store volatile i32 %arg12, i32 addrspace(1)* undef
- store volatile i32 %arg13, i32 addrspace(1)* undef
- store volatile i32 %arg14, i32 addrspace(1)* undef
- store volatile i32 %arg15, i32 addrspace(1)* undef
-
- store volatile i32 %arg16, i32 addrspace(1)* undef
- store volatile i32 %arg17, i32 addrspace(1)* undef
- store volatile i32 %arg18, i32 addrspace(1)* undef
- store volatile i32 %arg19, i32 addrspace(1)* undef
- store volatile i32 %arg20, i32 addrspace(1)* undef
- store volatile i32 %arg21, i32 addrspace(1)* undef
- store volatile i32 %arg22, i32 addrspace(1)* undef
- store volatile i32 %arg23, i32 addrspace(1)* undef
-
- store volatile i32 %arg24, i32 addrspace(1)* undef
- store volatile i32 %arg25, i32 addrspace(1)* undef
- store volatile i32 %arg26, i32 addrspace(1)* undef
- store volatile i32 %arg27, i32 addrspace(1)* undef
- store volatile i32 %arg28, i32 addrspace(1)* undef
- store volatile i32 %arg29, i32 addrspace(1)* undef
- store volatile i32 %arg30, i32 addrspace(1)* undef
+ store volatile i32 %val2, ptr addrspace(1) undef
+
+ store volatile i32 %arg0, ptr addrspace(1) undef
+ store volatile i32 %arg1, ptr addrspace(1) undef
+ store volatile i32 %arg2, ptr addrspace(1) undef
+ store volatile i32 %arg3, ptr addrspace(1) undef
+ store volatile i32 %arg4, ptr addrspace(1) undef
+ store volatile i32 %arg5, ptr addrspace(1) undef
+ store volatile i32 %arg6, ptr addrspace(1) undef
+ store volatile i32 %arg7, ptr addrspace(1) undef
+
+ store volatile i32 %arg8, ptr addrspace(1) undef
+ store volatile i32 %arg9, ptr addrspace(1) undef
+ store volatile i32 %arg10, ptr addrspace(1) undef
+ store volatile i32 %arg11, ptr addrspace(1) undef
+ store volatile i32 %arg12, ptr addrspace(1) undef
+ store volatile i32 %arg13, ptr addrspace(1) undef
+ store volatile i32 %arg14, ptr addrspace(1) undef
+ store volatile i32 %arg15, ptr addrspace(1) undef
+
+ store volatile i32 %arg16, ptr addrspace(1) undef
+ store volatile i32 %arg17, ptr addrspace(1) undef
+ store volatile i32 %arg18, ptr addrspace(1) undef
+ store volatile i32 %arg19, ptr addrspace(1) undef
+ store volatile i32 %arg20, ptr addrspace(1) undef
+ store volatile i32 %arg21, ptr addrspace(1) undef
+ store volatile i32 %arg22, ptr addrspace(1) undef
+ store volatile i32 %arg23, ptr addrspace(1) undef
+
+ store volatile i32 %arg24, ptr addrspace(1) undef
+ store volatile i32 %arg25, ptr addrspace(1) undef
+ store volatile i32 %arg26, ptr addrspace(1) undef
+ store volatile i32 %arg27, ptr addrspace(1) undef
+ store volatile i32 %arg28, ptr addrspace(1) undef
+ store volatile i32 %arg29, ptr addrspace(1) undef
+ store volatile i32 %arg30, ptr addrspace(1) undef
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
index 75c496ab2632..85c76b5146e4 100644
--- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
+++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
@@ -5,18 +5,18 @@
; GCN-LABEL: {{^}}kernel:
; GCN: s_endpgm
-define spir_kernel void @kernel(i32 addrspace(1)* %out) {
+define spir_kernel void @kernel(ptr addrspace(1) %out) {
entry:
- store i32 0, i32 addrspace(1)* %out
+ store i32 0, ptr addrspace(1) %out
ret void
}
; FIXME: This is treated like a kernel
; XGCN-LABEL: {{^}}func:
; XGCN: s_endpgm
-; define spir_func void @func(i32 addrspace(1)* %out) {
+; define spir_func void @func(ptr addrspace(1) %out) {
; entry:
-; store i32 0, i32 addrspace(1)* %out
+; store i32 0, ptr addrspace(1) %out
; ret void
; }
@@ -63,7 +63,7 @@ define coldcc float @coldcc(float %arg0) #0 {
; GCN: s_swappc_b64
define amdgpu_kernel void @call_coldcc() #0 {
%val = call float @coldcc(float 1.0)
- store float %val, float addrspace(1)* undef
+ store float %val, ptr addrspace(1) undef
ret void
}
@@ -72,7 +72,7 @@ define amdgpu_kernel void @call_coldcc() #0 {
; GCN: s_swappc_b64
define amdgpu_kernel void @call_fastcc() #0 {
%val = call float @fastcc(float 1.0)
- store float %val, float addrspace(1)* undef
+ store float %val, ptr addrspace(1) undef
ret void
}
@@ -176,7 +176,7 @@ define amdgpu_ps <2 x half> @ps_mesa_inreg_v2f16(<2 x half> inreg %arg0) {
; SI: v_add_i32_e32 v0, vcc, 0x10000, v0
define amdgpu_ps void @ps_mesa_v2i16(<2 x i16> %arg0) {
%add = add <2 x i16> %arg0, <i16 1, i16 1>
- store <2 x i16> %add, <2 x i16> addrspace(1)* undef
+ store <2 x i16> %add, ptr addrspace(1) undef
ret void
}
@@ -195,7 +195,7 @@ define amdgpu_ps void @ps_mesa_v2i16(<2 x i16> %arg0) {
; SI: s_add_i32 s0, s0, 0x10000
define amdgpu_ps void @ps_mesa_inreg_v2i16(<2 x i16> inreg %arg0) {
%add = add <2 x i16> %arg0, <i16 1, i16 1>
- store <2 x i16> %add, <2 x i16> addrspace(1)* undef
+ store <2 x i16> %add, ptr addrspace(1) undef
ret void
}
@@ -236,7 +236,7 @@ define amdgpu_ps <4 x half> @ps_mesa_inreg_v4f16(<4 x half> inreg %arg0) {
; GCN-DAG: s_add_i32 s{{[0-9]*}}, s2, 3
define amdgpu_ps void @ps_mesa_inreg_v3i32(<3 x i32> inreg %arg0) {
%add = add <3 x i32> %arg0, <i32 1, i32 2, i32 3>
- store <3 x i32> %add, <3 x i32> addrspace(1)* undef
+ store <3 x i32> %add, ptr addrspace(1) undef
ret void
}
@@ -246,7 +246,7 @@ define amdgpu_ps void @ps_mesa_inreg_v3i32(<3 x i32> inreg %arg0) {
; GCN-DAG: v_add_f32{{.*}}, s2, 4.0
define amdgpu_ps void @ps_mesa_inreg_v3f32(<3 x float> inreg %arg0) {
%add = fadd <3 x float> %arg0, <float 1.0, float 2.0, float 4.0>
- store <3 x float> %add, <3 x float> addrspace(1)* undef
+ store <3 x float> %add, ptr addrspace(1) undef
ret void
}
@@ -258,7 +258,7 @@ define amdgpu_ps void @ps_mesa_inreg_v3f32(<3 x float> inreg %arg0) {
; GCN-DAG: s_add_i32 s{{[0-9]*}}, s4, 5
define amdgpu_ps void @ps_mesa_inreg_v5i32(<5 x i32> inreg %arg0) {
%add = add <5 x i32> %arg0, <i32 1, i32 2, i32 3, i32 4, i32 5>
- store <5 x i32> %add, <5 x i32> addrspace(1)* undef
+ store <5 x i32> %add, ptr addrspace(1) undef
ret void
}
@@ -270,7 +270,7 @@ define amdgpu_ps void @ps_mesa_inreg_v5i32(<5 x i32> inreg %arg0) {
; GCN-DAG: v_add_f32{{.*}}, s4, 0.5
define amdgpu_ps void @ps_mesa_inreg_v5f32(<5 x float> inreg %arg0) {
%add = fadd <5 x float> %arg0, <float 1.0, float 2.0, float 4.0, float -1.0, float 0.5>
- store <5 x float> %add, <5 x float> addrspace(1)* undef
+ store <5 x float> %add, ptr addrspace(1) undef
ret void
}
@@ -280,7 +280,7 @@ define amdgpu_ps void @ps_mesa_inreg_v5f32(<5 x float> inreg %arg0) {
; GCN-DAG: v_add_{{.*}}, 3, v2
define amdgpu_ps void @ps_mesa_v3i32(<3 x i32> %arg0) {
%add = add <3 x i32> %arg0, <i32 1, i32 2, i32 3>
- store <3 x i32> %add, <3 x i32> addrspace(1)* undef
+ store <3 x i32> %add, ptr addrspace(1) undef
ret void
}
@@ -290,7 +290,7 @@ define amdgpu_ps void @ps_mesa_v3i32(<3 x i32> %arg0) {
; GCN-DAG: v_add_{{.*}}, 4.0, v2
define amdgpu_ps void @ps_mesa_v3f32(<3 x float> %arg0) {
%add = fadd <3 x float> %arg0, <float 1.0, float 2.0, float 4.0>
- store <3 x float> %add, <3 x float> addrspace(1)* undef
+ store <3 x float> %add, ptr addrspace(1) undef
ret void
}
@@ -302,7 +302,7 @@ define amdgpu_ps void @ps_mesa_v3f32(<3 x float> %arg0) {
; GCN-DAG: v_add_{{.*}}, 5, v4
define amdgpu_ps void @ps_mesa_v5i32(<5 x i32> %arg0) {
%add = add <5 x i32> %arg0, <i32 1, i32 2, i32 3, i32 4, i32 5>
- store <5 x i32> %add, <5 x i32> addrspace(1)* undef
+ store <5 x i32> %add, ptr addrspace(1) undef
ret void
}
@@ -314,7 +314,7 @@ define amdgpu_ps void @ps_mesa_v5i32(<5 x i32> %arg0) {
; GCN-DAG: v_add_f32{{.*}}, 0.5, v4
define amdgpu_ps void @ps_mesa_v5f32(<5 x float> %arg0) {
%add = fadd <5 x float> %arg0, <float 1.0, float 2.0, float 4.0, float -1.0, float 0.5>
- store <5 x float> %add, <5 x float> addrspace(1)* undef
+ store <5 x float> %add, ptr addrspace(1) undef
ret void
}
@@ -323,7 +323,7 @@ define amdgpu_ps void @ps_mesa_v5f32(<5 x float> %arg0) {
; VI: v_add_u16_e32 v{{[0-9]+}}, v0, v0
define amdgpu_ps void @ps_mesa_i16(i16 %arg0) {
%add = add i16 %arg0, %arg0
- store i16 %add, i16 addrspace(1)* undef
+ store i16 %add, ptr addrspace(1) undef
ret void
}
@@ -331,7 +331,7 @@ define amdgpu_ps void @ps_mesa_i16(i16 %arg0) {
; GCN: s_add_i32 s{{[0-9]+}}, s0, s0
define amdgpu_ps void @ps_mesa_inreg_i16(i16 inreg %arg0) {
%add = add i16 %arg0, %arg0
- store i16 %add, i16 addrspace(1)* undef
+ store i16 %add, ptr addrspace(1) undef
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/inline-calls.ll b/llvm/test/CodeGen/AMDGPU/inline-calls.ll
index 134cd301b974..e1cdfa834608 100644
--- a/llvm/test/CodeGen/AMDGPU/inline-calls.ll
+++ b/llvm/test/CodeGen/AMDGPU/inline-calls.ll
@@ -11,23 +11,23 @@ entry:
; CHECK: {{^}}kernel:
; GCN-NOT: s_swappc_b64
-define amdgpu_kernel void @kernel(i32 addrspace(1)* %out) {
+define amdgpu_kernel void @kernel(ptr addrspace(1) %out) {
entry:
%tmp0 = call i32 @func(i32 1)
- store i32 %tmp0, i32 addrspace(1)* %out
+ store i32 %tmp0, ptr addrspace(1) %out
ret void
}
; CHECK: func_alias
; R600-NOT: func_alias
- at func_alias = alias i32 (i32), i32 (i32)* @func
+ at func_alias = alias i32 (i32), ptr @func
; CHECK-NOT: {{^}}kernel3:
; GCN-NOT: s_swappc_b64
; R600: {{^}}kernel3:
-define amdgpu_kernel void @kernel3(i32 addrspace(1)* %out) {
+define amdgpu_kernel void @kernel3(ptr addrspace(1) %out) {
entry:
%tmp0 = call i32 @func_alias(i32 1)
- store i32 %tmp0, i32 addrspace(1)* %out
+ store i32 %tmp0, ptr addrspace(1) %out
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/nested-calls.ll b/llvm/test/CodeGen/AMDGPU/nested-calls.ll
index 2ae8530e1ed1..88e3949370e2 100644
--- a/llvm/test/CodeGen/AMDGPU/nested-calls.ll
+++ b/llvm/test/CodeGen/AMDGPU/nested-calls.ll
@@ -47,10 +47,9 @@ define void @test_func_call_external_void_func_i32_imm() #0 {
; GCN: s_setpc_b64
define void @test_func_call_external_void_func_i32_imm_stack_use() #0 {
%alloca = alloca [16 x i32], align 4, addrspace(5)
- %gep0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
- %gep15 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 16
- store volatile i32 0, i32 addrspace(5)* %gep0
- store volatile i32 0, i32 addrspace(5)* %gep15
+ %gep15 = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 16
+ store volatile i32 0, ptr addrspace(5) %alloca
+ store volatile i32 0, ptr addrspace(5) %gep15
call void @external_void_func_i32(i32 42)
ret void
}
diff --git a/llvm/test/CodeGen/AMDGPU/sibling-call.ll b/llvm/test/CodeGen/AMDGPU/sibling-call.ll
index 054d4ef3651e..dd0c0d54e5bd 100644
--- a/llvm/test/CodeGen/AMDGPU/sibling-call.ll
+++ b/llvm/test/CodeGen/AMDGPU/sibling-call.ll
@@ -25,8 +25,8 @@ define fastcc i32 @i32_fastcc_i32_i32(i32 %arg0, i32 %arg1) #1 {
; GCN: ; ScratchSize: 68
define fastcc i32 @i32_fastcc_i32_i32_stack_object(i32 %arg0, i32 %arg1) #1 {
%alloca = alloca [16 x i32], align 4, addrspace(5)
- %gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 5
- store volatile i32 9, i32 addrspace(5)* %gep
+ %gep = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 5
+ store volatile i32 9, ptr addrspace(5) %gep
%add0 = add i32 %arg0, %arg1
ret i32 %add0
}
@@ -46,8 +46,8 @@ entry:
define fastcc i32 @sibling_call_i32_fastcc_i32_i32_stack_object(i32 %a, i32 %b, i32 %c) #1 {
entry:
%alloca = alloca [16 x i32], align 4, addrspace(5)
- %gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 5
- store volatile i32 9, i32 addrspace(5)* %gep
+ %gep = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 5
+ store volatile i32 9, ptr addrspace(5) %gep
%ret = tail call fastcc i32 @i32_fastcc_i32_i32(i32 %a, i32 %b)
ret i32 %ret
}
@@ -60,8 +60,8 @@ entry:
define fastcc i32 @sibling_call_i32_fastcc_i32_i32_callee_stack_object(i32 %a, i32 %b, i32 %c) #1 {
entry:
%alloca = alloca [16 x i32], align 4, addrspace(5)
- %gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 5
- store volatile i32 9, i32 addrspace(5)* %gep
+ %gep = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 5
+ store volatile i32 9, ptr addrspace(5) %gep
%ret = tail call fastcc i32 @i32_fastcc_i32_i32_stack_object(i32 %a, i32 %b)
ret i32 %ret
}
@@ -91,8 +91,8 @@ entry:
; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
; GCN-NEXT: s_setpc_b64 s[30:31]
-define hidden fastcc i32 @i32_fastcc_i32_byval_i32(i32 %arg0, i32 addrspace(5)* byval(i32) align 4 %arg1) #1 {
- %arg1.load = load i32, i32 addrspace(5)* %arg1, align 4
+define hidden fastcc i32 @i32_fastcc_i32_byval_i32(i32 %arg0, ptr addrspace(5) byval(i32) align 4 %arg1) #1 {
+ %arg1.load = load i32, ptr addrspace(5) %arg1, align 4
%add0 = add i32 %arg0, %arg1.load
ret i32 %add0
}
@@ -104,9 +104,9 @@ define hidden fastcc i32 @i32_fastcc_i32_byval_i32(i32 %arg0, i32 addrspace(5)*
; GCN: s_swappc_b64
; GCN-NOT: v_readlane_b32 s32
; GCN: s_setpc_b64
-define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32_byval_parent(i32 %a, i32 addrspace(5)* byval(i32) %b.byval, i32 %c) #1 {
+define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32_byval_parent(i32 %a, ptr addrspace(5) byval(i32) %b.byval, i32 %c) #1 {
entry:
- %ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, i32 addrspace(5)* byval(i32) %b.byval)
+ %ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, ptr addrspace(5) byval(i32) %b.byval)
ret i32 %ret
}
@@ -122,7 +122,7 @@ entry:
; GCN-NEXT: s_setpc_b64
define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32(i32 %a, [32 x i32] %large) #1 {
entry:
- %ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, i32 addrspace(5)* byval(i32) inttoptr (i32 16 to i32 addrspace(5)*))
+ %ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, ptr addrspace(5) byval(i32) inttoptr (i32 16 to ptr addrspace(5)))
ret i32 %ret
}
@@ -177,8 +177,8 @@ entry:
define fastcc i32 @sibling_call_i32_fastcc_i32_i32_a32i32_stack_object(i32 %a, i32 %b, [32 x i32] %c) #1 {
entry:
%alloca = alloca [16 x i32], align 4, addrspace(5)
- %gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 5
- store volatile i32 9, i32 addrspace(5)* %gep
+ %gep = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 5
+ store volatile i32 9, ptr addrspace(5) %gep
%ret = tail call fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] %c)
ret i32 %ret
}
@@ -253,8 +253,8 @@ entry:
define fastcc i32 @sibling_call_stack_objecti32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] %c) #1 {
entry:
%alloca = alloca [16 x i32], align 4, addrspace(5)
- %gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 5
- store volatile i32 9, i32 addrspace(5)* %gep
+ %gep = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 5
+ store volatile i32 9, ptr addrspace(5) %gep
%ret = tail call fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] %c)
ret i32 %ret
}
@@ -268,13 +268,13 @@ entry:
define fastcc i32 @sibling_call_stack_objecti32_fastcc_i32_i32_a32i32_larger_arg_area(i32 %a, i32 %b, [36 x i32] %c) #1 {
entry:
%alloca = alloca [16 x i32], align 4, addrspace(5)
- %gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 5
- store volatile i32 9, i32 addrspace(5)* %gep
+ %gep = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 5
+ store volatile i32 9, ptr addrspace(5) %gep
%ret = tail call fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] zeroinitializer)
ret i32 %ret
}
- at func_ptr_gv = external unnamed_addr addrspace(4) constant i32(i32, i32)*, align 4
+ at func_ptr_gv = external unnamed_addr addrspace(4) constant ptr, align 4
; Do support tail calls with a uniform, but unknown, callee.
; GCN-LABEL: {{^}}indirect_uniform_sibling_call_i32_fastcc_i32_i32:
@@ -283,7 +283,7 @@ entry:
; GCN: s_setpc_b64 [[FUNC_PTR]]
define hidden fastcc i32 @indirect_uniform_sibling_call_i32_fastcc_i32_i32(i32 %a, i32 %b, i32 %c) #1 {
entry:
- %func.ptr.load = load i32(i32, i32)*, i32(i32, i32)* addrspace(4)* @func_ptr_gv
+ %func.ptr.load = load ptr, ptr addrspace(4) @func_ptr_gv
%ret = tail call fastcc i32 %func.ptr.load(i32 %a, i32 %b)
ret i32 %ret
}
@@ -297,14 +297,14 @@ entry:
; GCN: s_swappc_b64
; GCN: s_cbranch_execnz
; GCN: s_setpc_b64
-define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(i32(i32, i32)* %func.ptr, i32 %a, i32 %b, i32 %c) #1 {
+define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr %func.ptr, i32 %a, i32 %b, i32 %c) #1 {
entry:
%add = add i32 %b, %c
%ret = tail call fastcc i32 %func.ptr(i32 %a, i32 %add)
ret i32 %ret
}
-declare hidden void @void_fastcc_multi_byval(i32 %a, [3 x i32] addrspace(5)* byval([3 x i32]) align 16, [2 x i64] addrspace(5)* byval([2 x i64]))
+declare hidden void @void_fastcc_multi_byval(i32 %a, ptr addrspace(5) byval([3 x i32]) align 16, ptr addrspace(5) byval([2 x i64]))
; GCN-LABEL: {{^}}sibling_call_fastcc_multi_byval:
; GCN-DAG: s_getpc_b64 [[TARGET_ADDR:s\[[0-9]+:[0-9]+\]]]
@@ -333,13 +333,13 @@ define fastcc void @sibling_call_fastcc_multi_byval(i32 %a, [64 x i32]) #1 {
entry:
%alloca0 = alloca [3 x i32], align 16, addrspace(5)
%alloca1 = alloca [2 x i64], align 8, addrspace(5)
- store [3 x i32] [i32 9, i32 9, i32 9], [3 x i32] addrspace(5)* %alloca0
- store [2 x i64] zeroinitializer, [2 x i64] addrspace(5)* %alloca1
- tail call fastcc void @void_fastcc_multi_byval(i32 %a, [3 x i32] addrspace(5)* byval([3 x i32]) %alloca0, [2 x i64] addrspace(5)* byval([2 x i64]) %alloca1)
+ store [3 x i32] [i32 9, i32 9, i32 9], ptr addrspace(5) %alloca0
+ store [2 x i64] zeroinitializer, ptr addrspace(5) %alloca1
+ tail call fastcc void @void_fastcc_multi_byval(i32 %a, ptr addrspace(5) byval([3 x i32]) %alloca0, ptr addrspace(5) byval([2 x i64]) %alloca1)
ret void
}
-declare hidden void @void_fastcc_byval_and_stack_passed([3 x i32] addrspace(5)* byval([3 x i32]) align 16, [32 x i32], i32)
+declare hidden void @void_fastcc_byval_and_stack_passed(ptr addrspace(5) byval([3 x i32]) align 16, [32 x i32], i32)
; Callee has a byval and non-byval stack passed argument
; GCN-LABEL: {{^}}sibling_call_byval_and_stack_passed:
@@ -364,8 +364,8 @@ declare hidden void @void_fastcc_byval_and_stack_passed([3 x i32] addrspace(5)*
define fastcc void @sibling_call_byval_and_stack_passed(i32 %stack.out.arg, [64 x i32]) #1 {
entry:
%alloca = alloca [3 x i32], align 16, addrspace(5)
- store [3 x i32] [i32 9, i32 9, i32 9], [3 x i32] addrspace(5)* %alloca
- tail call fastcc void @void_fastcc_byval_and_stack_passed([3 x i32] addrspace(5)* byval([3 x i32]) %alloca, [32 x i32] zeroinitializer, i32 %stack.out.arg)
+ store [3 x i32] [i32 9, i32 9, i32 9], ptr addrspace(5) %alloca
+ tail call fastcc void @void_fastcc_byval_and_stack_passed(ptr addrspace(5) byval([3 x i32]) %alloca, [32 x i32] zeroinitializer, i32 %stack.out.arg)
ret void
}
@@ -383,7 +383,7 @@ entry:
ret i64 %ret
}
-declare hidden fastcc i8 addrspace(1)* @p1i8_fastcc_p1i8(i8 addrspace(1)* %arg0)
+declare hidden fastcc ptr addrspace(1) @p1i8_fastcc_p1i8(ptr addrspace(1) %arg0)
; GCN-LABEL: {{^}}sibling_call_p1i8_fastcc_p1i8:
; GCN: s_waitcnt
@@ -391,10 +391,10 @@ declare hidden fastcc i8 addrspace(1)* @p1i8_fastcc_p1i8(i8 addrspace(1)* %arg0)
; GCN-NEXT: s_add_u32
; GCN-NEXT: s_addc_u32
; GCN-NEXT: s_setpc_b64
-define hidden fastcc i8 addrspace(1)* @sibling_call_p1i8_fastcc_p1i8(i8 addrspace(1)* %a) #1 {
+define hidden fastcc ptr addrspace(1) @sibling_call_p1i8_fastcc_p1i8(ptr addrspace(1) %a) #1 {
entry:
- %ret = tail call fastcc i8 addrspace(1)* @p1i8_fastcc_p1i8(i8 addrspace(1)* %a)
- ret i8 addrspace(1)* %ret
+ %ret = tail call fastcc ptr addrspace(1) @p1i8_fastcc_p1i8(ptr addrspace(1) %a)
+ ret ptr addrspace(1) %ret
}
declare hidden fastcc i16 @i16_fastcc_i16(i16 %arg0)
diff --git a/llvm/test/CodeGen/AMDGPU/stress-calls.ll b/llvm/test/CodeGen/AMDGPU/stress-calls.ll
index 8498076bf29a..6c6f81f0922d 100644
--- a/llvm/test/CodeGen/AMDGPU/stress-calls.ll
+++ b/llvm/test/CodeGen/AMDGPU/stress-calls.ll
@@ -21,14 +21,14 @@ entry:
ret i32 %tmp0
}
-define amdgpu_kernel void @kernel(i32 addrspace(1)* %out) {
+define amdgpu_kernel void @kernel(ptr addrspace(1) %out) {
entry:
%tmp0 = call i32 @alwaysinline_func(i32 1)
- store volatile i32 %tmp0, i32 addrspace(1)* %out
+ store volatile i32 %tmp0, ptr addrspace(1) %out
%tmp1 = call i32 @noinline_func(i32 1)
- store volatile i32 %tmp1, i32 addrspace(1)* %out
+ store volatile i32 %tmp1, ptr addrspace(1) %out
%tmp2 = call i32 @unmarked_func(i32 1)
- store volatile i32 %tmp2, i32 addrspace(1)* %out
+ store volatile i32 %tmp2, ptr addrspace(1) %out
ret void
}
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