[PATCH] D138949: AMDGPU: Remove ImagePSV and move images to addrspace 7

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle created this revision.
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Following up on the removal of BufferPSV in commit 43b86bf992 <https://reviews.llvm.org/rG43b86bf9921be5741017db47ae2fa1c8148680b4> ("AMDGPU:
Remove BufferPseudoSourceValue")

It is unclear what exactly the right address space for images should be.
They seem morally closest to buffers, so that's what I went with. In
practical terms, address space 7 is better than address space 0 because
it can't alias with LDS.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138949

Files:
  llvm/lib/Target/AMDGPU/AMDGPUMIRFormatter.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
  llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
  llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir
  llvm/test/CodeGen/AMDGPU/hard-clauses.mir
  llvm/test/CodeGen/AMDGPU/nsa-reassign.mir
  llvm/test/CodeGen/AMDGPU/release-vgprs.mir
  llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
  llvm/test/CodeGen/AMDGPU/unallocatable-bundle-regression.mir
  llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll
  llvm/test/CodeGen/AMDGPU/unsupported-image-g16.ll
  llvm/test/CodeGen/AMDGPU/verify-image-vaddr-align.mir
  llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
  llvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir
  llvm/test/CodeGen/AMDGPU/wqm.mir
  llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll

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