[PATCH] D138922: [SPARC] Lower SELECT_CC to MOVr on 64-bit target whenever possible

[Matt Arsenault via Phabricator via llvm-commits]

arsenm requested changes to this revision.
arsenm added inline comments.
This revision now requires changes to proceed.


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Comment at: llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp:205-206
+  case SP::FMOVRQ:
+    // Make sure CC is a register conditional flag.
+    CC = (CC < 48) ? (CC + 48) : CC;
+    break;
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Can't say I understand these magic numbers but they seem to be following a pattern


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Comment at: llvm/lib/Target/Sparc/Sparc.h:97
+    REG_GZ = 6 + 48,  // Greater than zero
+    REG_GEZ = 7 + 48  // Greater than or equal to zero
+  };
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Could add _BEGIN/ _END entries for these to avoid the hardcoded numbers other places


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Comment at: llvm/lib/Target/Sparc/SparcISelLowering.cpp:1459
+/// code operates on unsigned integers.
+static bool IsUnsignedIntCompare(ISD::CondCode CC) {
+  return CC == ISD::SETULT || CC == ISD::SETUGT || CC == ISD::SETULE ||
----------------
ISD::isUnsignedIntSetCC already exists


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Comment at: llvm/lib/Target/Sparc/SparcISelLowering.cpp:1466
+/// rcond condition.
+static SPCC::CondCodes IntCondCCodeToRcond(ISD::CondCode CC) {
+  switch (CC) {
----------------
Lowercase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138922/new/

https://reviews.llvm.org/D138922