[PATCH] D138817: [AAch64] Optimize muls with operands having enough sign bits.

[Biplob Mishra via Phabricator via llvm-commits]

bipmis updated this revision to Diff 478635.
bipmis marked an inline comment as done.
bipmis added a comment.

Fixed for scenario where smullwithonesignbits is treated as commutative. 
Added corner case tests where signBits<32


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138817/new/

https://reviews.llvm.org/D138817

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
  llvm/test/CodeGen/AArch64/aarch64-smull.ll

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