[llvm] 0daa3df - [AMDGPU] Use GCNSubtarget::hasInstPrefetch instead of generation check. NFC.
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 29 09:39:02 PST 2022
Author: Jay Foad
Date: 2022-11-29T17:36:33Z
New Revision: 0daa3df3a543af3b95a5de1fa2af3356a42453a2
URL: https://github.com/llvm/llvm-project/commit/0daa3df3a543af3b95a5de1fa2af3356a42453a2
DIFF: https://github.com/llvm/llvm-project/commit/0daa3df3a543af3b95a5de1fa2af3356a42453a2.diff
LOG: [AMDGPU] Use GCNSubtarget::hasInstPrefetch instead of generation check. NFC.
Added:
Modified:
llvm/lib/Target/AMDGPU/GCNSubtarget.h
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index b0ce007de572..731e203be1f0 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -783,6 +783,8 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
return getGeneration() < SEA_ISLANDS;
}
+ bool hasInstPrefetch() const { return getGeneration() >= GFX10; }
+
// Scratch is allocated in 256 dword per wave blocks for the entire
// wavefront. When viewed from the perspective of an arbitrary workitem, this
// is 4-byte aligned.
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 1cba1e446ed4..72942ae06f89 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -12670,8 +12670,7 @@ Align SITargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
const Align CacheLineAlign = Align(64);
// Pre-GFX10 target did not benefit from loop alignment
- if (!ML || DisableLoopAlignment ||
- (getSubtarget()->getGeneration() < AMDGPUSubtarget::GFX10) ||
+ if (!ML || DisableLoopAlignment || !getSubtarget()->hasInstPrefetch() ||
getSubtarget()->hasInstFwdPrefetchBug())
return PrefAlign;
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