[llvm] 9b8eb5f - [AMDGPU][MC][GFX11] Correct op_sel handling for permlane*16
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 29 07:45:41 PST 2022
Author: Dmitry Preobrazhensky
Date: 2022-11-29T18:45:22+03:00
New Revision: 9b8eb5fa8ef0870e2b5d23ff0afacac6a7500e1f
URL: https://github.com/llvm/llvm-project/commit/9b8eb5fa8ef0870e2b5d23ff0afacac6a7500e1f
DIFF: https://github.com/llvm/llvm-project/commit/9b8eb5fa8ef0870e2b5d23ff0afacac6a7500e1f.diff
LOG: [AMDGPU][MC][GFX11] Correct op_sel handling for permlane*16
Differential Revision: https://reviews.llvm.org/D137969
Added:
llvm/test/MC/AMDGPU/gfx11_asm_vop3_err.s
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index ba5d62e81fc5f..3c6050cba7d56 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -4217,8 +4217,7 @@ bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst) const {
bool AMDGPUAsmParser::validateOpSel(const MCInst &Inst) {
const unsigned Opc = Inst.getOpcode();
- if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
- Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) {
+ if (isPermlane16(Opc)) {
int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);
unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index c1448ae7edf7f..5c4146b8ff59e 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -1210,8 +1210,7 @@ void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
const MCSubtargetInfo &STI,
raw_ostream &O) {
unsigned Opc = MI->getOpcode();
- if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
- Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) {
+ if (isPermlane16(Opc)) {
auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0);
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 6c519939507a2..8d622f124d9aa 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -455,6 +455,13 @@ bool isMAC(unsigned Opc) {
Opc == AMDGPU::V_DOT8C_I32_I4_e64_vi;
}
+bool isPermlane16(unsigned Opc) {
+ return Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
+ Opc == AMDGPU::V_PERMLANEX16_B32_gfx10 ||
+ Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx11 ||
+ Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx11;
+}
+
bool isTrue16Inst(unsigned Opc) {
const VOPTrue16Info *Info = getTrue16OpcodeHelper(Opc);
return Info ? Info->IsTrue16 : false;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 71db4261247bd..5e38a0c731e6b 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -512,6 +512,9 @@ bool isVOPD(unsigned Opc);
LLVM_READNONE
bool isMAC(unsigned Opc);
+LLVM_READNONE
+bool isPermlane16(unsigned Opc);
+
namespace VOPD {
enum Component : unsigned {
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_err.s
new file mode 100644
index 0000000000000..14c27d53df114
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_err.s
@@ -0,0 +1,8 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
+
+v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
+
+v_permlanex16_b32 v5, v1, s2, s3 op_sel:[0, 0, 1, 0]
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
index 67ecd5da929bf..afbda0e321aa1 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3.txt
@@ -4888,6 +4888,15 @@
# GFX11: v_permlanex16_b32 v5, v1, s2, s3 ; encoding: [0x05,0x00,0x5c,0xd6,0x01,0x05,0x0c,0x00]
0x05,0x00,0x5c,0xd6,0x01,0x05,0x0c,0x00
+# GFX11: v_permlane16_b32 v5, v1, s2, s3 op_sel:[1,1] ; encoding: [0x05,0x18,0x5b,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x18,0x5b,0xd6,0x01,0x05,0x0c,0x00
+
+# GFX11: v_permlane16_b32 v5, v1, s2, s3 op_sel:[1,0] ; encoding: [0x05,0x08,0x5b,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x08,0x5b,0xd6,0x01,0x05,0x0c,0x00
+
+# GFX11: v_permlane16_b32 v5, v1, s2, s3 op_sel:[0,1] ; encoding: [0x05,0x10,0x5b,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x10,0x5b,0xd6,0x01,0x05,0x0c,0x00
+
# GFX11: v_permlanex16_b32 v5, v1, s105, s105 ; encoding: [0x05,0x00,0x5c,0xd6,0x01,0xd3,0xa4,0x01]
0x05,0x00,0x5c,0xd6,0x01,0xd3,0xa4,0x01
@@ -4924,6 +4933,15 @@
# GFX11: v_permlanex16_b32 v255, v255, 0xaf123456, null ; encoding: [0xff,0x00,0x5c,0xd6,0xff,0xff,0xf1,0x01,0x56,0x34,0x12,0xaf]
0xff,0x00,0x5c,0xd6,0xff,0xff,0xf1,0x01,0x56,0x34,0x12,0xaf
+# GFX11: v_permlanex16_b32 v5, v1, s2, s3 op_sel:[1,1] ; encoding: [0x05,0x18,0x5c,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x18,0x5c,0xd6,0x01,0x05,0x0c,0x00
+
+# GFX11: v_permlanex16_b32 v5, v1, s2, s3 op_sel:[1,0] ; encoding: [0x05,0x08,0x5c,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x08,0x5c,0xd6,0x01,0x05,0x0c,0x00
+
+# GFX11: v_permlanex16_b32 v5, v1, s2, s3 op_sel:[0,1] ; encoding: [0x05,0x10,0x5c,0xd6,0x01,0x05,0x0c,0x00]
+0x05,0x10,0x5c,0xd6,0x01,0x05,0x0c,0x00
+
# GFX11: v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[14:15] ; encoding: [0x05,0x00,0x3a,0xd6,0x01,0x05,0xea,0x01]
0x05,0x00,0x3a,0xd6,0x01,0x05,0xea,0x01
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