[PATCH] D138883: [SelectionDAG][PowerPC] Memset reuse vector element for tail store

[Ting Wang via Phabricator via llvm-commits]

tingwang marked an inline comment as done.
tingwang added inline comments.


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Comment at: llvm/include/llvm/CodeGen/TargetLowering.h:672
+  /// construct constant value and store.
+  virtual bool isStoreElementFromVectorCheap(SelectionDAG &DAG, EVT VT,
+                                             uint64_t &Idx) const {
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nemanjai wrote:
> Do we need this? Can `canCombineStoreAndExtract()` suffice for this purpose?
Thank you! I did a try and updated patch. Saw two cases changed. I will look into the detail tomorrow.


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Comment at: llvm/test/CodeGen/PowerPC/memset-tail.ll:42
+; P8-LE-NEXT:    li 4, 16
+; P8-LE-NEXT:    xxswapd 0, 34
+; P8-LE-NEXT:    stxsdx 34, 3, 4
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nemanjai wrote:
> Why do we now get the redundant swap for the vector store that we didn't get before? Was it eliminated by the swap elimination before and now it is not because we have a use of the partial vector?
Debug-only `ppc-vsx-swaps` shows "Web 0 rejected for physreg, partial reg, or not swap[pable]". I will look into it and probably post another patch to fix the issue. Thank you!


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https://reviews.llvm.org/D138883