[llvm] 5f77ee4 - [NFC][AMDGPU] Pre-commit tests for D136432
Thomas Symalla via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 29 03:58:15 PST 2022
Author: Thomas Symalla
Date: 2022-11-29T12:57:59+01:00
New Revision: 5f77ee4011e621c76a7f43be958428dbfe35692b
URL: https://github.com/llvm/llvm-project/commit/5f77ee4011e621c76a7f43be958428dbfe35692b
DIFF: https://github.com/llvm/llvm-project/commit/5f77ee4011e621c76a7f43be958428dbfe35692b.diff
LOG: [NFC][AMDGPU] Pre-commit tests for D136432
Added:
Modified:
llvm/test/CodeGen/AMDGPU/bfi_nested.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/bfi_nested.ll b/llvm/test/CodeGen/AMDGPU/bfi_nested.ll
index 15ba181f1aab3..cc6e654a5ddae 100644
--- a/llvm/test/CodeGen/AMDGPU/bfi_nested.ll
+++ b/llvm/test/CodeGen/AMDGPU/bfi_nested.ll
@@ -1,23 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX10 %s
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
define float @v_bfi_single_nesting_level(float %x, float %y, float %z) {
-; GFX10-LABEL: v_bfi_single_nesting_level:
-; GFX10: ; %bb.0: ; %.entry
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
-; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX10-NEXT: v_mul_f32_e32 v2, 0x447fc000, v2
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 20, v0
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffc00, v1
-; GFX10-NEXT: v_and_b32_e32 v2, 0xc00003ff, v2
-; GFX10-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
-; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_bfi_single_nesting_level:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mul_f32_e32 v2, 0x447fc000, v2
+; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v1
+; GCN-NEXT: v_and_b32_e32 v2, 0xc00003ff, v2
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v0
+; GCN-NEXT: v_or_b32_e32 v1, v1, v2
+; GCN-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
+; GCN-NEXT: v_or_b32_e32 v0, v1, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
.entry:
%mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+03
%mul.base.i32 = fptoui float %mul.base to i32
@@ -36,21 +36,22 @@ define float @v_bfi_single_nesting_level(float %x, float %y, float %z) {
}
define float @v_bfi_single_nesting_level_swapped_operands(float %x, float %y, float %z) {
-; GFX10-LABEL: v_bfi_single_nesting_level_swapped_operands:
-; GFX10: ; %bb.0: ; %.entry
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_mul_f32_e32 v2, 0x447fc000, v2
-; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX10-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
-; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_and_b32_e32 v2, 0xc00003ff, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 20, v0
-; GFX10-NEXT: v_and_or_b32 v1, 0xffc00, v1, v2
-; GFX10-NEXT: v_and_or_b32 v0, 0x3ff00000, v0, v1
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_bfi_single_nesting_level_swapped_operands:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mul_f32_e32 v2, 0x447fc000, v2
+; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v1
+; GCN-NEXT: v_and_b32_e32 v2, 0xc00003ff, v2
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v0
+; GCN-NEXT: v_or_b32_e32 v1, v1, v2
+; GCN-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
+; GCN-NEXT: v_or_b32_e32 v0, v0, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
.entry:
%mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+03
%mul.base.i32 = fptoui float %mul.base to i32
@@ -69,22 +70,24 @@ define float @v_bfi_single_nesting_level_swapped_operands(float %x, float %y, fl
}
define float @v_bfi_single_nesting_level_unbalanced_subtree(float %x, float %y, float %z) {
-; GFX10-LABEL: v_bfi_single_nesting_level_unbalanced_subtree:
-; GFX10: ; %bb.0: ; %.entry
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_mul_f32_e32 v2, 0x447fc000, v2
-; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX10-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
-; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_and_b32_e32 v3, 0x3e0, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 20, v0
-; GFX10-NEXT: v_and_or_b32 v1, 0xffc00, v1, v3
-; GFX10-NEXT: v_and_or_b32 v1, 0xc000001f, v2, v1
-; GFX10-NEXT: v_and_or_b32 v0, 0x3ff00000, v0, v1
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_bfi_single_nesting_level_unbalanced_subtree:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mul_f32_e32 v2, 0x447fc000, v2
+; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v1
+; GCN-NEXT: v_and_b32_e32 v3, 0x3e0, v2
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v0
+; GCN-NEXT: v_or_b32_e32 v1, v1, v3
+; GCN-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
+; GCN-NEXT: v_and_b32_e32 v2, 0xc000001f, v2
+; GCN-NEXT: v_or_b32_e32 v1, v2, v1
+; GCN-NEXT: v_or_b32_e32 v0, v0, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
.entry:
%mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+03
%mul.base.i32 = fptoui float %mul.base to i32
@@ -105,18 +108,18 @@ define float @v_bfi_single_nesting_level_unbalanced_subtree(float %x, float %y,
}
define float @v_bfi_single_nesting_level_inner_use(float %x, float %y, float %z) {
-; GFX10-LABEL: v_bfi_single_nesting_level_inner_use:
-; GFX10: ; %bb.0: ; %.entry
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_mul_f32_e32 v0, 0x447fc000, v2
-; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX10-NEXT: v_and_b32_e32 v0, 0x400003ff, v0
-; GFX10-NEXT: v_and_or_b32 v0, 0xffc00, v1, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_bfi_single_nesting_level_inner_use:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v2
+; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v1
+; GCN-NEXT: v_and_b32_e32 v0, 0x400003ff, v0
+; GCN-NEXT: v_or_b32_e32 v0, v1, v0
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
.entry:
%mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+03
%mul.base.i32 = fptoui float %mul.base to i32
@@ -136,22 +139,22 @@ define float @v_bfi_single_nesting_level_inner_use(float %x, float %y, float %z)
}
define float @v_bfi_no_nesting(float %x, float %y, float %z) {
-; GFX10-LABEL: v_bfi_no_nesting:
-; GFX10: ; %bb.0: ; %.entry
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
-; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX10-NEXT: v_mul_f32_e32 v2, 0x447fc000, v2
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 20, v0
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffc00, v1
-; GFX10-NEXT: v_and_b32_e32 v2, 0xc0000400, v2
-; GFX10-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
-; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_bfi_no_nesting:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mul_f32_e32 v2, 0x447fc000, v2
+; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v1
+; GCN-NEXT: v_and_b32_e32 v2, 0xc0000400, v2
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v0
+; GCN-NEXT: v_or_b32_e32 v1, v1, v2
+; GCN-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
+; GCN-NEXT: v_or_b32_e32 v0, v1, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
.entry:
%mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+03
%mul.base.i32 = fptoui float %mul.base to i32
@@ -170,23 +173,24 @@ define float @v_bfi_no_nesting(float %x, float %y, float %z) {
}
define float @v_bfi_two_levels(float %x, float %y, float %z) {
-; GFX10-LABEL: v_bfi_two_levels:
-; GFX10: ; %bb.0: ; %.entry
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
-; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v3, 5, v1
-; GFX10-NEXT: v_and_b32_e32 v2, 0xc000001f, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 20, v0
-; GFX10-NEXT: v_and_or_b32 v2, 0x3e0, v3, v2
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffc00, v1
-; GFX10-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
-; GFX10-NEXT: v_or3_b32 v0, v2, v1, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_bfi_two_levels:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
+; GCN-NEXT: v_lshlrev_b32_e32 v3, 5, v1
+; GCN-NEXT: v_and_b32_e32 v2, 0xc000001f, v2
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_and_b32_e32 v3, 0x3e0, v3
+; GCN-NEXT: v_and_b32_e32 v1, 0xffc00, v1
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v0
+; GCN-NEXT: v_or_b32_e32 v2, v3, v2
+; GCN-NEXT: v_or_b32_e32 v1, v2, v1
+; GCN-NEXT: v_and_b32_e32 v0, 0x3ff00000, v0
+; GCN-NEXT: v_or_b32_e32 v0, v1, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
.entry:
%y.i32 = fptoui float %y to i32
%shl.insert.inner = shl i32 %y.i32, 5
@@ -207,19 +211,19 @@ define float @v_bfi_two_levels(float %x, float %y, float %z) {
}
define float @v_bfi_single_constant_as_partition(float %x, float %y, float %z) {
-; GFX10-LABEL: v_bfi_single_constant_as_partition:
-; GFX10: ; %bb.0: ; %.entry
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
-; GFX10-NEXT: v_mul_f32_e32 v2, 0x447fc000, v2
-; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX10-NEXT: v_cvt_u32_f32_e32 v2, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v1, 10, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 20, v0
-; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: v_bfi_single_constant_as_partition:
+; GCN: ; %bb.0: ; %.entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mul_f32_e32 v2, 0x447fc000, v2
+; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GCN-NEXT: v_mul_f32_e32 v0, 0x447fc000, v0
+; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
+; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GCN-NEXT: v_or_b32_e32 v1, v1, v2
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 20, v0
+; GCN-NEXT: v_or_b32_e32 v0, v1, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
.entry:
%mul.base = fmul reassoc nnan nsz arcp contract afn float %z, 1.023000e+03
%mul.base.i32 = fptoui float %mul.base to i32
@@ -234,3 +238,27 @@ define float @v_bfi_single_constant_as_partition(float %x, float %y, float %z) {
%result = bitcast i32 %or.outer to float
ret float %result
}
+
+define amdgpu_kernel void @v_bfi_dont_applied_for_scalar_ops(i32 addrspace(1)* %out, i16 %a, i32 %b) {; GFX10-LABEL: v_bfi_not_applied_in_scalar_case:
+; GCN-LABEL: v_bfi_dont_applied_for_scalar_ops:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_and_b32 s3, s3, 0xffff0000
+; GCN-NEXT: s_and_b32 s2, s2, 0xffff
+; GCN-NEXT: s_or_b32 s2, s2, s3
+; GCN-NEXT: s_mov_b32 s6, -1
+; GCN-NEXT: s_mov_b32 s4, s0
+; GCN-NEXT: s_mov_b32 s5, s1
+; GCN-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GCN-NEXT: s_endpgm
+ %shift = lshr i32 %b, 16
+ %tr = trunc i32 %shift to i16
+ %tmp = insertelement <2 x i16> undef, i16 %a, i32 0
+ %vec = insertelement <2 x i16> %tmp, i16 %tr, i32 1
+ %val = bitcast <2 x i16> %vec to i32
+ store i32 %val, i32 addrspace(1)* %out, align 4
+ ret void
+}
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