[PATCH] D138899: [PowerPC] add a peephole to eliminate unnecessary load

[ChenZheng via Phabricator via llvm-commits]

shchenz created this revision.
shchenz added reviewers: nemanjai, scui, PowerPC.
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For byval parameter, PPC currently will generate loads in the `lower_call()` to loads the parameter to the registers.

If there is store instruction which stores some value to the parameter in the same block, there will be load hit store issue.

This patch tries to solve this. 
Implementing this in PPC Peephole is because:
1: `lower_call` in PPC instruction selection pass has several versions for different platforms, so in peephole pass can avoid adding duplicated codes for each ABI implementation.
2: The load elimination should not be limited to a single block(even though for load-hit-store, it mostly happens in same block), for example, if we can analysis domination and alias well, it should be possible to eliminate a load in a different block with the store. So in DAG based PPC instruction selection pass, we can not extend current implementation to a function level optimization.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138899

Files:
  llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
  llvm/test/CodeGen/PowerPC/byval-lhs.ll
  llvm/test/CodeGen/PowerPC/convert-load-to-copy.mir
  llvm/test/CodeGen/PowerPC/vsx-p9.ll

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