[PATCH] D138844: [PowerPC] Materialize floats in the range [-16.0, 15.0].

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added a comment.

Do we already handle vector constants that are splats (i.e. `{ 1.0f, 1.0f, 1.0f, 1.0f }` or `{ 3.0, 3.0 }`)? If not, do we plan to?



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Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1348
 
+static SDNode *selectFloatImm(SelectionDAG *CurDAG, SDNode *N) {
+  ConstantFPSDNode *ConstFPNode = cast<ConstantFPSDNode>(N);
----------------
Why do we need custom selection code here? Can't we just implement this in the `.td` files similarly to how we implemented lowering for Power10 (see `nzFPImmAsi32` and `getFPAs32BitInt`). We just need a version of `nzFPImmAsi32` that checks for exact conversion and the result being in the expected range.


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Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1367-1368
+        CurDAG->getMachineNode(PPC::VSPLTISW, dl, MVT::v4i32, SDImm), 0);
+    if (N->getValueType(0) == MVT::f32)
+      return CurDAG->getMachineNode(PPC::XVCVSXWSP, dl, MVT::f32, SplatNode);
+    else if (N->getValueType(0) == MVT::f64)
----------------
This looks wrong. This will produce a pair of 32-bit single precision values in the FP portion of the VSX register. What you want is a 64-bit double precision value in each doubleword.

Don't forget that single precision values on PPC are in registers as double precison but rounded to single precision (i.e. a double precision representation of a single precision value).

I think you should use scalar instructions for scalar values (`xscvsxdsp`, `xscvsxddp`).


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https://reviews.llvm.org/D138844