[PATCH] D138682: [AArch64][SME]: Generate streaming-compatible code for bit counting/select

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:8477
+  if (VT.isScalableVector() ||
+    useSVEForFixedLengthVectorVT(VT, Subtarget->forceStreamingCompatibleSVE()))
     return LowerToPredicatedOp(Op, DAG, AArch64ISD::CTPOP_MERGE_PASSTHRU);
----------------
Odd indentation, have you used clang-format?


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:15678-15679
 
   // The combining code currently only works for NEON vectors. In particular,
   // it does not work for SVE when dealing with vectors wider than 128 bits.
+  if ((!VT.is64BitVector() && !VT.is128BitVector()) ||
----------------
This comment seems out of date?


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:15681
+  if ((!VT.is64BitVector() && !VT.is128BitVector()) ||
+    DAG.getSubtarget<AArch64Subtarget>().forceStreamingCompatibleSVE())
     return SDValue();
----------------
Odd indentation, have you used clang-format?

Also, is this the same as (and should this be):

  if (useSVEForFixedLengthVectorVT(VT, Subtarget->forceStreamingCompatibleSVE()))

?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138682/new/

https://reviews.llvm.org/D138682