[PATCH] D138786: [AMDGPU] Add llvm.amdgcn.raw.atomic.buffer.load intrinsic to support OpAtomicLoad lowering

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:977
+    if (ME.onlyReadsMemory() ||
+        IntrID == Intrinsic::amdgcn_raw_atomic_buffer_load) {
       unsigned MaxNumLanes = 4;
----------------
We really ought to fix these bypassing the usual atomic memory model stuff


================
Comment at: llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll:23
+bb1:
+  %0 = call i32 @llvm.amdgcn.raw.atomic.buffer.load.i32(<4 x i32> %addr, i32 4, i32 0, i32 1)
+  %1 = icmp eq i32 %0, %tmp0
----------------
Use named values in tests


================
Comment at: llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.atomic.buffer.load.ll:53
+declare i32 @llvm.amdgcn.raw.atomic.buffer.load.i32(<4 x i32>, i32, i32, i32 immarg)
+declare i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32>, i32, i32, i32 immarg)
+declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32 immarg)
----------------
Needs tests with more types. i64, <2 x i16>, <4 x i16>, and some pointers


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138786/new/

https://reviews.llvm.org/D138786