[PATCH] D138817: [AAch64] Optimize muls with operands having enough sign bits.

[Biplob Mishra via Phabricator via llvm-commits]

bipmis created this revision.
bipmis added reviewers: dmgreen, samtebbs.
bipmis added projects: All, LLVM.
bipmis requested review of this revision.

Muls with 64bit operands where each of the operand is having more than 32 sign bits, we can generate a single smull instruction on a 32bit operand.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138817

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
  llvm/test/CodeGen/AArch64/aarch64-smull.ll
  llvm/test/CodeGen/AArch64/arm64-mul.ll

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