[llvm] 143ca74 - AtomicExpand: Convert tests to opaque pointers
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 28 05:55:19 PST 2022
Author: Matt Arsenault
Date: 2022-11-28T08:43:16-05:00
New Revision: 143ca74ed3402c2be0e3cd733ea2cf50157ef103
URL: https://github.com/llvm/llvm-project/commit/143ca74ed3402c2be0e3cd733ea2cf50157ef103
DIFF: https://github.com/llvm/llvm-project/commit/143ca74ed3402c2be0e3cd733ea2cf50157ef103.diff
LOG: AtomicExpand: Convert tests to opaque pointers
Added:
Modified:
llvm/test/Transforms/AtomicExpand/AArch64/atomicrmw-fp.ll
llvm/test/Transforms/AtomicExpand/AArch64/expand-atomicrmw-xchg-fp.ll
llvm/test/Transforms/AtomicExpand/AArch64/pcsections.ll
llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll
llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd-flat-specialization.ll
llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmax.ll
llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmin.ll
llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fsub.ll
llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-nand.ll
llvm/test/Transforms/AtomicExpand/AMDGPU/unaligned-atomic.ll
llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v7.ll
llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v8.ll
llvm/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll
llvm/test/Transforms/AtomicExpand/ARM/cmpxchg-weak.ll
llvm/test/Transforms/AtomicExpand/Hexagon/atomicrmw-fp.ll
llvm/test/Transforms/AtomicExpand/Mips/atomicrmw-fp.ll
llvm/test/Transforms/AtomicExpand/PowerPC/atomicrmw-fp.ll
llvm/test/Transforms/AtomicExpand/PowerPC/cfence-double.ll
llvm/test/Transforms/AtomicExpand/PowerPC/cfence-float.ll
llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll
llvm/test/Transforms/AtomicExpand/PowerPC/issue55983.ll
llvm/test/Transforms/AtomicExpand/RISCV/atomicrmw-fp.ll
llvm/test/Transforms/AtomicExpand/SPARC/libcalls.ll
llvm/test/Transforms/AtomicExpand/SPARC/partword.ll
llvm/test/Transforms/AtomicExpand/X86/expand-atomic-libcall.ll
llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll
llvm/test/Transforms/AtomicExpand/X86/expand-atomic-rmw-fp.ll
llvm/test/Transforms/AtomicExpand/X86/expand-atomic-rmw-initial-load.ll
llvm/test/Transforms/AtomicExpand/X86/expand-atomic-xchg-fp.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/AtomicExpand/AArch64/atomicrmw-fp.ll b/llvm/test/Transforms/AtomicExpand/AArch64/atomicrmw-fp.ll
index d63f911a33f89..2fc848a3a810b 100644
--- a/llvm/test/Transforms/AtomicExpand/AArch64/atomicrmw-fp.ll
+++ b/llvm/test/Transforms/AtomicExpand/AArch64/atomicrmw-fp.ll
@@ -1,17 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -mtriple=aarch64-linux-gnu -atomic-expand %s | FileCheck %s
-define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
+define float @test_atomicrmw_fadd_f32(ptr %ptr, float %value) {
; CHECK-LABEL: @test_atomicrmw_fadd_f32(
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -19,21 +18,20 @@ define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
; CHECK: atomicrmw.end:
; CHECK-NEXT: ret float [[TMP6]]
;
- %res = atomicrmw fadd float* %ptr, float %value seq_cst
+ %res = atomicrmw fadd ptr %ptr, float %value seq_cst
ret float %res
}
-define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
+define float @test_atomicrmw_fsub_f32(ptr %ptr, float %value) {
; CHECK-LABEL: @test_atomicrmw_fsub_f32(
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -41,7 +39,7 @@ define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
; CHECK: atomicrmw.end:
; CHECK-NEXT: ret float [[TMP6]]
;
- %res = atomicrmw fsub float* %ptr, float %value seq_cst
+ %res = atomicrmw fsub ptr %ptr, float %value seq_cst
ret float %res
}
diff --git a/llvm/test/Transforms/AtomicExpand/AArch64/expand-atomicrmw-xchg-fp.ll b/llvm/test/Transforms/AtomicExpand/AArch64/expand-atomicrmw-xchg-fp.ll
index 0f7da33b1652f..47d626261bfc4 100644
--- a/llvm/test/Transforms/AtomicExpand/AArch64/expand-atomicrmw-xchg-fp.ll
+++ b/llvm/test/Transforms/AtomicExpand/AArch64/expand-atomicrmw-xchg-fp.ll
@@ -2,16 +2,15 @@
; RUN: opt -codegen-opt-level=1 -S -mtriple=aarch64-- -atomic-expand %s | FileCheck %s
; RUN: opt -codegen-opt-level=1 -S -mtriple=aarch64-- -mattr=+outline-atomics -atomic-expand %s | FileCheck %s --check-prefix=OUTLINE-ATOMICS
-define void @atomic_swap_f16(half* %ptr, half %val) nounwind {
+define void @atomic_swap_f16(ptr %ptr, half %val) nounwind {
; CHECK-LABEL: @atomic_swap_f16(
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast half* [[PTR:%.*]] to i16*
; CHECK-NEXT: [[TMP2:%.*]] = bitcast half [[VAL:%.*]] to i16
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
-; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i16(i16* elementtype(i16) [[TMP1]])
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i16) [[PTR:%.*]])
; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i16
; CHECK-NEXT: [[TMP5:%.*]] = zext i16 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.aarch64.stxr.p0i16(i64 [[TMP5]], i16* elementtype(i16) [[TMP1]])
+; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.aarch64.stxr.p0(i64 [[TMP5]], ptr elementtype(i16) [[PTR]])
; CHECK-NEXT: [[TRYAGAIN:%.*]] = icmp ne i32 [[TMP6]], 0
; CHECK-NEXT: br i1 [[TRYAGAIN]], label [[ATOMICRMW_START]], label [[ATOMICRMW_END:%.*]]
; CHECK: atomicrmw.end:
@@ -19,26 +18,24 @@ define void @atomic_swap_f16(half* %ptr, half %val) nounwind {
; CHECK-NEXT: ret void
;
; OUTLINE-ATOMICS-LABEL: @atomic_swap_f16(
-; OUTLINE-ATOMICS-NEXT: [[TMP1:%.*]] = bitcast half* [[PTR:%.*]] to i16*
; OUTLINE-ATOMICS-NEXT: [[TMP2:%.*]] = bitcast half [[VAL:%.*]] to i16
-; OUTLINE-ATOMICS-NEXT: [[TMP3:%.*]] = atomicrmw xchg i16* [[TMP1]], i16 [[TMP2]] acquire, align 2
+; OUTLINE-ATOMICS-NEXT: [[TMP3:%.*]] = atomicrmw xchg ptr [[PTR:%.*]], i16 [[TMP2]] acquire, align 2
; OUTLINE-ATOMICS-NEXT: [[TMP4:%.*]] = bitcast i16 [[TMP3]] to half
; OUTLINE-ATOMICS-NEXT: ret void
;
- %t1 = atomicrmw xchg half* %ptr, half %val acquire
+ %t1 = atomicrmw xchg ptr %ptr, half %val acquire
ret void
}
-define void @atomic_swap_f32(float* %ptr, float %val) nounwind {
+define void @atomic_swap_f32(ptr %ptr, float %val) nounwind {
; CHECK-LABEL: @atomic_swap_f32(
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[PTR:%.*]] to i32*
; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[VAL:%.*]] to i32
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
-; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i32(i32* elementtype(i32) [[TMP1]])
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i32) [[PTR:%.*]])
; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP2]] to i64
-; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.aarch64.stxr.p0i32(i64 [[TMP5]], i32* elementtype(i32) [[TMP1]])
+; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.aarch64.stxr.p0(i64 [[TMP5]], ptr elementtype(i32) [[PTR]])
; CHECK-NEXT: [[TRYAGAIN:%.*]] = icmp ne i32 [[TMP6]], 0
; CHECK-NEXT: br i1 [[TRYAGAIN]], label [[ATOMICRMW_START]], label [[ATOMICRMW_END:%.*]]
; CHECK: atomicrmw.end:
@@ -46,24 +43,22 @@ define void @atomic_swap_f32(float* %ptr, float %val) nounwind {
; CHECK-NEXT: ret void
;
; OUTLINE-ATOMICS-LABEL: @atomic_swap_f32(
-; OUTLINE-ATOMICS-NEXT: [[TMP1:%.*]] = bitcast float* [[PTR:%.*]] to i32*
; OUTLINE-ATOMICS-NEXT: [[TMP2:%.*]] = bitcast float [[VAL:%.*]] to i32
-; OUTLINE-ATOMICS-NEXT: [[TMP3:%.*]] = atomicrmw xchg i32* [[TMP1]], i32 [[TMP2]] acquire, align 4
+; OUTLINE-ATOMICS-NEXT: [[TMP3:%.*]] = atomicrmw xchg ptr [[PTR:%.*]], i32 [[TMP2]] acquire, align 4
; OUTLINE-ATOMICS-NEXT: [[TMP4:%.*]] = bitcast i32 [[TMP3]] to float
; OUTLINE-ATOMICS-NEXT: ret void
;
- %t1 = atomicrmw xchg float* %ptr, float %val acquire
+ %t1 = atomicrmw xchg ptr %ptr, float %val acquire
ret void
}
-define void @atomic_swap_f64(double* %ptr, double %val) nounwind {
+define void @atomic_swap_f64(ptr %ptr, double %val) nounwind {
; CHECK-LABEL: @atomic_swap_f64(
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast double* [[PTR:%.*]] to i64*
; CHECK-NEXT: [[TMP2:%.*]] = bitcast double [[VAL:%.*]] to i64
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
-; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i64(i64* elementtype(i64) [[TMP1]])
-; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.aarch64.stxr.p0i64(i64 [[TMP2]], i64* elementtype(i64) [[TMP1]])
+; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i64) [[PTR:%.*]])
+; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.aarch64.stxr.p0(i64 [[TMP2]], ptr elementtype(i64) [[PTR]])
; CHECK-NEXT: [[TRYAGAIN:%.*]] = icmp ne i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TRYAGAIN]], label [[ATOMICRMW_START]], label [[ATOMICRMW_END:%.*]]
; CHECK: atomicrmw.end:
@@ -71,12 +66,11 @@ define void @atomic_swap_f64(double* %ptr, double %val) nounwind {
; CHECK-NEXT: ret void
;
; OUTLINE-ATOMICS-LABEL: @atomic_swap_f64(
-; OUTLINE-ATOMICS-NEXT: [[TMP1:%.*]] = bitcast double* [[PTR:%.*]] to i64*
; OUTLINE-ATOMICS-NEXT: [[TMP2:%.*]] = bitcast double [[VAL:%.*]] to i64
-; OUTLINE-ATOMICS-NEXT: [[TMP3:%.*]] = atomicrmw xchg i64* [[TMP1]], i64 [[TMP2]] acquire, align 8
+; OUTLINE-ATOMICS-NEXT: [[TMP3:%.*]] = atomicrmw xchg ptr [[PTR:%.*]], i64 [[TMP2]] acquire, align 8
; OUTLINE-ATOMICS-NEXT: [[TMP4:%.*]] = bitcast i64 [[TMP3]] to double
; OUTLINE-ATOMICS-NEXT: ret void
;
- %t1 = atomicrmw xchg double* %ptr, double %val acquire
+ %t1 = atomicrmw xchg ptr %ptr, double %val acquire
ret void
}
diff --git a/llvm/test/Transforms/AtomicExpand/AArch64/pcsections.ll b/llvm/test/Transforms/AtomicExpand/AArch64/pcsections.ll
index 639ae8f31defd..2e9efe911e6d6 100644
--- a/llvm/test/Transforms/AtomicExpand/AArch64/pcsections.ll
+++ b/llvm/test/Transforms/AtomicExpand/AArch64/pcsections.ll
@@ -1,102 +1,102 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -mtriple=aarch64-linux-gnu -atomic-expand %s | FileCheck %s
-define i8 @atomic8_load_unordered(i8* %a) nounwind uwtable {
+define i8 @atomic8_load_unordered(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_load_unordered(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load atomic i8, i8* [[A:%.*]] unordered, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load atomic i8, ptr [[A:%.*]] unordered, align 1, !pcsections !0
; CHECK-NEXT: ret i8 [[TMP0]]
;
entry:
- %0 = load atomic i8, i8* %a unordered, align 1, !pcsections !0
+ %0 = load atomic i8, ptr %a unordered, align 1, !pcsections !0
ret i8 %0
}
-define i8 @atomic8_load_monotonic(i8* %a) nounwind uwtable {
+define i8 @atomic8_load_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_load_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load atomic i8, i8* [[A:%.*]] monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load atomic i8, ptr [[A:%.*]] monotonic, align 1, !pcsections !0
; CHECK-NEXT: ret i8 [[TMP0]]
;
entry:
- %0 = load atomic i8, i8* %a monotonic, align 1, !pcsections !0
+ %0 = load atomic i8, ptr %a monotonic, align 1, !pcsections !0
ret i8 %0
}
-define i8 @atomic8_load_acquire(i8* %a) nounwind uwtable {
+define i8 @atomic8_load_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_load_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load atomic i8, i8* [[A:%.*]] acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load atomic i8, ptr [[A:%.*]] acquire, align 1, !pcsections !0
; CHECK-NEXT: ret i8 [[TMP0]]
;
entry:
- %0 = load atomic i8, i8* %a acquire, align 1, !pcsections !0
+ %0 = load atomic i8, ptr %a acquire, align 1, !pcsections !0
ret i8 %0
}
-define i8 @atomic8_load_seq_cst(i8* %a) nounwind uwtable {
+define i8 @atomic8_load_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_load_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load atomic i8, i8* [[A:%.*]] seq_cst, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load atomic i8, ptr [[A:%.*]] seq_cst, align 1, !pcsections !0
; CHECK-NEXT: ret i8 [[TMP0]]
;
entry:
- %0 = load atomic i8, i8* %a seq_cst, align 1, !pcsections !0
+ %0 = load atomic i8, ptr %a seq_cst, align 1, !pcsections !0
ret i8 %0
}
-define void @atomic8_store_unordered(i8* %a) nounwind uwtable {
+define void @atomic8_store_unordered(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_store_unordered(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store atomic i8 0, i8* [[A:%.*]] unordered, align 1, !pcsections !0
+; CHECK-NEXT: store atomic i8 0, ptr [[A:%.*]] unordered, align 1, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- store atomic i8 0, i8* %a unordered, align 1, !pcsections !0
+ store atomic i8 0, ptr %a unordered, align 1, !pcsections !0
ret void
}
-define void @atomic8_store_monotonic(i8* %a) nounwind uwtable {
+define void @atomic8_store_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_store_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store atomic i8 0, i8* [[A:%.*]] monotonic, align 1, !pcsections !0
+; CHECK-NEXT: store atomic i8 0, ptr [[A:%.*]] monotonic, align 1, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- store atomic i8 0, i8* %a monotonic, align 1, !pcsections !0
+ store atomic i8 0, ptr %a monotonic, align 1, !pcsections !0
ret void
}
-define void @atomic8_store_release(i8* %a) nounwind uwtable {
+define void @atomic8_store_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_store_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store atomic i8 0, i8* [[A:%.*]] release, align 1, !pcsections !0
+; CHECK-NEXT: store atomic i8 0, ptr [[A:%.*]] release, align 1, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- store atomic i8 0, i8* %a release, align 1, !pcsections !0
+ store atomic i8 0, ptr %a release, align 1, !pcsections !0
ret void
}
-define void @atomic8_store_seq_cst(i8* %a) nounwind uwtable {
+define void @atomic8_store_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_store_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store atomic i8 0, i8* [[A:%.*]] seq_cst, align 1, !pcsections !0
+; CHECK-NEXT: store atomic i8 0, ptr [[A:%.*]] seq_cst, align 1, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- store atomic i8 0, i8* %a seq_cst, align 1, !pcsections !0
+ store atomic i8 0, ptr %a seq_cst, align 1, !pcsections !0
ret void
}
-define void @atomic8_xchg_monotonic(i8* %a) nounwind uwtable {
+define void @atomic8_xchg_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_xchg_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 monotonic monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 monotonic monotonic, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -104,18 +104,18 @@ define void @atomic8_xchg_monotonic(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i8* %a, i8 0 monotonic, !pcsections !0
+ atomicrmw xchg ptr %a, i8 0 monotonic, !pcsections !0
ret void
}
-define void @atomic8_add_monotonic(i8* %a) nounwind uwtable {
+define void @atomic8_add_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_add_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] monotonic monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] monotonic monotonic, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -123,18 +123,18 @@ define void @atomic8_add_monotonic(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i8* %a, i8 0 monotonic, !pcsections !0
+ atomicrmw add ptr %a, i8 0 monotonic, !pcsections !0
ret void
}
-define void @atomic8_sub_monotonic(i8* %a) nounwind uwtable {
+define void @atomic8_sub_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_sub_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] monotonic monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] monotonic monotonic, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -142,18 +142,18 @@ define void @atomic8_sub_monotonic(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i8* %a, i8 0 monotonic, !pcsections !0
+ atomicrmw sub ptr %a, i8 0 monotonic, !pcsections !0
ret void
}
-define void @atomic8_and_monotonic(i8* %a) nounwind uwtable {
+define void @atomic8_and_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_and_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 monotonic monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 monotonic monotonic, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -161,18 +161,18 @@ define void @atomic8_and_monotonic(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i8* %a, i8 0 monotonic, !pcsections !0
+ atomicrmw and ptr %a, i8 0 monotonic, !pcsections !0
ret void
}
-define void @atomic8_or_monotonic(i8* %a) nounwind uwtable {
+define void @atomic8_or_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_or_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] monotonic monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] monotonic monotonic, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -180,18 +180,18 @@ define void @atomic8_or_monotonic(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i8* %a, i8 0 monotonic, !pcsections !0
+ atomicrmw or ptr %a, i8 0 monotonic, !pcsections !0
ret void
}
-define void @atomic8_xor_monotonic(i8* %a) nounwind uwtable {
+define void @atomic8_xor_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_xor_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] monotonic monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] monotonic monotonic, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -199,18 +199,18 @@ define void @atomic8_xor_monotonic(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i8* %a, i8 0 monotonic, !pcsections !0
+ atomicrmw xor ptr %a, i8 0 monotonic, !pcsections !0
ret void
}
-define void @atomic8_nand_monotonic(i8* %a) nounwind uwtable {
+define void @atomic8_nand_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_nand_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 -1 monotonic monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 -1 monotonic monotonic, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -218,18 +218,18 @@ define void @atomic8_nand_monotonic(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i8* %a, i8 0 monotonic, !pcsections !0
+ atomicrmw nand ptr %a, i8 0 monotonic, !pcsections !0
ret void
}
-define void @atomic8_xchg_acquire(i8* %a) nounwind uwtable {
+define void @atomic8_xchg_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_xchg_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 acquire acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 acquire acquire, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -237,18 +237,18 @@ define void @atomic8_xchg_acquire(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i8* %a, i8 0 acquire, !pcsections !0
+ atomicrmw xchg ptr %a, i8 0 acquire, !pcsections !0
ret void
}
-define void @atomic8_add_acquire(i8* %a) nounwind uwtable {
+define void @atomic8_add_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_add_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] acquire acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] acquire acquire, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -256,18 +256,18 @@ define void @atomic8_add_acquire(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i8* %a, i8 0 acquire, !pcsections !0
+ atomicrmw add ptr %a, i8 0 acquire, !pcsections !0
ret void
}
-define void @atomic8_sub_acquire(i8* %a) nounwind uwtable {
+define void @atomic8_sub_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_sub_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] acquire acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] acquire acquire, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -275,18 +275,18 @@ define void @atomic8_sub_acquire(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i8* %a, i8 0 acquire, !pcsections !0
+ atomicrmw sub ptr %a, i8 0 acquire, !pcsections !0
ret void
}
-define void @atomic8_and_acquire(i8* %a) nounwind uwtable {
+define void @atomic8_and_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_and_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 acquire acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 acquire acquire, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -294,18 +294,18 @@ define void @atomic8_and_acquire(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i8* %a, i8 0 acquire, !pcsections !0
+ atomicrmw and ptr %a, i8 0 acquire, !pcsections !0
ret void
}
-define void @atomic8_or_acquire(i8* %a) nounwind uwtable {
+define void @atomic8_or_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_or_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] acquire acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] acquire acquire, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -313,18 +313,18 @@ define void @atomic8_or_acquire(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i8* %a, i8 0 acquire, !pcsections !0
+ atomicrmw or ptr %a, i8 0 acquire, !pcsections !0
ret void
}
-define void @atomic8_xor_acquire(i8* %a) nounwind uwtable {
+define void @atomic8_xor_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_xor_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] acquire acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] acquire acquire, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -332,18 +332,18 @@ define void @atomic8_xor_acquire(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i8* %a, i8 0 acquire, !pcsections !0
+ atomicrmw xor ptr %a, i8 0 acquire, !pcsections !0
ret void
}
-define void @atomic8_nand_acquire(i8* %a) nounwind uwtable {
+define void @atomic8_nand_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_nand_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 -1 acquire acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 -1 acquire acquire, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -351,18 +351,18 @@ define void @atomic8_nand_acquire(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i8* %a, i8 0 acquire, !pcsections !0
+ atomicrmw nand ptr %a, i8 0 acquire, !pcsections !0
ret void
}
-define void @atomic8_xchg_release(i8* %a) nounwind uwtable {
+define void @atomic8_xchg_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_xchg_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 release monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 release monotonic, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -370,18 +370,18 @@ define void @atomic8_xchg_release(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i8* %a, i8 0 release, !pcsections !0
+ atomicrmw xchg ptr %a, i8 0 release, !pcsections !0
ret void
}
-define void @atomic8_add_release(i8* %a) nounwind uwtable {
+define void @atomic8_add_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_add_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] release monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] release monotonic, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -389,18 +389,18 @@ define void @atomic8_add_release(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i8* %a, i8 0 release, !pcsections !0
+ atomicrmw add ptr %a, i8 0 release, !pcsections !0
ret void
}
-define void @atomic8_sub_release(i8* %a) nounwind uwtable {
+define void @atomic8_sub_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_sub_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] release monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] release monotonic, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -408,18 +408,18 @@ define void @atomic8_sub_release(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i8* %a, i8 0 release, !pcsections !0
+ atomicrmw sub ptr %a, i8 0 release, !pcsections !0
ret void
}
-define void @atomic8_and_release(i8* %a) nounwind uwtable {
+define void @atomic8_and_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_and_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 release monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 release monotonic, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -427,18 +427,18 @@ define void @atomic8_and_release(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i8* %a, i8 0 release, !pcsections !0
+ atomicrmw and ptr %a, i8 0 release, !pcsections !0
ret void
}
-define void @atomic8_or_release(i8* %a) nounwind uwtable {
+define void @atomic8_or_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_or_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] release monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] release monotonic, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -446,18 +446,18 @@ define void @atomic8_or_release(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i8* %a, i8 0 release, !pcsections !0
+ atomicrmw or ptr %a, i8 0 release, !pcsections !0
ret void
}
-define void @atomic8_xor_release(i8* %a) nounwind uwtable {
+define void @atomic8_xor_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_xor_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] release monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] release monotonic, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -465,18 +465,18 @@ define void @atomic8_xor_release(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i8* %a, i8 0 release, !pcsections !0
+ atomicrmw xor ptr %a, i8 0 release, !pcsections !0
ret void
}
-define void @atomic8_nand_release(i8* %a) nounwind uwtable {
+define void @atomic8_nand_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_nand_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 -1 release monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 -1 release monotonic, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -484,18 +484,18 @@ define void @atomic8_nand_release(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i8* %a, i8 0 release, !pcsections !0
+ atomicrmw nand ptr %a, i8 0 release, !pcsections !0
ret void
}
-define void @atomic8_xchg_acq_rel(i8* %a) nounwind uwtable {
+define void @atomic8_xchg_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_xchg_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 acq_rel acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 acq_rel acquire, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -503,18 +503,18 @@ define void @atomic8_xchg_acq_rel(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i8* %a, i8 0 acq_rel, !pcsections !0
+ atomicrmw xchg ptr %a, i8 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic8_add_acq_rel(i8* %a) nounwind uwtable {
+define void @atomic8_add_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_add_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] acq_rel acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] acq_rel acquire, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -522,18 +522,18 @@ define void @atomic8_add_acq_rel(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i8* %a, i8 0 acq_rel, !pcsections !0
+ atomicrmw add ptr %a, i8 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic8_sub_acq_rel(i8* %a) nounwind uwtable {
+define void @atomic8_sub_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_sub_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] acq_rel acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] acq_rel acquire, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -541,18 +541,18 @@ define void @atomic8_sub_acq_rel(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i8* %a, i8 0 acq_rel, !pcsections !0
+ atomicrmw sub ptr %a, i8 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic8_and_acq_rel(i8* %a) nounwind uwtable {
+define void @atomic8_and_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_and_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 acq_rel acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 acq_rel acquire, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -560,18 +560,18 @@ define void @atomic8_and_acq_rel(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i8* %a, i8 0 acq_rel, !pcsections !0
+ atomicrmw and ptr %a, i8 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic8_or_acq_rel(i8* %a) nounwind uwtable {
+define void @atomic8_or_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_or_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] acq_rel acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] acq_rel acquire, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -579,18 +579,18 @@ define void @atomic8_or_acq_rel(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i8* %a, i8 0 acq_rel, !pcsections !0
+ atomicrmw or ptr %a, i8 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic8_xor_acq_rel(i8* %a) nounwind uwtable {
+define void @atomic8_xor_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_xor_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] acq_rel acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] acq_rel acquire, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -598,18 +598,18 @@ define void @atomic8_xor_acq_rel(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i8* %a, i8 0 acq_rel, !pcsections !0
+ atomicrmw xor ptr %a, i8 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic8_nand_acq_rel(i8* %a) nounwind uwtable {
+define void @atomic8_nand_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_nand_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 -1 acq_rel acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 -1 acq_rel acquire, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -617,18 +617,18 @@ define void @atomic8_nand_acq_rel(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i8* %a, i8 0 acq_rel, !pcsections !0
+ atomicrmw nand ptr %a, i8 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic8_xchg_seq_cst(i8* %a) nounwind uwtable {
+define void @atomic8_xchg_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_xchg_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 seq_cst seq_cst, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 seq_cst seq_cst, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -636,18 +636,18 @@ define void @atomic8_xchg_seq_cst(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i8* %a, i8 0 seq_cst, !pcsections !0
+ atomicrmw xchg ptr %a, i8 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic8_add_seq_cst(i8* %a) nounwind uwtable {
+define void @atomic8_add_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_add_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] seq_cst seq_cst, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] seq_cst seq_cst, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -655,18 +655,18 @@ define void @atomic8_add_seq_cst(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i8* %a, i8 0 seq_cst, !pcsections !0
+ atomicrmw add ptr %a, i8 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic8_sub_seq_cst(i8* %a) nounwind uwtable {
+define void @atomic8_sub_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_sub_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] seq_cst seq_cst, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] seq_cst seq_cst, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -674,18 +674,18 @@ define void @atomic8_sub_seq_cst(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i8* %a, i8 0 seq_cst, !pcsections !0
+ atomicrmw sub ptr %a, i8 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic8_and_seq_cst(i8* %a) nounwind uwtable {
+define void @atomic8_and_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_and_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 seq_cst seq_cst, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 seq_cst seq_cst, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -693,18 +693,18 @@ define void @atomic8_and_seq_cst(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i8* %a, i8 0 seq_cst, !pcsections !0
+ atomicrmw and ptr %a, i8 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic8_or_seq_cst(i8* %a) nounwind uwtable {
+define void @atomic8_or_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_or_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] seq_cst seq_cst, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] seq_cst seq_cst, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -712,18 +712,18 @@ define void @atomic8_or_seq_cst(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i8* %a, i8 0 seq_cst, !pcsections !0
+ atomicrmw or ptr %a, i8 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic8_xor_seq_cst(i8* %a) nounwind uwtable {
+define void @atomic8_xor_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_xor_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] seq_cst seq_cst, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] seq_cst seq_cst, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -731,18 +731,18 @@ define void @atomic8_xor_seq_cst(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i8* %a, i8 0 seq_cst, !pcsections !0
+ atomicrmw xor ptr %a, i8 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic8_nand_seq_cst(i8* %a) nounwind uwtable {
+define void @atomic8_nand_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_nand_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 -1 seq_cst seq_cst, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 -1 seq_cst seq_cst, align 1, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -750,181 +750,181 @@ define void @atomic8_nand_seq_cst(i8* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i8* %a, i8 0 seq_cst, !pcsections !0
+ atomicrmw nand ptr %a, i8 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic8_cas_monotonic(i8* %a) nounwind uwtable {
+define void @atomic8_cas_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_cas_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i8* [[A:%.*]], i8 0, i8 1 monotonic monotonic, align 1, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 monotonic acquire, align 1, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 monotonic seq_cst, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i8 0, i8 1 monotonic monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 monotonic acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 monotonic seq_cst, align 1, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i8* %a, i8 0, i8 1 monotonic monotonic, !pcsections !0
- cmpxchg i8* %a, i8 0, i8 1 monotonic acquire, !pcsections !0
- cmpxchg i8* %a, i8 0, i8 1 monotonic seq_cst, !pcsections !0
+ cmpxchg ptr %a, i8 0, i8 1 monotonic monotonic, !pcsections !0
+ cmpxchg ptr %a, i8 0, i8 1 monotonic acquire, !pcsections !0
+ cmpxchg ptr %a, i8 0, i8 1 monotonic seq_cst, !pcsections !0
ret void
}
-define void @atomic8_cas_acquire(i8* %a) nounwind uwtable {
+define void @atomic8_cas_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_cas_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i8* [[A:%.*]], i8 0, i8 1 acquire monotonic, align 1, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 acquire acquire, align 1, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 acquire seq_cst, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i8 0, i8 1 acquire monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 acquire acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 acquire seq_cst, align 1, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i8* %a, i8 0, i8 1 acquire monotonic, !pcsections !0
- cmpxchg i8* %a, i8 0, i8 1 acquire acquire, !pcsections !0
- cmpxchg i8* %a, i8 0, i8 1 acquire seq_cst, !pcsections !0
+ cmpxchg ptr %a, i8 0, i8 1 acquire monotonic, !pcsections !0
+ cmpxchg ptr %a, i8 0, i8 1 acquire acquire, !pcsections !0
+ cmpxchg ptr %a, i8 0, i8 1 acquire seq_cst, !pcsections !0
ret void
}
-define void @atomic8_cas_release(i8* %a) nounwind uwtable {
+define void @atomic8_cas_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_cas_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i8* [[A:%.*]], i8 0, i8 1 release monotonic, align 1, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 release acquire, align 1, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 release seq_cst, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i8 0, i8 1 release monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 release acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 release seq_cst, align 1, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i8* %a, i8 0, i8 1 release monotonic, !pcsections !0
- cmpxchg i8* %a, i8 0, i8 1 release acquire, !pcsections !0
- cmpxchg i8* %a, i8 0, i8 1 release seq_cst, !pcsections !0
+ cmpxchg ptr %a, i8 0, i8 1 release monotonic, !pcsections !0
+ cmpxchg ptr %a, i8 0, i8 1 release acquire, !pcsections !0
+ cmpxchg ptr %a, i8 0, i8 1 release seq_cst, !pcsections !0
ret void
}
-define void @atomic8_cas_acq_rel(i8* %a) nounwind uwtable {
+define void @atomic8_cas_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_cas_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i8* [[A:%.*]], i8 0, i8 1 acq_rel monotonic, align 1, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 acq_rel acquire, align 1, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 acq_rel seq_cst, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i8 0, i8 1 acq_rel monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 acq_rel acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 acq_rel seq_cst, align 1, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i8* %a, i8 0, i8 1 acq_rel monotonic, !pcsections !0
- cmpxchg i8* %a, i8 0, i8 1 acq_rel acquire, !pcsections !0
- cmpxchg i8* %a, i8 0, i8 1 acq_rel seq_cst, !pcsections !0
+ cmpxchg ptr %a, i8 0, i8 1 acq_rel monotonic, !pcsections !0
+ cmpxchg ptr %a, i8 0, i8 1 acq_rel acquire, !pcsections !0
+ cmpxchg ptr %a, i8 0, i8 1 acq_rel seq_cst, !pcsections !0
ret void
}
-define void @atomic8_cas_seq_cst(i8* %a) nounwind uwtable {
+define void @atomic8_cas_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic8_cas_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i8* [[A:%.*]], i8 0, i8 1 seq_cst monotonic, align 1, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 seq_cst acquire, align 1, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 seq_cst seq_cst, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i8 0, i8 1 seq_cst monotonic, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 seq_cst acquire, align 1, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 seq_cst seq_cst, align 1, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i8* %a, i8 0, i8 1 seq_cst monotonic, !pcsections !0
- cmpxchg i8* %a, i8 0, i8 1 seq_cst acquire, !pcsections !0
- cmpxchg i8* %a, i8 0, i8 1 seq_cst seq_cst, !pcsections !0
+ cmpxchg ptr %a, i8 0, i8 1 seq_cst monotonic, !pcsections !0
+ cmpxchg ptr %a, i8 0, i8 1 seq_cst acquire, !pcsections !0
+ cmpxchg ptr %a, i8 0, i8 1 seq_cst seq_cst, !pcsections !0
ret void
}
-define i16 @atomic16_load_unordered(i16* %a) nounwind uwtable {
+define i16 @atomic16_load_unordered(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_load_unordered(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, i16* [[A:%.*]] unordered, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, ptr [[A:%.*]] unordered, align 2, !pcsections !0
; CHECK-NEXT: ret i16 [[TMP0]]
;
entry:
- %0 = load atomic i16, i16* %a unordered, align 2, !pcsections !0
+ %0 = load atomic i16, ptr %a unordered, align 2, !pcsections !0
ret i16 %0
}
-define i16 @atomic16_load_monotonic(i16* %a) nounwind uwtable {
+define i16 @atomic16_load_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_load_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, i16* [[A:%.*]] monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, ptr [[A:%.*]] monotonic, align 2, !pcsections !0
; CHECK-NEXT: ret i16 [[TMP0]]
;
entry:
- %0 = load atomic i16, i16* %a monotonic, align 2, !pcsections !0
+ %0 = load atomic i16, ptr %a monotonic, align 2, !pcsections !0
ret i16 %0
}
-define i16 @atomic16_load_acquire(i16* %a) nounwind uwtable {
+define i16 @atomic16_load_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_load_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, i16* [[A:%.*]] acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, ptr [[A:%.*]] acquire, align 2, !pcsections !0
; CHECK-NEXT: ret i16 [[TMP0]]
;
entry:
- %0 = load atomic i16, i16* %a acquire, align 2, !pcsections !0
+ %0 = load atomic i16, ptr %a acquire, align 2, !pcsections !0
ret i16 %0
}
-define i16 @atomic16_load_seq_cst(i16* %a) nounwind uwtable {
+define i16 @atomic16_load_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_load_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, i16* [[A:%.*]] seq_cst, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, ptr [[A:%.*]] seq_cst, align 2, !pcsections !0
; CHECK-NEXT: ret i16 [[TMP0]]
;
entry:
- %0 = load atomic i16, i16* %a seq_cst, align 2, !pcsections !0
+ %0 = load atomic i16, ptr %a seq_cst, align 2, !pcsections !0
ret i16 %0
}
-define void @atomic16_store_unordered(i16* %a) nounwind uwtable {
+define void @atomic16_store_unordered(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_store_unordered(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store atomic i16 0, i16* [[A:%.*]] unordered, align 2, !pcsections !0
+; CHECK-NEXT: store atomic i16 0, ptr [[A:%.*]] unordered, align 2, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- store atomic i16 0, i16* %a unordered, align 2, !pcsections !0
+ store atomic i16 0, ptr %a unordered, align 2, !pcsections !0
ret void
}
-define void @atomic16_store_monotonic(i16* %a) nounwind uwtable {
+define void @atomic16_store_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_store_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store atomic i16 0, i16* [[A:%.*]] monotonic, align 2, !pcsections !0
+; CHECK-NEXT: store atomic i16 0, ptr [[A:%.*]] monotonic, align 2, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- store atomic i16 0, i16* %a monotonic, align 2, !pcsections !0
+ store atomic i16 0, ptr %a monotonic, align 2, !pcsections !0
ret void
}
-define void @atomic16_store_release(i16* %a) nounwind uwtable {
+define void @atomic16_store_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_store_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store atomic i16 0, i16* [[A:%.*]] release, align 2, !pcsections !0
+; CHECK-NEXT: store atomic i16 0, ptr [[A:%.*]] release, align 2, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- store atomic i16 0, i16* %a release, align 2, !pcsections !0
+ store atomic i16 0, ptr %a release, align 2, !pcsections !0
ret void
}
-define void @atomic16_store_seq_cst(i16* %a) nounwind uwtable {
+define void @atomic16_store_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_store_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store atomic i16 0, i16* [[A:%.*]] seq_cst, align 2, !pcsections !0
+; CHECK-NEXT: store atomic i16 0, ptr [[A:%.*]] seq_cst, align 2, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- store atomic i16 0, i16* %a seq_cst, align 2, !pcsections !0
+ store atomic i16 0, ptr %a seq_cst, align 2, !pcsections !0
ret void
}
-define void @atomic16_xchg_monotonic(i16* %a) nounwind uwtable {
+define void @atomic16_xchg_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_xchg_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 monotonic monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 monotonic monotonic, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -932,18 +932,18 @@ define void @atomic16_xchg_monotonic(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i16* %a, i16 0 monotonic, !pcsections !0
+ atomicrmw xchg ptr %a, i16 0 monotonic, !pcsections !0
ret void
}
-define void @atomic16_add_monotonic(i16* %a) nounwind uwtable {
+define void @atomic16_add_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_add_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] monotonic monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] monotonic monotonic, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -951,18 +951,18 @@ define void @atomic16_add_monotonic(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i16* %a, i16 0 monotonic, !pcsections !0
+ atomicrmw add ptr %a, i16 0 monotonic, !pcsections !0
ret void
}
-define void @atomic16_sub_monotonic(i16* %a) nounwind uwtable {
+define void @atomic16_sub_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_sub_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] monotonic monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] monotonic monotonic, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -970,18 +970,18 @@ define void @atomic16_sub_monotonic(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i16* %a, i16 0 monotonic, !pcsections !0
+ atomicrmw sub ptr %a, i16 0 monotonic, !pcsections !0
ret void
}
-define void @atomic16_and_monotonic(i16* %a) nounwind uwtable {
+define void @atomic16_and_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_and_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 monotonic monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 monotonic monotonic, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -989,18 +989,18 @@ define void @atomic16_and_monotonic(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i16* %a, i16 0 monotonic, !pcsections !0
+ atomicrmw and ptr %a, i16 0 monotonic, !pcsections !0
ret void
}
-define void @atomic16_or_monotonic(i16* %a) nounwind uwtable {
+define void @atomic16_or_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_or_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] monotonic monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] monotonic monotonic, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1008,18 +1008,18 @@ define void @atomic16_or_monotonic(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i16* %a, i16 0 monotonic, !pcsections !0
+ atomicrmw or ptr %a, i16 0 monotonic, !pcsections !0
ret void
}
-define void @atomic16_xor_monotonic(i16* %a) nounwind uwtable {
+define void @atomic16_xor_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_xor_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] monotonic monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] monotonic monotonic, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1027,18 +1027,18 @@ define void @atomic16_xor_monotonic(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i16* %a, i16 0 monotonic, !pcsections !0
+ atomicrmw xor ptr %a, i16 0 monotonic, !pcsections !0
ret void
}
-define void @atomic16_nand_monotonic(i16* %a) nounwind uwtable {
+define void @atomic16_nand_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_nand_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 -1 monotonic monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 -1 monotonic monotonic, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1046,18 +1046,18 @@ define void @atomic16_nand_monotonic(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i16* %a, i16 0 monotonic, !pcsections !0
+ atomicrmw nand ptr %a, i16 0 monotonic, !pcsections !0
ret void
}
-define void @atomic16_xchg_acquire(i16* %a) nounwind uwtable {
+define void @atomic16_xchg_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_xchg_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 acquire acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 acquire acquire, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1065,18 +1065,18 @@ define void @atomic16_xchg_acquire(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i16* %a, i16 0 acquire, !pcsections !0
+ atomicrmw xchg ptr %a, i16 0 acquire, !pcsections !0
ret void
}
-define void @atomic16_add_acquire(i16* %a) nounwind uwtable {
+define void @atomic16_add_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_add_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] acquire acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] acquire acquire, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1084,18 +1084,18 @@ define void @atomic16_add_acquire(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i16* %a, i16 0 acquire, !pcsections !0
+ atomicrmw add ptr %a, i16 0 acquire, !pcsections !0
ret void
}
-define void @atomic16_sub_acquire(i16* %a) nounwind uwtable {
+define void @atomic16_sub_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_sub_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] acquire acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] acquire acquire, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1103,18 +1103,18 @@ define void @atomic16_sub_acquire(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i16* %a, i16 0 acquire, !pcsections !0
+ atomicrmw sub ptr %a, i16 0 acquire, !pcsections !0
ret void
}
-define void @atomic16_and_acquire(i16* %a) nounwind uwtable {
+define void @atomic16_and_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_and_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 acquire acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 acquire acquire, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1122,18 +1122,18 @@ define void @atomic16_and_acquire(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i16* %a, i16 0 acquire, !pcsections !0
+ atomicrmw and ptr %a, i16 0 acquire, !pcsections !0
ret void
}
-define void @atomic16_or_acquire(i16* %a) nounwind uwtable {
+define void @atomic16_or_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_or_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] acquire acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] acquire acquire, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1141,18 +1141,18 @@ define void @atomic16_or_acquire(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i16* %a, i16 0 acquire, !pcsections !0
+ atomicrmw or ptr %a, i16 0 acquire, !pcsections !0
ret void
}
-define void @atomic16_xor_acquire(i16* %a) nounwind uwtable {
+define void @atomic16_xor_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_xor_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] acquire acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] acquire acquire, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1160,18 +1160,18 @@ define void @atomic16_xor_acquire(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i16* %a, i16 0 acquire, !pcsections !0
+ atomicrmw xor ptr %a, i16 0 acquire, !pcsections !0
ret void
}
-define void @atomic16_nand_acquire(i16* %a) nounwind uwtable {
+define void @atomic16_nand_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_nand_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 -1 acquire acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 -1 acquire acquire, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1179,18 +1179,18 @@ define void @atomic16_nand_acquire(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i16* %a, i16 0 acquire, !pcsections !0
+ atomicrmw nand ptr %a, i16 0 acquire, !pcsections !0
ret void
}
-define void @atomic16_xchg_release(i16* %a) nounwind uwtable {
+define void @atomic16_xchg_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_xchg_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 release monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 release monotonic, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1198,18 +1198,18 @@ define void @atomic16_xchg_release(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i16* %a, i16 0 release, !pcsections !0
+ atomicrmw xchg ptr %a, i16 0 release, !pcsections !0
ret void
}
-define void @atomic16_add_release(i16* %a) nounwind uwtable {
+define void @atomic16_add_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_add_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] release monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] release monotonic, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1217,18 +1217,18 @@ define void @atomic16_add_release(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i16* %a, i16 0 release, !pcsections !0
+ atomicrmw add ptr %a, i16 0 release, !pcsections !0
ret void
}
-define void @atomic16_sub_release(i16* %a) nounwind uwtable {
+define void @atomic16_sub_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_sub_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] release monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] release monotonic, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1236,18 +1236,18 @@ define void @atomic16_sub_release(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i16* %a, i16 0 release, !pcsections !0
+ atomicrmw sub ptr %a, i16 0 release, !pcsections !0
ret void
}
-define void @atomic16_and_release(i16* %a) nounwind uwtable {
+define void @atomic16_and_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_and_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 release monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 release monotonic, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1255,18 +1255,18 @@ define void @atomic16_and_release(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i16* %a, i16 0 release, !pcsections !0
+ atomicrmw and ptr %a, i16 0 release, !pcsections !0
ret void
}
-define void @atomic16_or_release(i16* %a) nounwind uwtable {
+define void @atomic16_or_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_or_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] release monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] release monotonic, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1274,18 +1274,18 @@ define void @atomic16_or_release(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i16* %a, i16 0 release, !pcsections !0
+ atomicrmw or ptr %a, i16 0 release, !pcsections !0
ret void
}
-define void @atomic16_xor_release(i16* %a) nounwind uwtable {
+define void @atomic16_xor_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_xor_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] release monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] release monotonic, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1293,18 +1293,18 @@ define void @atomic16_xor_release(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i16* %a, i16 0 release, !pcsections !0
+ atomicrmw xor ptr %a, i16 0 release, !pcsections !0
ret void
}
-define void @atomic16_nand_release(i16* %a) nounwind uwtable {
+define void @atomic16_nand_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_nand_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 -1 release monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 -1 release monotonic, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1312,18 +1312,18 @@ define void @atomic16_nand_release(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i16* %a, i16 0 release, !pcsections !0
+ atomicrmw nand ptr %a, i16 0 release, !pcsections !0
ret void
}
-define void @atomic16_xchg_acq_rel(i16* %a) nounwind uwtable {
+define void @atomic16_xchg_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_xchg_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 acq_rel acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 acq_rel acquire, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1331,18 +1331,18 @@ define void @atomic16_xchg_acq_rel(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i16* %a, i16 0 acq_rel, !pcsections !0
+ atomicrmw xchg ptr %a, i16 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic16_add_acq_rel(i16* %a) nounwind uwtable {
+define void @atomic16_add_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_add_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] acq_rel acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] acq_rel acquire, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1350,18 +1350,18 @@ define void @atomic16_add_acq_rel(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i16* %a, i16 0 acq_rel, !pcsections !0
+ atomicrmw add ptr %a, i16 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic16_sub_acq_rel(i16* %a) nounwind uwtable {
+define void @atomic16_sub_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_sub_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] acq_rel acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] acq_rel acquire, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1369,18 +1369,18 @@ define void @atomic16_sub_acq_rel(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i16* %a, i16 0 acq_rel, !pcsections !0
+ atomicrmw sub ptr %a, i16 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic16_and_acq_rel(i16* %a) nounwind uwtable {
+define void @atomic16_and_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_and_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 acq_rel acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 acq_rel acquire, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1388,18 +1388,18 @@ define void @atomic16_and_acq_rel(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i16* %a, i16 0 acq_rel, !pcsections !0
+ atomicrmw and ptr %a, i16 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic16_or_acq_rel(i16* %a) nounwind uwtable {
+define void @atomic16_or_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_or_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] acq_rel acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] acq_rel acquire, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1407,18 +1407,18 @@ define void @atomic16_or_acq_rel(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i16* %a, i16 0 acq_rel, !pcsections !0
+ atomicrmw or ptr %a, i16 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic16_xor_acq_rel(i16* %a) nounwind uwtable {
+define void @atomic16_xor_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_xor_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] acq_rel acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] acq_rel acquire, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1426,18 +1426,18 @@ define void @atomic16_xor_acq_rel(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i16* %a, i16 0 acq_rel, !pcsections !0
+ atomicrmw xor ptr %a, i16 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic16_nand_acq_rel(i16* %a) nounwind uwtable {
+define void @atomic16_nand_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_nand_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 -1 acq_rel acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 -1 acq_rel acquire, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1445,18 +1445,18 @@ define void @atomic16_nand_acq_rel(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i16* %a, i16 0 acq_rel, !pcsections !0
+ atomicrmw nand ptr %a, i16 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic16_xchg_seq_cst(i16* %a) nounwind uwtable {
+define void @atomic16_xchg_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_xchg_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 seq_cst seq_cst, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 seq_cst seq_cst, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1464,18 +1464,18 @@ define void @atomic16_xchg_seq_cst(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i16* %a, i16 0 seq_cst, !pcsections !0
+ atomicrmw xchg ptr %a, i16 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic16_add_seq_cst(i16* %a) nounwind uwtable {
+define void @atomic16_add_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_add_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] seq_cst seq_cst, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] seq_cst seq_cst, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1483,18 +1483,18 @@ define void @atomic16_add_seq_cst(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i16* %a, i16 0 seq_cst, !pcsections !0
+ atomicrmw add ptr %a, i16 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic16_sub_seq_cst(i16* %a) nounwind uwtable {
+define void @atomic16_sub_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_sub_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] seq_cst seq_cst, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] seq_cst seq_cst, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1502,18 +1502,18 @@ define void @atomic16_sub_seq_cst(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i16* %a, i16 0 seq_cst, !pcsections !0
+ atomicrmw sub ptr %a, i16 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic16_and_seq_cst(i16* %a) nounwind uwtable {
+define void @atomic16_and_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_and_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 seq_cst seq_cst, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 seq_cst seq_cst, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1521,18 +1521,18 @@ define void @atomic16_and_seq_cst(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i16* %a, i16 0 seq_cst, !pcsections !0
+ atomicrmw and ptr %a, i16 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic16_or_seq_cst(i16* %a) nounwind uwtable {
+define void @atomic16_or_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_or_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] seq_cst seq_cst, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] seq_cst seq_cst, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1540,18 +1540,18 @@ define void @atomic16_or_seq_cst(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i16* %a, i16 0 seq_cst, !pcsections !0
+ atomicrmw or ptr %a, i16 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic16_xor_seq_cst(i16* %a) nounwind uwtable {
+define void @atomic16_xor_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_xor_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] seq_cst seq_cst, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] seq_cst seq_cst, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1559,18 +1559,18 @@ define void @atomic16_xor_seq_cst(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i16* %a, i16 0 seq_cst, !pcsections !0
+ atomicrmw xor ptr %a, i16 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic16_nand_seq_cst(i16* %a) nounwind uwtable {
+define void @atomic16_nand_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_nand_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 -1 seq_cst seq_cst, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 -1 seq_cst seq_cst, align 2, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1578,181 +1578,181 @@ define void @atomic16_nand_seq_cst(i16* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i16* %a, i16 0 seq_cst, !pcsections !0
+ atomicrmw nand ptr %a, i16 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic16_cas_monotonic(i16* %a) nounwind uwtable {
+define void @atomic16_cas_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_cas_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i16* [[A:%.*]], i16 0, i16 1 monotonic monotonic, align 2, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 monotonic acquire, align 2, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 monotonic seq_cst, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i16 0, i16 1 monotonic monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 monotonic acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 monotonic seq_cst, align 2, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i16* %a, i16 0, i16 1 monotonic monotonic, !pcsections !0
- cmpxchg i16* %a, i16 0, i16 1 monotonic acquire, !pcsections !0
- cmpxchg i16* %a, i16 0, i16 1 monotonic seq_cst, !pcsections !0
+ cmpxchg ptr %a, i16 0, i16 1 monotonic monotonic, !pcsections !0
+ cmpxchg ptr %a, i16 0, i16 1 monotonic acquire, !pcsections !0
+ cmpxchg ptr %a, i16 0, i16 1 monotonic seq_cst, !pcsections !0
ret void
}
-define void @atomic16_cas_acquire(i16* %a) nounwind uwtable {
+define void @atomic16_cas_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_cas_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i16* [[A:%.*]], i16 0, i16 1 acquire monotonic, align 2, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 acquire acquire, align 2, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 acquire seq_cst, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i16 0, i16 1 acquire monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 acquire acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 acquire seq_cst, align 2, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i16* %a, i16 0, i16 1 acquire monotonic, !pcsections !0
- cmpxchg i16* %a, i16 0, i16 1 acquire acquire, !pcsections !0
- cmpxchg i16* %a, i16 0, i16 1 acquire seq_cst, !pcsections !0
+ cmpxchg ptr %a, i16 0, i16 1 acquire monotonic, !pcsections !0
+ cmpxchg ptr %a, i16 0, i16 1 acquire acquire, !pcsections !0
+ cmpxchg ptr %a, i16 0, i16 1 acquire seq_cst, !pcsections !0
ret void
}
-define void @atomic16_cas_release(i16* %a) nounwind uwtable {
+define void @atomic16_cas_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_cas_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i16* [[A:%.*]], i16 0, i16 1 release monotonic, align 2, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 release acquire, align 2, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 release seq_cst, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i16 0, i16 1 release monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 release acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 release seq_cst, align 2, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i16* %a, i16 0, i16 1 release monotonic, !pcsections !0
- cmpxchg i16* %a, i16 0, i16 1 release acquire, !pcsections !0
- cmpxchg i16* %a, i16 0, i16 1 release seq_cst, !pcsections !0
+ cmpxchg ptr %a, i16 0, i16 1 release monotonic, !pcsections !0
+ cmpxchg ptr %a, i16 0, i16 1 release acquire, !pcsections !0
+ cmpxchg ptr %a, i16 0, i16 1 release seq_cst, !pcsections !0
ret void
}
-define void @atomic16_cas_acq_rel(i16* %a) nounwind uwtable {
+define void @atomic16_cas_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_cas_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i16* [[A:%.*]], i16 0, i16 1 acq_rel monotonic, align 2, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 acq_rel acquire, align 2, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 acq_rel seq_cst, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i16 0, i16 1 acq_rel monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 acq_rel acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 acq_rel seq_cst, align 2, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i16* %a, i16 0, i16 1 acq_rel monotonic, !pcsections !0
- cmpxchg i16* %a, i16 0, i16 1 acq_rel acquire, !pcsections !0
- cmpxchg i16* %a, i16 0, i16 1 acq_rel seq_cst, !pcsections !0
+ cmpxchg ptr %a, i16 0, i16 1 acq_rel monotonic, !pcsections !0
+ cmpxchg ptr %a, i16 0, i16 1 acq_rel acquire, !pcsections !0
+ cmpxchg ptr %a, i16 0, i16 1 acq_rel seq_cst, !pcsections !0
ret void
}
-define void @atomic16_cas_seq_cst(i16* %a) nounwind uwtable {
+define void @atomic16_cas_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic16_cas_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i16* [[A:%.*]], i16 0, i16 1 seq_cst monotonic, align 2, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 seq_cst acquire, align 2, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 seq_cst seq_cst, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i16 0, i16 1 seq_cst monotonic, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 seq_cst acquire, align 2, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 seq_cst seq_cst, align 2, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i16* %a, i16 0, i16 1 seq_cst monotonic, !pcsections !0
- cmpxchg i16* %a, i16 0, i16 1 seq_cst acquire, !pcsections !0
- cmpxchg i16* %a, i16 0, i16 1 seq_cst seq_cst, !pcsections !0
+ cmpxchg ptr %a, i16 0, i16 1 seq_cst monotonic, !pcsections !0
+ cmpxchg ptr %a, i16 0, i16 1 seq_cst acquire, !pcsections !0
+ cmpxchg ptr %a, i16 0, i16 1 seq_cst seq_cst, !pcsections !0
ret void
}
-define i32 @atomic32_load_unordered(i32* %a) nounwind uwtable {
+define i32 @atomic32_load_unordered(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_load_unordered(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, i32* [[A:%.*]] unordered, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, ptr [[A:%.*]] unordered, align 4, !pcsections !0
; CHECK-NEXT: ret i32 [[TMP0]]
;
entry:
- %0 = load atomic i32, i32* %a unordered, align 4, !pcsections !0
+ %0 = load atomic i32, ptr %a unordered, align 4, !pcsections !0
ret i32 %0
}
-define i32 @atomic32_load_monotonic(i32* %a) nounwind uwtable {
+define i32 @atomic32_load_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_load_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, i32* [[A:%.*]] monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, ptr [[A:%.*]] monotonic, align 4, !pcsections !0
; CHECK-NEXT: ret i32 [[TMP0]]
;
entry:
- %0 = load atomic i32, i32* %a monotonic, align 4, !pcsections !0
+ %0 = load atomic i32, ptr %a monotonic, align 4, !pcsections !0
ret i32 %0
}
-define i32 @atomic32_load_acquire(i32* %a) nounwind uwtable {
+define i32 @atomic32_load_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_load_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, i32* [[A:%.*]] acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, ptr [[A:%.*]] acquire, align 4, !pcsections !0
; CHECK-NEXT: ret i32 [[TMP0]]
;
entry:
- %0 = load atomic i32, i32* %a acquire, align 4, !pcsections !0
+ %0 = load atomic i32, ptr %a acquire, align 4, !pcsections !0
ret i32 %0
}
-define i32 @atomic32_load_seq_cst(i32* %a) nounwind uwtable {
+define i32 @atomic32_load_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_load_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, i32* [[A:%.*]] seq_cst, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, ptr [[A:%.*]] seq_cst, align 4, !pcsections !0
; CHECK-NEXT: ret i32 [[TMP0]]
;
entry:
- %0 = load atomic i32, i32* %a seq_cst, align 4, !pcsections !0
+ %0 = load atomic i32, ptr %a seq_cst, align 4, !pcsections !0
ret i32 %0
}
-define void @atomic32_store_unordered(i32* %a) nounwind uwtable {
+define void @atomic32_store_unordered(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_store_unordered(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store atomic i32 0, i32* [[A:%.*]] unordered, align 4, !pcsections !0
+; CHECK-NEXT: store atomic i32 0, ptr [[A:%.*]] unordered, align 4, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- store atomic i32 0, i32* %a unordered, align 4, !pcsections !0
+ store atomic i32 0, ptr %a unordered, align 4, !pcsections !0
ret void
}
-define void @atomic32_store_monotonic(i32* %a) nounwind uwtable {
+define void @atomic32_store_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_store_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store atomic i32 0, i32* [[A:%.*]] monotonic, align 4, !pcsections !0
+; CHECK-NEXT: store atomic i32 0, ptr [[A:%.*]] monotonic, align 4, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- store atomic i32 0, i32* %a monotonic, align 4, !pcsections !0
+ store atomic i32 0, ptr %a monotonic, align 4, !pcsections !0
ret void
}
-define void @atomic32_store_release(i32* %a) nounwind uwtable {
+define void @atomic32_store_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_store_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store atomic i32 0, i32* [[A:%.*]] release, align 4, !pcsections !0
+; CHECK-NEXT: store atomic i32 0, ptr [[A:%.*]] release, align 4, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- store atomic i32 0, i32* %a release, align 4, !pcsections !0
+ store atomic i32 0, ptr %a release, align 4, !pcsections !0
ret void
}
-define void @atomic32_store_seq_cst(i32* %a) nounwind uwtable {
+define void @atomic32_store_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_store_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store atomic i32 0, i32* [[A:%.*]] seq_cst, align 4, !pcsections !0
+; CHECK-NEXT: store atomic i32 0, ptr [[A:%.*]] seq_cst, align 4, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- store atomic i32 0, i32* %a seq_cst, align 4, !pcsections !0
+ store atomic i32 0, ptr %a seq_cst, align 4, !pcsections !0
ret void
}
-define void @atomic32_xchg_monotonic(i32* %a) nounwind uwtable {
+define void @atomic32_xchg_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_xchg_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 monotonic monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 monotonic monotonic, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1760,18 +1760,18 @@ define void @atomic32_xchg_monotonic(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i32* %a, i32 0 monotonic, !pcsections !0
+ atomicrmw xchg ptr %a, i32 0 monotonic, !pcsections !0
ret void
}
-define void @atomic32_add_monotonic(i32* %a) nounwind uwtable {
+define void @atomic32_add_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_add_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] monotonic monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] monotonic monotonic, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1779,18 +1779,18 @@ define void @atomic32_add_monotonic(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i32* %a, i32 0 monotonic, !pcsections !0
+ atomicrmw add ptr %a, i32 0 monotonic, !pcsections !0
ret void
}
-define void @atomic32_sub_monotonic(i32* %a) nounwind uwtable {
+define void @atomic32_sub_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_sub_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] monotonic monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] monotonic monotonic, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1798,18 +1798,18 @@ define void @atomic32_sub_monotonic(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i32* %a, i32 0 monotonic, !pcsections !0
+ atomicrmw sub ptr %a, i32 0 monotonic, !pcsections !0
ret void
}
-define void @atomic32_and_monotonic(i32* %a) nounwind uwtable {
+define void @atomic32_and_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_and_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 monotonic monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 monotonic monotonic, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1817,18 +1817,18 @@ define void @atomic32_and_monotonic(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i32* %a, i32 0 monotonic, !pcsections !0
+ atomicrmw and ptr %a, i32 0 monotonic, !pcsections !0
ret void
}
-define void @atomic32_or_monotonic(i32* %a) nounwind uwtable {
+define void @atomic32_or_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_or_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] monotonic monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] monotonic monotonic, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1836,18 +1836,18 @@ define void @atomic32_or_monotonic(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i32* %a, i32 0 monotonic, !pcsections !0
+ atomicrmw or ptr %a, i32 0 monotonic, !pcsections !0
ret void
}
-define void @atomic32_xor_monotonic(i32* %a) nounwind uwtable {
+define void @atomic32_xor_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_xor_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] monotonic monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] monotonic monotonic, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1855,18 +1855,18 @@ define void @atomic32_xor_monotonic(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i32* %a, i32 0 monotonic, !pcsections !0
+ atomicrmw xor ptr %a, i32 0 monotonic, !pcsections !0
ret void
}
-define void @atomic32_nand_monotonic(i32* %a) nounwind uwtable {
+define void @atomic32_nand_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_nand_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 -1 monotonic monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 -1 monotonic monotonic, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1874,18 +1874,18 @@ define void @atomic32_nand_monotonic(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i32* %a, i32 0 monotonic, !pcsections !0
+ atomicrmw nand ptr %a, i32 0 monotonic, !pcsections !0
ret void
}
-define void @atomic32_xchg_acquire(i32* %a) nounwind uwtable {
+define void @atomic32_xchg_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_xchg_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 acquire acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 acquire acquire, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1893,18 +1893,18 @@ define void @atomic32_xchg_acquire(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i32* %a, i32 0 acquire, !pcsections !0
+ atomicrmw xchg ptr %a, i32 0 acquire, !pcsections !0
ret void
}
-define void @atomic32_add_acquire(i32* %a) nounwind uwtable {
+define void @atomic32_add_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_add_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] acquire acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] acquire acquire, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1912,18 +1912,18 @@ define void @atomic32_add_acquire(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i32* %a, i32 0 acquire, !pcsections !0
+ atomicrmw add ptr %a, i32 0 acquire, !pcsections !0
ret void
}
-define void @atomic32_sub_acquire(i32* %a) nounwind uwtable {
+define void @atomic32_sub_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_sub_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] acquire acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] acquire acquire, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1931,18 +1931,18 @@ define void @atomic32_sub_acquire(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i32* %a, i32 0 acquire, !pcsections !0
+ atomicrmw sub ptr %a, i32 0 acquire, !pcsections !0
ret void
}
-define void @atomic32_and_acquire(i32* %a) nounwind uwtable {
+define void @atomic32_and_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_and_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 acquire acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 acquire acquire, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1950,18 +1950,18 @@ define void @atomic32_and_acquire(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i32* %a, i32 0 acquire, !pcsections !0
+ atomicrmw and ptr %a, i32 0 acquire, !pcsections !0
ret void
}
-define void @atomic32_or_acquire(i32* %a) nounwind uwtable {
+define void @atomic32_or_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_or_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] acquire acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] acquire acquire, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1969,18 +1969,18 @@ define void @atomic32_or_acquire(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i32* %a, i32 0 acquire, !pcsections !0
+ atomicrmw or ptr %a, i32 0 acquire, !pcsections !0
ret void
}
-define void @atomic32_xor_acquire(i32* %a) nounwind uwtable {
+define void @atomic32_xor_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_xor_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] acquire acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] acquire acquire, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -1988,18 +1988,18 @@ define void @atomic32_xor_acquire(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i32* %a, i32 0 acquire, !pcsections !0
+ atomicrmw xor ptr %a, i32 0 acquire, !pcsections !0
ret void
}
-define void @atomic32_nand_acquire(i32* %a) nounwind uwtable {
+define void @atomic32_nand_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_nand_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 -1 acquire acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 -1 acquire acquire, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2007,18 +2007,18 @@ define void @atomic32_nand_acquire(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i32* %a, i32 0 acquire, !pcsections !0
+ atomicrmw nand ptr %a, i32 0 acquire, !pcsections !0
ret void
}
-define void @atomic32_xchg_release(i32* %a) nounwind uwtable {
+define void @atomic32_xchg_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_xchg_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 release monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 release monotonic, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2026,18 +2026,18 @@ define void @atomic32_xchg_release(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i32* %a, i32 0 release, !pcsections !0
+ atomicrmw xchg ptr %a, i32 0 release, !pcsections !0
ret void
}
-define void @atomic32_add_release(i32* %a) nounwind uwtable {
+define void @atomic32_add_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_add_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] release monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] release monotonic, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2045,18 +2045,18 @@ define void @atomic32_add_release(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i32* %a, i32 0 release, !pcsections !0
+ atomicrmw add ptr %a, i32 0 release, !pcsections !0
ret void
}
-define void @atomic32_sub_release(i32* %a) nounwind uwtable {
+define void @atomic32_sub_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_sub_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] release monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] release monotonic, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2064,18 +2064,18 @@ define void @atomic32_sub_release(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i32* %a, i32 0 release, !pcsections !0
+ atomicrmw sub ptr %a, i32 0 release, !pcsections !0
ret void
}
-define void @atomic32_and_release(i32* %a) nounwind uwtable {
+define void @atomic32_and_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_and_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 release monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 release monotonic, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2083,18 +2083,18 @@ define void @atomic32_and_release(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i32* %a, i32 0 release, !pcsections !0
+ atomicrmw and ptr %a, i32 0 release, !pcsections !0
ret void
}
-define void @atomic32_or_release(i32* %a) nounwind uwtable {
+define void @atomic32_or_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_or_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] release monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] release monotonic, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2102,18 +2102,18 @@ define void @atomic32_or_release(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i32* %a, i32 0 release, !pcsections !0
+ atomicrmw or ptr %a, i32 0 release, !pcsections !0
ret void
}
-define void @atomic32_xor_release(i32* %a) nounwind uwtable {
+define void @atomic32_xor_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_xor_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] release monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] release monotonic, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2121,18 +2121,18 @@ define void @atomic32_xor_release(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i32* %a, i32 0 release, !pcsections !0
+ atomicrmw xor ptr %a, i32 0 release, !pcsections !0
ret void
}
-define void @atomic32_nand_release(i32* %a) nounwind uwtable {
+define void @atomic32_nand_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_nand_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 -1 release monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 -1 release monotonic, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2140,18 +2140,18 @@ define void @atomic32_nand_release(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i32* %a, i32 0 release, !pcsections !0
+ atomicrmw nand ptr %a, i32 0 release, !pcsections !0
ret void
}
-define void @atomic32_xchg_acq_rel(i32* %a) nounwind uwtable {
+define void @atomic32_xchg_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_xchg_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 acq_rel acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 acq_rel acquire, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2159,18 +2159,18 @@ define void @atomic32_xchg_acq_rel(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i32* %a, i32 0 acq_rel, !pcsections !0
+ atomicrmw xchg ptr %a, i32 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic32_add_acq_rel(i32* %a) nounwind uwtable {
+define void @atomic32_add_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_add_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] acq_rel acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] acq_rel acquire, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2178,18 +2178,18 @@ define void @atomic32_add_acq_rel(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i32* %a, i32 0 acq_rel, !pcsections !0
+ atomicrmw add ptr %a, i32 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic32_sub_acq_rel(i32* %a) nounwind uwtable {
+define void @atomic32_sub_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_sub_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] acq_rel acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] acq_rel acquire, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2197,18 +2197,18 @@ define void @atomic32_sub_acq_rel(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i32* %a, i32 0 acq_rel, !pcsections !0
+ atomicrmw sub ptr %a, i32 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic32_and_acq_rel(i32* %a) nounwind uwtable {
+define void @atomic32_and_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_and_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 acq_rel acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 acq_rel acquire, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2216,18 +2216,18 @@ define void @atomic32_and_acq_rel(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i32* %a, i32 0 acq_rel, !pcsections !0
+ atomicrmw and ptr %a, i32 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic32_or_acq_rel(i32* %a) nounwind uwtable {
+define void @atomic32_or_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_or_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] acq_rel acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] acq_rel acquire, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2235,18 +2235,18 @@ define void @atomic32_or_acq_rel(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i32* %a, i32 0 acq_rel, !pcsections !0
+ atomicrmw or ptr %a, i32 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic32_xor_acq_rel(i32* %a) nounwind uwtable {
+define void @atomic32_xor_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_xor_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] acq_rel acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] acq_rel acquire, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2254,18 +2254,18 @@ define void @atomic32_xor_acq_rel(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i32* %a, i32 0 acq_rel, !pcsections !0
+ atomicrmw xor ptr %a, i32 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic32_nand_acq_rel(i32* %a) nounwind uwtable {
+define void @atomic32_nand_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_nand_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 -1 acq_rel acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 -1 acq_rel acquire, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2273,18 +2273,18 @@ define void @atomic32_nand_acq_rel(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i32* %a, i32 0 acq_rel, !pcsections !0
+ atomicrmw nand ptr %a, i32 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic32_xchg_seq_cst(i32* %a) nounwind uwtable {
+define void @atomic32_xchg_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_xchg_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 seq_cst seq_cst, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 seq_cst seq_cst, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2292,18 +2292,18 @@ define void @atomic32_xchg_seq_cst(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i32* %a, i32 0 seq_cst, !pcsections !0
+ atomicrmw xchg ptr %a, i32 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic32_add_seq_cst(i32* %a) nounwind uwtable {
+define void @atomic32_add_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_add_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] seq_cst seq_cst, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] seq_cst seq_cst, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2311,18 +2311,18 @@ define void @atomic32_add_seq_cst(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i32* %a, i32 0 seq_cst, !pcsections !0
+ atomicrmw add ptr %a, i32 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic32_sub_seq_cst(i32* %a) nounwind uwtable {
+define void @atomic32_sub_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_sub_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] seq_cst seq_cst, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] seq_cst seq_cst, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2330,18 +2330,18 @@ define void @atomic32_sub_seq_cst(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i32* %a, i32 0 seq_cst, !pcsections !0
+ atomicrmw sub ptr %a, i32 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic32_and_seq_cst(i32* %a) nounwind uwtable {
+define void @atomic32_and_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_and_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 seq_cst seq_cst, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 seq_cst seq_cst, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2349,18 +2349,18 @@ define void @atomic32_and_seq_cst(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i32* %a, i32 0 seq_cst, !pcsections !0
+ atomicrmw and ptr %a, i32 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic32_or_seq_cst(i32* %a) nounwind uwtable {
+define void @atomic32_or_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_or_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] seq_cst seq_cst, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] seq_cst seq_cst, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2368,18 +2368,18 @@ define void @atomic32_or_seq_cst(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i32* %a, i32 0 seq_cst, !pcsections !0
+ atomicrmw or ptr %a, i32 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic32_xor_seq_cst(i32* %a) nounwind uwtable {
+define void @atomic32_xor_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_xor_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] seq_cst seq_cst, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] seq_cst seq_cst, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2387,18 +2387,18 @@ define void @atomic32_xor_seq_cst(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i32* %a, i32 0 seq_cst, !pcsections !0
+ atomicrmw xor ptr %a, i32 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic32_nand_seq_cst(i32* %a) nounwind uwtable {
+define void @atomic32_nand_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_nand_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 -1 seq_cst seq_cst, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 -1 seq_cst seq_cst, align 4, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2406,203 +2406,203 @@ define void @atomic32_nand_seq_cst(i32* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i32* %a, i32 0 seq_cst, !pcsections !0
+ atomicrmw nand ptr %a, i32 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic32_cas_monotonic(i32* %a) nounwind uwtable {
+define void @atomic32_cas_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_cas_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i32* [[A:%.*]], i32 0, i32 1 monotonic monotonic, align 4, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 monotonic acquire, align 4, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 monotonic seq_cst, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i32 0, i32 1 monotonic monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 monotonic acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 monotonic seq_cst, align 4, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i32* %a, i32 0, i32 1 monotonic monotonic, !pcsections !0
- cmpxchg i32* %a, i32 0, i32 1 monotonic acquire, !pcsections !0
- cmpxchg i32* %a, i32 0, i32 1 monotonic seq_cst, !pcsections !0
+ cmpxchg ptr %a, i32 0, i32 1 monotonic monotonic, !pcsections !0
+ cmpxchg ptr %a, i32 0, i32 1 monotonic acquire, !pcsections !0
+ cmpxchg ptr %a, i32 0, i32 1 monotonic seq_cst, !pcsections !0
ret void
}
-define void @atomic32_cas_acquire(i32* %a) nounwind uwtable {
+define void @atomic32_cas_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_cas_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i32* [[A:%.*]], i32 0, i32 1 acquire monotonic, align 4, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 acquire acquire, align 4, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 acquire seq_cst, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i32 0, i32 1 acquire monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 acquire acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 acquire seq_cst, align 4, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i32* %a, i32 0, i32 1 acquire monotonic, !pcsections !0
- cmpxchg i32* %a, i32 0, i32 1 acquire acquire, !pcsections !0
- cmpxchg i32* %a, i32 0, i32 1 acquire seq_cst, !pcsections !0
+ cmpxchg ptr %a, i32 0, i32 1 acquire monotonic, !pcsections !0
+ cmpxchg ptr %a, i32 0, i32 1 acquire acquire, !pcsections !0
+ cmpxchg ptr %a, i32 0, i32 1 acquire seq_cst, !pcsections !0
ret void
}
-define void @atomic32_cas_release(i32* %a) nounwind uwtable {
+define void @atomic32_cas_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_cas_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i32* [[A:%.*]], i32 0, i32 1 release monotonic, align 4, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 release acquire, align 4, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 release seq_cst, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i32 0, i32 1 release monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 release acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 release seq_cst, align 4, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i32* %a, i32 0, i32 1 release monotonic, !pcsections !0
- cmpxchg i32* %a, i32 0, i32 1 release acquire, !pcsections !0
- cmpxchg i32* %a, i32 0, i32 1 release seq_cst, !pcsections !0
+ cmpxchg ptr %a, i32 0, i32 1 release monotonic, !pcsections !0
+ cmpxchg ptr %a, i32 0, i32 1 release acquire, !pcsections !0
+ cmpxchg ptr %a, i32 0, i32 1 release seq_cst, !pcsections !0
ret void
}
-define void @atomic32_cas_acq_rel(i32* %a) nounwind uwtable {
+define void @atomic32_cas_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_cas_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i32* [[A:%.*]], i32 0, i32 1 acq_rel monotonic, align 4, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 acq_rel acquire, align 4, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 acq_rel seq_cst, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i32 0, i32 1 acq_rel monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 acq_rel acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 acq_rel seq_cst, align 4, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i32* %a, i32 0, i32 1 acq_rel monotonic, !pcsections !0
- cmpxchg i32* %a, i32 0, i32 1 acq_rel acquire, !pcsections !0
- cmpxchg i32* %a, i32 0, i32 1 acq_rel seq_cst, !pcsections !0
+ cmpxchg ptr %a, i32 0, i32 1 acq_rel monotonic, !pcsections !0
+ cmpxchg ptr %a, i32 0, i32 1 acq_rel acquire, !pcsections !0
+ cmpxchg ptr %a, i32 0, i32 1 acq_rel seq_cst, !pcsections !0
ret void
}
-define void @atomic32_cas_seq_cst(i32* %a) nounwind uwtable {
+define void @atomic32_cas_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic32_cas_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i32* [[A:%.*]], i32 0, i32 1 seq_cst monotonic, align 4, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 seq_cst acquire, align 4, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 seq_cst seq_cst, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i32 0, i32 1 seq_cst monotonic, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 seq_cst acquire, align 4, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 seq_cst seq_cst, align 4, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i32* %a, i32 0, i32 1 seq_cst monotonic, !pcsections !0
- cmpxchg i32* %a, i32 0, i32 1 seq_cst acquire, !pcsections !0
- cmpxchg i32* %a, i32 0, i32 1 seq_cst seq_cst, !pcsections !0
+ cmpxchg ptr %a, i32 0, i32 1 seq_cst monotonic, !pcsections !0
+ cmpxchg ptr %a, i32 0, i32 1 seq_cst acquire, !pcsections !0
+ cmpxchg ptr %a, i32 0, i32 1 seq_cst seq_cst, !pcsections !0
ret void
}
-define i64 @atomic64_load_unordered(i64* %a) nounwind uwtable {
+define i64 @atomic64_load_unordered(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_load_unordered(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, i64* [[A:%.*]] unordered, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, ptr [[A:%.*]] unordered, align 8, !pcsections !0
; CHECK-NEXT: ret i64 [[TMP0]]
;
entry:
- %0 = load atomic i64, i64* %a unordered, align 8, !pcsections !0
+ %0 = load atomic i64, ptr %a unordered, align 8, !pcsections !0
ret i64 %0
}
-define i64 @atomic64_load_monotonic(i64* %a) nounwind uwtable {
+define i64 @atomic64_load_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_load_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, i64* [[A:%.*]] monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, ptr [[A:%.*]] monotonic, align 8, !pcsections !0
; CHECK-NEXT: ret i64 [[TMP0]]
;
entry:
- %0 = load atomic i64, i64* %a monotonic, align 8, !pcsections !0
+ %0 = load atomic i64, ptr %a monotonic, align 8, !pcsections !0
ret i64 %0
}
-define i64 @atomic64_load_acquire(i64* %a) nounwind uwtable {
+define i64 @atomic64_load_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_load_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, i64* [[A:%.*]] acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, ptr [[A:%.*]] acquire, align 8, !pcsections !0
; CHECK-NEXT: ret i64 [[TMP0]]
;
entry:
- %0 = load atomic i64, i64* %a acquire, align 8, !pcsections !0
+ %0 = load atomic i64, ptr %a acquire, align 8, !pcsections !0
ret i64 %0
}
-define i64 @atomic64_load_seq_cst(i64* %a) nounwind uwtable {
+define i64 @atomic64_load_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_load_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, i64* [[A:%.*]] seq_cst, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, ptr [[A:%.*]] seq_cst, align 8, !pcsections !0
; CHECK-NEXT: ret i64 [[TMP0]]
;
entry:
- %0 = load atomic i64, i64* %a seq_cst, align 8, !pcsections !0
+ %0 = load atomic i64, ptr %a seq_cst, align 8, !pcsections !0
ret i64 %0
}
-define i8* @atomic64_load_seq_cst_ptr_ty(i8** %a) nounwind uwtable {
+define ptr @atomic64_load_seq_cst_ptr_ty(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_load_seq_cst_ptr_ty(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load atomic i8*, i8** [[A:%.*]] seq_cst, align 8, !pcsections !0
-; CHECK-NEXT: ret i8* [[TMP0]]
+; CHECK-NEXT: [[TMP0:%.*]] = load atomic ptr, ptr [[A:%.*]] seq_cst, align 8, !pcsections !0
+; CHECK-NEXT: ret ptr [[TMP0]]
;
entry:
- %0 = load atomic i8*, i8** %a seq_cst, align 8, !pcsections !0
- ret i8* %0
+ %0 = load atomic ptr, ptr %a seq_cst, align 8, !pcsections !0
+ ret ptr %0
}
-define void @atomic64_store_unordered(i64* %a) nounwind uwtable {
+define void @atomic64_store_unordered(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_store_unordered(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store atomic i64 0, i64* [[A:%.*]] unordered, align 8, !pcsections !0
+; CHECK-NEXT: store atomic i64 0, ptr [[A:%.*]] unordered, align 8, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- store atomic i64 0, i64* %a unordered, align 8, !pcsections !0
+ store atomic i64 0, ptr %a unordered, align 8, !pcsections !0
ret void
}
-define void @atomic64_store_monotonic(i64* %a) nounwind uwtable {
+define void @atomic64_store_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_store_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store atomic i64 0, i64* [[A:%.*]] monotonic, align 8, !pcsections !0
+; CHECK-NEXT: store atomic i64 0, ptr [[A:%.*]] monotonic, align 8, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- store atomic i64 0, i64* %a monotonic, align 8, !pcsections !0
+ store atomic i64 0, ptr %a monotonic, align 8, !pcsections !0
ret void
}
-define void @atomic64_store_release(i64* %a) nounwind uwtable {
+define void @atomic64_store_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_store_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store atomic i64 0, i64* [[A:%.*]] release, align 8, !pcsections !0
+; CHECK-NEXT: store atomic i64 0, ptr [[A:%.*]] release, align 8, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- store atomic i64 0, i64* %a release, align 8, !pcsections !0
+ store atomic i64 0, ptr %a release, align 8, !pcsections !0
ret void
}
-define void @atomic64_store_seq_cst(i64* %a) nounwind uwtable {
+define void @atomic64_store_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_store_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store atomic i64 0, i64* [[A:%.*]] seq_cst, align 8, !pcsections !0
+; CHECK-NEXT: store atomic i64 0, ptr [[A:%.*]] seq_cst, align 8, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- store atomic i64 0, i64* %a seq_cst, align 8, !pcsections !0
+ store atomic i64 0, ptr %a seq_cst, align 8, !pcsections !0
ret void
}
-define void @atomic64_store_seq_cst_ptr_ty(i8** %a, i8* %v) nounwind uwtable {
+define void @atomic64_store_seq_cst_ptr_ty(ptr %a, ptr %v) nounwind uwtable {
; CHECK-LABEL: @atomic64_store_seq_cst_ptr_ty(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store atomic i8* [[V:%.*]], i8** [[A:%.*]] seq_cst, align 8, !pcsections !0
+; CHECK-NEXT: store atomic ptr [[V:%.*]], ptr [[A:%.*]] seq_cst, align 8, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- store atomic i8* %v, i8** %a seq_cst, align 8, !pcsections !0
+ store atomic ptr %v, ptr %a seq_cst, align 8, !pcsections !0
ret void
}
-define void @atomic64_xchg_monotonic(i64* %a) nounwind uwtable {
+define void @atomic64_xchg_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_xchg_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 monotonic monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 monotonic monotonic, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2610,18 +2610,18 @@ define void @atomic64_xchg_monotonic(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i64* %a, i64 0 monotonic, !pcsections !0
+ atomicrmw xchg ptr %a, i64 0 monotonic, !pcsections !0
ret void
}
-define void @atomic64_add_monotonic(i64* %a) nounwind uwtable {
+define void @atomic64_add_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_add_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] monotonic monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] monotonic monotonic, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2629,18 +2629,18 @@ define void @atomic64_add_monotonic(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i64* %a, i64 0 monotonic, !pcsections !0
+ atomicrmw add ptr %a, i64 0 monotonic, !pcsections !0
ret void
}
-define void @atomic64_sub_monotonic(i64* %a) nounwind uwtable {
+define void @atomic64_sub_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_sub_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] monotonic monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] monotonic monotonic, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2648,18 +2648,18 @@ define void @atomic64_sub_monotonic(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i64* %a, i64 0 monotonic, !pcsections !0
+ atomicrmw sub ptr %a, i64 0 monotonic, !pcsections !0
ret void
}
-define void @atomic64_and_monotonic(i64* %a) nounwind uwtable {
+define void @atomic64_and_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_and_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 monotonic monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 monotonic monotonic, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2667,18 +2667,18 @@ define void @atomic64_and_monotonic(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i64* %a, i64 0 monotonic, !pcsections !0
+ atomicrmw and ptr %a, i64 0 monotonic, !pcsections !0
ret void
}
-define void @atomic64_or_monotonic(i64* %a) nounwind uwtable {
+define void @atomic64_or_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_or_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] monotonic monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] monotonic monotonic, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2686,18 +2686,18 @@ define void @atomic64_or_monotonic(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i64* %a, i64 0 monotonic, !pcsections !0
+ atomicrmw or ptr %a, i64 0 monotonic, !pcsections !0
ret void
}
-define void @atomic64_xor_monotonic(i64* %a) nounwind uwtable {
+define void @atomic64_xor_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_xor_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] monotonic monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] monotonic monotonic, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2705,18 +2705,18 @@ define void @atomic64_xor_monotonic(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i64* %a, i64 0 monotonic, !pcsections !0
+ atomicrmw xor ptr %a, i64 0 monotonic, !pcsections !0
ret void
}
-define void @atomic64_nand_monotonic(i64* %a) nounwind uwtable {
+define void @atomic64_nand_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_nand_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 -1 monotonic monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 -1 monotonic monotonic, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2724,18 +2724,18 @@ define void @atomic64_nand_monotonic(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i64* %a, i64 0 monotonic, !pcsections !0
+ atomicrmw nand ptr %a, i64 0 monotonic, !pcsections !0
ret void
}
-define void @atomic64_xchg_acquire(i64* %a) nounwind uwtable {
+define void @atomic64_xchg_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_xchg_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 acquire acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 acquire acquire, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2743,18 +2743,18 @@ define void @atomic64_xchg_acquire(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i64* %a, i64 0 acquire, !pcsections !0
+ atomicrmw xchg ptr %a, i64 0 acquire, !pcsections !0
ret void
}
-define void @atomic64_add_acquire(i64* %a) nounwind uwtable {
+define void @atomic64_add_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_add_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] acquire acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] acquire acquire, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2762,18 +2762,18 @@ define void @atomic64_add_acquire(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i64* %a, i64 0 acquire, !pcsections !0
+ atomicrmw add ptr %a, i64 0 acquire, !pcsections !0
ret void
}
-define void @atomic64_sub_acquire(i64* %a) nounwind uwtable {
+define void @atomic64_sub_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_sub_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] acquire acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] acquire acquire, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2781,18 +2781,18 @@ define void @atomic64_sub_acquire(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i64* %a, i64 0 acquire, !pcsections !0
+ atomicrmw sub ptr %a, i64 0 acquire, !pcsections !0
ret void
}
-define void @atomic64_and_acquire(i64* %a) nounwind uwtable {
+define void @atomic64_and_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_and_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 acquire acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 acquire acquire, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2800,18 +2800,18 @@ define void @atomic64_and_acquire(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i64* %a, i64 0 acquire, !pcsections !0
+ atomicrmw and ptr %a, i64 0 acquire, !pcsections !0
ret void
}
-define void @atomic64_or_acquire(i64* %a) nounwind uwtable {
+define void @atomic64_or_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_or_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] acquire acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] acquire acquire, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2819,18 +2819,18 @@ define void @atomic64_or_acquire(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i64* %a, i64 0 acquire, !pcsections !0
+ atomicrmw or ptr %a, i64 0 acquire, !pcsections !0
ret void
}
-define void @atomic64_xor_acquire(i64* %a) nounwind uwtable {
+define void @atomic64_xor_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_xor_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] acquire acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] acquire acquire, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2838,18 +2838,18 @@ define void @atomic64_xor_acquire(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i64* %a, i64 0 acquire, !pcsections !0
+ atomicrmw xor ptr %a, i64 0 acquire, !pcsections !0
ret void
}
-define void @atomic64_nand_acquire(i64* %a) nounwind uwtable {
+define void @atomic64_nand_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_nand_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 -1 acquire acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 -1 acquire acquire, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2857,18 +2857,18 @@ define void @atomic64_nand_acquire(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i64* %a, i64 0 acquire, !pcsections !0
+ atomicrmw nand ptr %a, i64 0 acquire, !pcsections !0
ret void
}
-define void @atomic64_xchg_release(i64* %a) nounwind uwtable {
+define void @atomic64_xchg_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_xchg_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 release monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 release monotonic, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2876,18 +2876,18 @@ define void @atomic64_xchg_release(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i64* %a, i64 0 release, !pcsections !0
+ atomicrmw xchg ptr %a, i64 0 release, !pcsections !0
ret void
}
-define void @atomic64_add_release(i64* %a) nounwind uwtable {
+define void @atomic64_add_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_add_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] release monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] release monotonic, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2895,18 +2895,18 @@ define void @atomic64_add_release(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i64* %a, i64 0 release, !pcsections !0
+ atomicrmw add ptr %a, i64 0 release, !pcsections !0
ret void
}
-define void @atomic64_sub_release(i64* %a) nounwind uwtable {
+define void @atomic64_sub_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_sub_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] release monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] release monotonic, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2914,18 +2914,18 @@ define void @atomic64_sub_release(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i64* %a, i64 0 release, !pcsections !0
+ atomicrmw sub ptr %a, i64 0 release, !pcsections !0
ret void
}
-define void @atomic64_and_release(i64* %a) nounwind uwtable {
+define void @atomic64_and_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_and_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 release monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 release monotonic, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2933,18 +2933,18 @@ define void @atomic64_and_release(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i64* %a, i64 0 release, !pcsections !0
+ atomicrmw and ptr %a, i64 0 release, !pcsections !0
ret void
}
-define void @atomic64_or_release(i64* %a) nounwind uwtable {
+define void @atomic64_or_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_or_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] release monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] release monotonic, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2952,18 +2952,18 @@ define void @atomic64_or_release(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i64* %a, i64 0 release, !pcsections !0
+ atomicrmw or ptr %a, i64 0 release, !pcsections !0
ret void
}
-define void @atomic64_xor_release(i64* %a) nounwind uwtable {
+define void @atomic64_xor_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_xor_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] release monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] release monotonic, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2971,18 +2971,18 @@ define void @atomic64_xor_release(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i64* %a, i64 0 release, !pcsections !0
+ atomicrmw xor ptr %a, i64 0 release, !pcsections !0
ret void
}
-define void @atomic64_nand_release(i64* %a) nounwind uwtable {
+define void @atomic64_nand_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_nand_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 -1 release monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 -1 release monotonic, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -2990,18 +2990,18 @@ define void @atomic64_nand_release(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i64* %a, i64 0 release, !pcsections !0
+ atomicrmw nand ptr %a, i64 0 release, !pcsections !0
ret void
}
-define void @atomic64_xchg_acq_rel(i64* %a) nounwind uwtable {
+define void @atomic64_xchg_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_xchg_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 acq_rel acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 acq_rel acquire, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3009,18 +3009,18 @@ define void @atomic64_xchg_acq_rel(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i64* %a, i64 0 acq_rel, !pcsections !0
+ atomicrmw xchg ptr %a, i64 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic64_add_acq_rel(i64* %a) nounwind uwtable {
+define void @atomic64_add_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_add_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] acq_rel acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] acq_rel acquire, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3028,18 +3028,18 @@ define void @atomic64_add_acq_rel(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i64* %a, i64 0 acq_rel, !pcsections !0
+ atomicrmw add ptr %a, i64 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic64_sub_acq_rel(i64* %a) nounwind uwtable {
+define void @atomic64_sub_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_sub_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] acq_rel acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] acq_rel acquire, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3047,18 +3047,18 @@ define void @atomic64_sub_acq_rel(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i64* %a, i64 0 acq_rel, !pcsections !0
+ atomicrmw sub ptr %a, i64 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic64_and_acq_rel(i64* %a) nounwind uwtable {
+define void @atomic64_and_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_and_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 acq_rel acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 acq_rel acquire, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3066,18 +3066,18 @@ define void @atomic64_and_acq_rel(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i64* %a, i64 0 acq_rel, !pcsections !0
+ atomicrmw and ptr %a, i64 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic64_or_acq_rel(i64* %a) nounwind uwtable {
+define void @atomic64_or_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_or_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] acq_rel acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] acq_rel acquire, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3085,18 +3085,18 @@ define void @atomic64_or_acq_rel(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i64* %a, i64 0 acq_rel, !pcsections !0
+ atomicrmw or ptr %a, i64 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic64_xor_acq_rel(i64* %a) nounwind uwtable {
+define void @atomic64_xor_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_xor_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] acq_rel acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] acq_rel acquire, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3104,18 +3104,18 @@ define void @atomic64_xor_acq_rel(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i64* %a, i64 0 acq_rel, !pcsections !0
+ atomicrmw xor ptr %a, i64 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic64_nand_acq_rel(i64* %a) nounwind uwtable {
+define void @atomic64_nand_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_nand_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 -1 acq_rel acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 -1 acq_rel acquire, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3123,18 +3123,18 @@ define void @atomic64_nand_acq_rel(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i64* %a, i64 0 acq_rel, !pcsections !0
+ atomicrmw nand ptr %a, i64 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic64_xchg_seq_cst(i64* %a) nounwind uwtable {
+define void @atomic64_xchg_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_xchg_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 seq_cst seq_cst, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 seq_cst seq_cst, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3142,18 +3142,18 @@ define void @atomic64_xchg_seq_cst(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i64* %a, i64 0 seq_cst, !pcsections !0
+ atomicrmw xchg ptr %a, i64 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic64_add_seq_cst(i64* %a) nounwind uwtable {
+define void @atomic64_add_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_add_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] seq_cst seq_cst, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] seq_cst seq_cst, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3161,18 +3161,18 @@ define void @atomic64_add_seq_cst(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i64* %a, i64 0 seq_cst, !pcsections !0
+ atomicrmw add ptr %a, i64 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic64_sub_seq_cst(i64* %a) nounwind uwtable {
+define void @atomic64_sub_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_sub_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] seq_cst seq_cst, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] seq_cst seq_cst, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3180,18 +3180,18 @@ define void @atomic64_sub_seq_cst(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i64* %a, i64 0 seq_cst, !pcsections !0
+ atomicrmw sub ptr %a, i64 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic64_and_seq_cst(i64* %a) nounwind uwtable {
+define void @atomic64_and_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_and_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 seq_cst seq_cst, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 seq_cst seq_cst, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3199,18 +3199,18 @@ define void @atomic64_and_seq_cst(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i64* %a, i64 0 seq_cst, !pcsections !0
+ atomicrmw and ptr %a, i64 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic64_or_seq_cst(i64* %a) nounwind uwtable {
+define void @atomic64_or_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_or_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] seq_cst seq_cst, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] seq_cst seq_cst, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3218,18 +3218,18 @@ define void @atomic64_or_seq_cst(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i64* %a, i64 0 seq_cst, !pcsections !0
+ atomicrmw or ptr %a, i64 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic64_xor_seq_cst(i64* %a) nounwind uwtable {
+define void @atomic64_xor_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_xor_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] seq_cst seq_cst, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] seq_cst seq_cst, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3237,18 +3237,18 @@ define void @atomic64_xor_seq_cst(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i64* %a, i64 0 seq_cst, !pcsections !0
+ atomicrmw xor ptr %a, i64 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic64_nand_seq_cst(i64* %a) nounwind uwtable {
+define void @atomic64_nand_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_nand_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 -1 seq_cst seq_cst, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 -1 seq_cst seq_cst, align 8, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3256,160 +3256,159 @@ define void @atomic64_nand_seq_cst(i64* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i64* %a, i64 0 seq_cst, !pcsections !0
+ atomicrmw nand ptr %a, i64 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic64_cas_monotonic(i64* %a) nounwind uwtable {
+define void @atomic64_cas_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_cas_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i64* [[A:%.*]], i64 0, i64 1 monotonic monotonic, align 8, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 monotonic acquire, align 8, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 monotonic seq_cst, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i64 0, i64 1 monotonic monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 monotonic acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 monotonic seq_cst, align 8, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i64* %a, i64 0, i64 1 monotonic monotonic, !pcsections !0
- cmpxchg i64* %a, i64 0, i64 1 monotonic acquire, !pcsections !0
- cmpxchg i64* %a, i64 0, i64 1 monotonic seq_cst, !pcsections !0
+ cmpxchg ptr %a, i64 0, i64 1 monotonic monotonic, !pcsections !0
+ cmpxchg ptr %a, i64 0, i64 1 monotonic acquire, !pcsections !0
+ cmpxchg ptr %a, i64 0, i64 1 monotonic seq_cst, !pcsections !0
ret void
}
-define void @atomic64_cas_acquire(i64* %a) nounwind uwtable {
+define void @atomic64_cas_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_cas_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i64* [[A:%.*]], i64 0, i64 1 acquire monotonic, align 8, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 acquire acquire, align 8, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 acquire seq_cst, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i64 0, i64 1 acquire monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 acquire acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 acquire seq_cst, align 8, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i64* %a, i64 0, i64 1 acquire monotonic, !pcsections !0
- cmpxchg i64* %a, i64 0, i64 1 acquire acquire, !pcsections !0
- cmpxchg i64* %a, i64 0, i64 1 acquire seq_cst, !pcsections !0
+ cmpxchg ptr %a, i64 0, i64 1 acquire monotonic, !pcsections !0
+ cmpxchg ptr %a, i64 0, i64 1 acquire acquire, !pcsections !0
+ cmpxchg ptr %a, i64 0, i64 1 acquire seq_cst, !pcsections !0
ret void
}
-define void @atomic64_cas_release(i64* %a) nounwind uwtable {
+define void @atomic64_cas_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_cas_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i64* [[A:%.*]], i64 0, i64 1 release monotonic, align 8, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 release acquire, align 8, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 release seq_cst, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i64 0, i64 1 release monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 release acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 release seq_cst, align 8, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i64* %a, i64 0, i64 1 release monotonic, !pcsections !0
- cmpxchg i64* %a, i64 0, i64 1 release acquire, !pcsections !0
- cmpxchg i64* %a, i64 0, i64 1 release seq_cst, !pcsections !0
+ cmpxchg ptr %a, i64 0, i64 1 release monotonic, !pcsections !0
+ cmpxchg ptr %a, i64 0, i64 1 release acquire, !pcsections !0
+ cmpxchg ptr %a, i64 0, i64 1 release seq_cst, !pcsections !0
ret void
}
-define void @atomic64_cas_acq_rel(i64* %a) nounwind uwtable {
+define void @atomic64_cas_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_cas_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i64* [[A:%.*]], i64 0, i64 1 acq_rel monotonic, align 8, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 acq_rel acquire, align 8, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 acq_rel seq_cst, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i64 0, i64 1 acq_rel monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 acq_rel acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 acq_rel seq_cst, align 8, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i64* %a, i64 0, i64 1 acq_rel monotonic, !pcsections !0
- cmpxchg i64* %a, i64 0, i64 1 acq_rel acquire, !pcsections !0
- cmpxchg i64* %a, i64 0, i64 1 acq_rel seq_cst, !pcsections !0
+ cmpxchg ptr %a, i64 0, i64 1 acq_rel monotonic, !pcsections !0
+ cmpxchg ptr %a, i64 0, i64 1 acq_rel acquire, !pcsections !0
+ cmpxchg ptr %a, i64 0, i64 1 acq_rel seq_cst, !pcsections !0
ret void
}
-define void @atomic64_cas_seq_cst(i64* %a) nounwind uwtable {
+define void @atomic64_cas_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic64_cas_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i64* [[A:%.*]], i64 0, i64 1 seq_cst monotonic, align 8, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 seq_cst acquire, align 8, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 seq_cst seq_cst, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i64 0, i64 1 seq_cst monotonic, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 seq_cst acquire, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 seq_cst seq_cst, align 8, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i64* %a, i64 0, i64 1 seq_cst monotonic, !pcsections !0
- cmpxchg i64* %a, i64 0, i64 1 seq_cst acquire, !pcsections !0
- cmpxchg i64* %a, i64 0, i64 1 seq_cst seq_cst, !pcsections !0
+ cmpxchg ptr %a, i64 0, i64 1 seq_cst monotonic, !pcsections !0
+ cmpxchg ptr %a, i64 0, i64 1 seq_cst acquire, !pcsections !0
+ cmpxchg ptr %a, i64 0, i64 1 seq_cst seq_cst, !pcsections !0
ret void
}
-define void @atomic64_cas_seq_cst_ptr_ty(i8** %a, i8* %v1, i8* %v2) nounwind uwtable {
+define void @atomic64_cas_seq_cst_ptr_ty(ptr %a, ptr %v1, ptr %v2) nounwind uwtable {
; CHECK-LABEL: @atomic64_cas_seq_cst_ptr_ty(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8** [[A:%.*]] to i64*, !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8* [[V1:%.*]] to i64, !pcsections !0
-; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint i8* [[V2:%.*]] to i64, !pcsections !0
-; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg i64* [[TMP0]], i64 [[TMP1]], i64 [[TMP2]] seq_cst seq_cst, align 8, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[V1:%.*]] to i64, !pcsections !0
+; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[V2:%.*]] to i64, !pcsections !0
+; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg ptr [[A:%.*]], i64 [[TMP1]], i64 [[TMP2]] seq_cst seq_cst, align 8, !pcsections !0
; CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i64, i1 } [[TMP3]], 0, !pcsections !0
; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i64, i1 } [[TMP3]], 1, !pcsections !0
-; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP4]] to i8*, !pcsections !0
-; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8*, i1 } poison, i8* [[TMP6]], 0, !pcsections !0
-; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { i8*, i1 } [[TMP7]], i1 [[TMP5]], 1, !pcsections !0
+; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP4]] to ptr, !pcsections !0
+; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { ptr, i1 } poison, ptr [[TMP6]], 0, !pcsections !0
+; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { ptr, i1 } [[TMP7]], i1 [[TMP5]], 1, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i8** %a, i8* %v1, i8* %v2 seq_cst seq_cst, !pcsections !0
+ cmpxchg ptr %a, ptr %v1, ptr %v2 seq_cst seq_cst, !pcsections !0
ret void
}
-define i128 @atomic128_load_unordered(i128* %a) nounwind uwtable {
+define i128 @atomic128_load_unordered(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_load_unordered(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i128* [[A:%.*]], i128 0, i128 0 monotonic monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i128 0, i128 0 monotonic monotonic, align 16, !pcsections !0
; CHECK-NEXT: [[LOADED:%.*]] = extractvalue { i128, i1 } [[TMP0]], 0, !pcsections !0
; CHECK-NEXT: ret i128 [[LOADED]]
;
entry:
- %0 = load atomic i128, i128* %a unordered, align 16, !pcsections !0
+ %0 = load atomic i128, ptr %a unordered, align 16, !pcsections !0
ret i128 %0
}
-define i128 @atomic128_load_monotonic(i128* %a) nounwind uwtable {
+define i128 @atomic128_load_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_load_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i128* [[A:%.*]], i128 0, i128 0 monotonic monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i128 0, i128 0 monotonic monotonic, align 16, !pcsections !0
; CHECK-NEXT: [[LOADED:%.*]] = extractvalue { i128, i1 } [[TMP0]], 0, !pcsections !0
; CHECK-NEXT: ret i128 [[LOADED]]
;
entry:
- %0 = load atomic i128, i128* %a monotonic, align 16, !pcsections !0
+ %0 = load atomic i128, ptr %a monotonic, align 16, !pcsections !0
ret i128 %0
}
-define i128 @atomic128_load_acquire(i128* %a) nounwind uwtable {
+define i128 @atomic128_load_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_load_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i128* [[A:%.*]], i128 0, i128 0 acquire acquire, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i128 0, i128 0 acquire acquire, align 16, !pcsections !0
; CHECK-NEXT: [[LOADED:%.*]] = extractvalue { i128, i1 } [[TMP0]], 0, !pcsections !0
; CHECK-NEXT: ret i128 [[LOADED]]
;
entry:
- %0 = load atomic i128, i128* %a acquire, align 16, !pcsections !0
+ %0 = load atomic i128, ptr %a acquire, align 16, !pcsections !0
ret i128 %0
}
-define i128 @atomic128_load_seq_cst(i128* %a) nounwind uwtable {
+define i128 @atomic128_load_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_load_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i128* [[A:%.*]], i128 0, i128 0 seq_cst seq_cst, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i128 0, i128 0 seq_cst seq_cst, align 16, !pcsections !0
; CHECK-NEXT: [[LOADED:%.*]] = extractvalue { i128, i1 } [[TMP0]], 0, !pcsections !0
; CHECK-NEXT: ret i128 [[LOADED]]
;
entry:
- %0 = load atomic i128, i128* %a seq_cst, align 16, !pcsections !0
+ %0 = load atomic i128, ptr %a seq_cst, align 16, !pcsections !0
ret i128 %0
}
-define void @atomic128_store_unordered(i128* %a) nounwind uwtable {
+define void @atomic128_store_unordered(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_store_unordered(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 monotonic monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 monotonic monotonic, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3417,18 +3416,18 @@ define void @atomic128_store_unordered(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- store atomic i128 0, i128* %a unordered, align 16, !pcsections !0
+ store atomic i128 0, ptr %a unordered, align 16, !pcsections !0
ret void
}
-define void @atomic128_store_monotonic(i128* %a) nounwind uwtable {
+define void @atomic128_store_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_store_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 monotonic monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 monotonic monotonic, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3436,18 +3435,18 @@ define void @atomic128_store_monotonic(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- store atomic i128 0, i128* %a monotonic, align 16, !pcsections !0
+ store atomic i128 0, ptr %a monotonic, align 16, !pcsections !0
ret void
}
-define void @atomic128_store_release(i128* %a) nounwind uwtable {
+define void @atomic128_store_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_store_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 release monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 release monotonic, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3455,18 +3454,18 @@ define void @atomic128_store_release(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- store atomic i128 0, i128* %a release, align 16, !pcsections !0
+ store atomic i128 0, ptr %a release, align 16, !pcsections !0
ret void
}
-define void @atomic128_store_seq_cst(i128* %a) nounwind uwtable {
+define void @atomic128_store_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_store_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 seq_cst seq_cst, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 seq_cst seq_cst, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3474,18 +3473,18 @@ define void @atomic128_store_seq_cst(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- store atomic i128 0, i128* %a seq_cst, align 16, !pcsections !0
+ store atomic i128 0, ptr %a seq_cst, align 16, !pcsections !0
ret void
}
-define void @atomic128_xchg_monotonic(i128* %a) nounwind uwtable {
+define void @atomic128_xchg_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_xchg_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 monotonic monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 monotonic monotonic, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3493,18 +3492,18 @@ define void @atomic128_xchg_monotonic(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i128* %a, i128 0 monotonic, !pcsections !0
+ atomicrmw xchg ptr %a, i128 0 monotonic, !pcsections !0
ret void
}
-define void @atomic128_add_monotonic(i128* %a) nounwind uwtable {
+define void @atomic128_add_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_add_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] monotonic monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] monotonic monotonic, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3512,18 +3511,18 @@ define void @atomic128_add_monotonic(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i128* %a, i128 0 monotonic, !pcsections !0
+ atomicrmw add ptr %a, i128 0 monotonic, !pcsections !0
ret void
}
-define void @atomic128_sub_monotonic(i128* %a) nounwind uwtable {
+define void @atomic128_sub_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_sub_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] monotonic monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] monotonic monotonic, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3531,18 +3530,18 @@ define void @atomic128_sub_monotonic(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i128* %a, i128 0 monotonic, !pcsections !0
+ atomicrmw sub ptr %a, i128 0 monotonic, !pcsections !0
ret void
}
-define void @atomic128_and_monotonic(i128* %a) nounwind uwtable {
+define void @atomic128_and_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_and_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 monotonic monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 monotonic monotonic, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3550,18 +3549,18 @@ define void @atomic128_and_monotonic(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i128* %a, i128 0 monotonic, !pcsections !0
+ atomicrmw and ptr %a, i128 0 monotonic, !pcsections !0
ret void
}
-define void @atomic128_or_monotonic(i128* %a) nounwind uwtable {
+define void @atomic128_or_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_or_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] monotonic monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] monotonic monotonic, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3569,18 +3568,18 @@ define void @atomic128_or_monotonic(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i128* %a, i128 0 monotonic, !pcsections !0
+ atomicrmw or ptr %a, i128 0 monotonic, !pcsections !0
ret void
}
-define void @atomic128_xor_monotonic(i128* %a) nounwind uwtable {
+define void @atomic128_xor_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_xor_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] monotonic monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] monotonic monotonic, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3588,18 +3587,18 @@ define void @atomic128_xor_monotonic(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i128* %a, i128 0 monotonic, !pcsections !0
+ atomicrmw xor ptr %a, i128 0 monotonic, !pcsections !0
ret void
}
-define void @atomic128_nand_monotonic(i128* %a) nounwind uwtable {
+define void @atomic128_nand_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_nand_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 -1 monotonic monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 -1 monotonic monotonic, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3607,18 +3606,18 @@ define void @atomic128_nand_monotonic(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i128* %a, i128 0 monotonic, !pcsections !0
+ atomicrmw nand ptr %a, i128 0 monotonic, !pcsections !0
ret void
}
-define void @atomic128_xchg_acquire(i128* %a) nounwind uwtable {
+define void @atomic128_xchg_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_xchg_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 acquire acquire, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 acquire acquire, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3626,18 +3625,18 @@ define void @atomic128_xchg_acquire(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i128* %a, i128 0 acquire, !pcsections !0
+ atomicrmw xchg ptr %a, i128 0 acquire, !pcsections !0
ret void
}
-define void @atomic128_add_acquire(i128* %a) nounwind uwtable {
+define void @atomic128_add_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_add_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] acquire acquire, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] acquire acquire, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3645,18 +3644,18 @@ define void @atomic128_add_acquire(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i128* %a, i128 0 acquire, !pcsections !0
+ atomicrmw add ptr %a, i128 0 acquire, !pcsections !0
ret void
}
-define void @atomic128_sub_acquire(i128* %a) nounwind uwtable {
+define void @atomic128_sub_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_sub_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] acquire acquire, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] acquire acquire, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3664,18 +3663,18 @@ define void @atomic128_sub_acquire(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i128* %a, i128 0 acquire, !pcsections !0
+ atomicrmw sub ptr %a, i128 0 acquire, !pcsections !0
ret void
}
-define void @atomic128_and_acquire(i128* %a) nounwind uwtable {
+define void @atomic128_and_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_and_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 acquire acquire, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 acquire acquire, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3683,18 +3682,18 @@ define void @atomic128_and_acquire(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i128* %a, i128 0 acquire, !pcsections !0
+ atomicrmw and ptr %a, i128 0 acquire, !pcsections !0
ret void
}
-define void @atomic128_or_acquire(i128* %a) nounwind uwtable {
+define void @atomic128_or_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_or_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] acquire acquire, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] acquire acquire, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3702,18 +3701,18 @@ define void @atomic128_or_acquire(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i128* %a, i128 0 acquire, !pcsections !0
+ atomicrmw or ptr %a, i128 0 acquire, !pcsections !0
ret void
}
-define void @atomic128_xor_acquire(i128* %a) nounwind uwtable {
+define void @atomic128_xor_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_xor_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] acquire acquire, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] acquire acquire, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3721,18 +3720,18 @@ define void @atomic128_xor_acquire(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i128* %a, i128 0 acquire, !pcsections !0
+ atomicrmw xor ptr %a, i128 0 acquire, !pcsections !0
ret void
}
-define void @atomic128_nand_acquire(i128* %a) nounwind uwtable {
+define void @atomic128_nand_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_nand_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 -1 acquire acquire, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 -1 acquire acquire, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3740,18 +3739,18 @@ define void @atomic128_nand_acquire(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i128* %a, i128 0 acquire, !pcsections !0
+ atomicrmw nand ptr %a, i128 0 acquire, !pcsections !0
ret void
}
-define void @atomic128_xchg_release(i128* %a) nounwind uwtable {
+define void @atomic128_xchg_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_xchg_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 release monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 release monotonic, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3759,18 +3758,18 @@ define void @atomic128_xchg_release(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i128* %a, i128 0 release, !pcsections !0
+ atomicrmw xchg ptr %a, i128 0 release, !pcsections !0
ret void
}
-define void @atomic128_add_release(i128* %a) nounwind uwtable {
+define void @atomic128_add_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_add_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] release monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] release monotonic, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3778,18 +3777,18 @@ define void @atomic128_add_release(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i128* %a, i128 0 release, !pcsections !0
+ atomicrmw add ptr %a, i128 0 release, !pcsections !0
ret void
}
-define void @atomic128_sub_release(i128* %a) nounwind uwtable {
+define void @atomic128_sub_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_sub_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] release monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] release monotonic, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3797,18 +3796,18 @@ define void @atomic128_sub_release(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i128* %a, i128 0 release, !pcsections !0
+ atomicrmw sub ptr %a, i128 0 release, !pcsections !0
ret void
}
-define void @atomic128_and_release(i128* %a) nounwind uwtable {
+define void @atomic128_and_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_and_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 release monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 release monotonic, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3816,18 +3815,18 @@ define void @atomic128_and_release(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i128* %a, i128 0 release, !pcsections !0
+ atomicrmw and ptr %a, i128 0 release, !pcsections !0
ret void
}
-define void @atomic128_or_release(i128* %a) nounwind uwtable {
+define void @atomic128_or_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_or_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] release monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] release monotonic, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3835,18 +3834,18 @@ define void @atomic128_or_release(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i128* %a, i128 0 release, !pcsections !0
+ atomicrmw or ptr %a, i128 0 release, !pcsections !0
ret void
}
-define void @atomic128_xor_release(i128* %a) nounwind uwtable {
+define void @atomic128_xor_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_xor_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] release monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] release monotonic, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3854,18 +3853,18 @@ define void @atomic128_xor_release(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i128* %a, i128 0 release, !pcsections !0
+ atomicrmw xor ptr %a, i128 0 release, !pcsections !0
ret void
}
-define void @atomic128_nand_release(i128* %a) nounwind uwtable {
+define void @atomic128_nand_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_nand_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 -1 release monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 -1 release monotonic, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3873,18 +3872,18 @@ define void @atomic128_nand_release(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i128* %a, i128 0 release, !pcsections !0
+ atomicrmw nand ptr %a, i128 0 release, !pcsections !0
ret void
}
-define void @atomic128_xchg_acq_rel(i128* %a) nounwind uwtable {
+define void @atomic128_xchg_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_xchg_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 acq_rel acquire, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 acq_rel acquire, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3892,18 +3891,18 @@ define void @atomic128_xchg_acq_rel(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i128* %a, i128 0 acq_rel, !pcsections !0
+ atomicrmw xchg ptr %a, i128 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic128_add_acq_rel(i128* %a) nounwind uwtable {
+define void @atomic128_add_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_add_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] acq_rel acquire, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] acq_rel acquire, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3911,18 +3910,18 @@ define void @atomic128_add_acq_rel(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i128* %a, i128 0 acq_rel, !pcsections !0
+ atomicrmw add ptr %a, i128 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic128_sub_acq_rel(i128* %a) nounwind uwtable {
+define void @atomic128_sub_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_sub_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] acq_rel acquire, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] acq_rel acquire, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3930,18 +3929,18 @@ define void @atomic128_sub_acq_rel(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i128* %a, i128 0 acq_rel, !pcsections !0
+ atomicrmw sub ptr %a, i128 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic128_and_acq_rel(i128* %a) nounwind uwtable {
+define void @atomic128_and_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_and_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 acq_rel acquire, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 acq_rel acquire, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3949,18 +3948,18 @@ define void @atomic128_and_acq_rel(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i128* %a, i128 0 acq_rel, !pcsections !0
+ atomicrmw and ptr %a, i128 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic128_or_acq_rel(i128* %a) nounwind uwtable {
+define void @atomic128_or_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_or_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] acq_rel acquire, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] acq_rel acquire, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3968,18 +3967,18 @@ define void @atomic128_or_acq_rel(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i128* %a, i128 0 acq_rel, !pcsections !0
+ atomicrmw or ptr %a, i128 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic128_xor_acq_rel(i128* %a) nounwind uwtable {
+define void @atomic128_xor_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_xor_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] acq_rel acquire, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] acq_rel acquire, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -3987,18 +3986,18 @@ define void @atomic128_xor_acq_rel(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i128* %a, i128 0 acq_rel, !pcsections !0
+ atomicrmw xor ptr %a, i128 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic128_nand_acq_rel(i128* %a) nounwind uwtable {
+define void @atomic128_nand_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_nand_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 -1 acq_rel acquire, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 -1 acq_rel acquire, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -4006,18 +4005,18 @@ define void @atomic128_nand_acq_rel(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i128* %a, i128 0 acq_rel, !pcsections !0
+ atomicrmw nand ptr %a, i128 0 acq_rel, !pcsections !0
ret void
}
-define void @atomic128_xchg_seq_cst(i128* %a) nounwind uwtable {
+define void @atomic128_xchg_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_xchg_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 seq_cst seq_cst, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 seq_cst seq_cst, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -4025,18 +4024,18 @@ define void @atomic128_xchg_seq_cst(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xchg i128* %a, i128 0 seq_cst, !pcsections !0
+ atomicrmw xchg ptr %a, i128 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic128_add_seq_cst(i128* %a) nounwind uwtable {
+define void @atomic128_add_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_add_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] seq_cst seq_cst, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] seq_cst seq_cst, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -4044,18 +4043,18 @@ define void @atomic128_add_seq_cst(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw add i128* %a, i128 0 seq_cst, !pcsections !0
+ atomicrmw add ptr %a, i128 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic128_sub_seq_cst(i128* %a) nounwind uwtable {
+define void @atomic128_sub_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_sub_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] seq_cst seq_cst, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] seq_cst seq_cst, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -4063,18 +4062,18 @@ define void @atomic128_sub_seq_cst(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw sub i128* %a, i128 0 seq_cst, !pcsections !0
+ atomicrmw sub ptr %a, i128 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic128_and_seq_cst(i128* %a) nounwind uwtable {
+define void @atomic128_and_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_and_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 seq_cst seq_cst, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 seq_cst seq_cst, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -4082,18 +4081,18 @@ define void @atomic128_and_seq_cst(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw and i128* %a, i128 0 seq_cst, !pcsections !0
+ atomicrmw and ptr %a, i128 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic128_or_seq_cst(i128* %a) nounwind uwtable {
+define void @atomic128_or_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_or_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] seq_cst seq_cst, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] seq_cst seq_cst, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -4101,18 +4100,18 @@ define void @atomic128_or_seq_cst(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw or i128* %a, i128 0 seq_cst, !pcsections !0
+ atomicrmw or ptr %a, i128 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic128_xor_seq_cst(i128* %a) nounwind uwtable {
+define void @atomic128_xor_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_xor_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] seq_cst seq_cst, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] seq_cst seq_cst, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -4120,18 +4119,18 @@ define void @atomic128_xor_seq_cst(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw xor i128* %a, i128 0 seq_cst, !pcsections !0
+ atomicrmw xor ptr %a, i128 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic128_nand_seq_cst(i128* %a) nounwind uwtable {
+define void @atomic128_nand_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_nand_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0
-; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 -1 seq_cst seq_cst, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 -1 seq_cst seq_cst, align 16, !pcsections !0
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0
@@ -4139,62 +4138,62 @@ define void @atomic128_nand_seq_cst(i128* %a) nounwind uwtable {
; CHECK-NEXT: ret void
;
entry:
- atomicrmw nand i128* %a, i128 0 seq_cst, !pcsections !0
+ atomicrmw nand ptr %a, i128 0 seq_cst, !pcsections !0
ret void
}
-define void @atomic128_cas_monotonic(i128* %a) nounwind uwtable {
+define void @atomic128_cas_monotonic(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_cas_monotonic(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i128* [[A:%.*]], i128 0, i128 1 monotonic monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i128 0, i128 1 monotonic monotonic, align 16, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i128* %a, i128 0, i128 1 monotonic monotonic, !pcsections !0
+ cmpxchg ptr %a, i128 0, i128 1 monotonic monotonic, !pcsections !0
ret void
}
-define void @atomic128_cas_acquire(i128* %a) nounwind uwtable {
+define void @atomic128_cas_acquire(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_cas_acquire(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i128* [[A:%.*]], i128 0, i128 1 acquire acquire, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i128 0, i128 1 acquire acquire, align 16, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i128* %a, i128 0, i128 1 acquire acquire, !pcsections !0
+ cmpxchg ptr %a, i128 0, i128 1 acquire acquire, !pcsections !0
ret void
}
-define void @atomic128_cas_release(i128* %a) nounwind uwtable {
+define void @atomic128_cas_release(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_cas_release(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i128* [[A:%.*]], i128 0, i128 1 release monotonic, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i128 0, i128 1 release monotonic, align 16, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i128* %a, i128 0, i128 1 release monotonic, !pcsections !0
+ cmpxchg ptr %a, i128 0, i128 1 release monotonic, !pcsections !0
ret void
}
-define void @atomic128_cas_acq_rel(i128* %a) nounwind uwtable {
+define void @atomic128_cas_acq_rel(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_cas_acq_rel(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i128* [[A:%.*]], i128 0, i128 1 acq_rel acquire, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i128 0, i128 1 acq_rel acquire, align 16, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i128* %a, i128 0, i128 1 acq_rel acquire, !pcsections !0
+ cmpxchg ptr %a, i128 0, i128 1 acq_rel acquire, !pcsections !0
ret void
}
-define void @atomic128_cas_seq_cst(i128* %a) nounwind uwtable {
+define void @atomic128_cas_seq_cst(ptr %a) nounwind uwtable {
; CHECK-LABEL: @atomic128_cas_seq_cst(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i128* [[A:%.*]], i128 0, i128 1 seq_cst seq_cst, align 16, !pcsections !0
+; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i128 0, i128 1 seq_cst seq_cst, align 16, !pcsections !0
; CHECK-NEXT: ret void
;
entry:
- cmpxchg i128* %a, i128 0, i128 1 seq_cst seq_cst, !pcsections !0
+ cmpxchg ptr %a, i128 0, i128 1 seq_cst seq_cst, !pcsections !0
ret void
}
diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
index 91e132f8faeba..ac89c7f1323a9 100644
--- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
+++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll
@@ -4,25 +4,24 @@
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
-define i16 @test_atomicrmw_xchg_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
+define i16 @test_atomicrmw_xchg_i16_global(ptr addrspace(1) %ptr, i16 %value) {
; CHECK-LABEL: @test_atomicrmw_xchg_i16_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[VALOPERAND_SHIFTED]]
-; CHECK-NEXT: [[TMP7:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP6]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP7:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP6]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -31,21 +30,20 @@ define i16 @test_atomicrmw_xchg_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16
; CHECK-NEXT: ret i16 [[EXTRACTED]]
;
- %res = atomicrmw xchg i16 addrspace(1)* %ptr, i16 %value seq_cst
+ %res = atomicrmw xchg ptr addrspace(1) %ptr, i16 %value seq_cst
ret i16 %res
}
-define i16 @test_atomicrmw_xchg_i16_global_align4(i16 addrspace(1)* %ptr, i16 %value) {
+define i16 @test_atomicrmw_xchg_i16_global_align4(ptr addrspace(1) %ptr, i16 %value) {
; CHECK-LABEL: @test_atomicrmw_xchg_i16_global_align4(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = bitcast i16 addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[VALUE:%.*]] to i32
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[LOADED]], -65536
; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP1]]
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP4]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[TMP4]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -53,23 +51,22 @@ define i16 @test_atomicrmw_xchg_i16_global_align4(i16 addrspace(1)* %ptr, i16 %v
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[NEWLOADED]] to i16
; CHECK-NEXT: ret i16 [[EXTRACTED]]
;
- %res = atomicrmw xchg i16 addrspace(1)* %ptr, i16 %value seq_cst, align 4
+ %res = atomicrmw xchg ptr addrspace(1) %ptr, i16 %value seq_cst, align 4
ret i16 %res
}
-define i16 @test_atomicrmw_add_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
+define i16 @test_atomicrmw_add_i16_global(ptr addrspace(1) %ptr, i16 %value) {
; CHECK-LABEL: @test_atomicrmw_add_i16_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -77,7 +74,7 @@ define i16 @test_atomicrmw_add_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[NEW]], [[MASK]]
; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP5]]
-; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP8]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -86,15 +83,14 @@ define i16 @test_atomicrmw_add_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16
; CHECK-NEXT: ret i16 [[EXTRACTED]]
;
- %res = atomicrmw add i16 addrspace(1)* %ptr, i16 %value seq_cst
+ %res = atomicrmw add ptr addrspace(1) %ptr, i16 %value seq_cst
ret i16 %res
}
-define i16 @test_atomicrmw_add_i16_global_align4(i16 addrspace(1)* %ptr, i16 %value) {
+define i16 @test_atomicrmw_add_i16_global_align4(ptr addrspace(1) %ptr, i16 %value) {
; CHECK-LABEL: @test_atomicrmw_add_i16_global_align4(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = bitcast i16 addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[VALUE:%.*]] to i32
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -102,7 +98,7 @@ define i16 @test_atomicrmw_add_i16_global_align4(i16 addrspace(1)* %ptr, i16 %va
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[NEW]], 65535
; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[LOADED]], -65536
; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP5]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[TMP5]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -110,23 +106,22 @@ define i16 @test_atomicrmw_add_i16_global_align4(i16 addrspace(1)* %ptr, i16 %va
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[NEWLOADED]] to i16
; CHECK-NEXT: ret i16 [[EXTRACTED]]
;
- %res = atomicrmw add i16 addrspace(1)* %ptr, i16 %value seq_cst, align 4
+ %res = atomicrmw add ptr addrspace(1) %ptr, i16 %value seq_cst, align 4
ret i16 %res
}
-define i16 @test_atomicrmw_sub_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
+define i16 @test_atomicrmw_sub_i16_global(ptr addrspace(1) %ptr, i16 %value) {
; CHECK-LABEL: @test_atomicrmw_sub_i16_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -134,7 +129,7 @@ define i16 @test_atomicrmw_sub_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[NEW]], [[MASK]]
; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP5]]
-; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP8]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -143,45 +138,43 @@ define i16 @test_atomicrmw_sub_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16
; CHECK-NEXT: ret i16 [[EXTRACTED]]
;
- %res = atomicrmw sub i16 addrspace(1)* %ptr, i16 %value seq_cst
+ %res = atomicrmw sub ptr addrspace(1) %ptr, i16 %value seq_cst
ret i16 %res
}
-define i16 @test_atomicrmw_and_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
+define i16 @test_atomicrmw_and_i16_global(ptr addrspace(1) %ptr, i16 %value) {
; CHECK-LABEL: @test_atomicrmw_and_i16_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[INV_MASK]], [[VALOPERAND_SHIFTED]]
-; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw and i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[ANDOPERAND]] seq_cst, align 4
+; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw and ptr addrspace(1) [[ALIGNEDADDR]], i32 [[ANDOPERAND]] seq_cst, align 4
; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]]
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16
; CHECK-NEXT: ret i16 [[EXTRACTED]]
;
- %res = atomicrmw and i16 addrspace(1)* %ptr, i16 %value seq_cst
+ %res = atomicrmw and ptr addrspace(1) %ptr, i16 %value seq_cst
ret i16 %res
}
-define i16 @test_atomicrmw_nand_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
+define i16 @test_atomicrmw_nand_i16_global(ptr addrspace(1) %ptr, i16 %value) {
; CHECK-LABEL: @test_atomicrmw_nand_i16_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -190,7 +183,7 @@ define i16 @test_atomicrmw_nand_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[NEW]], [[MASK]]
; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP8]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP9:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP8]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP9]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP9]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -199,63 +192,60 @@ define i16 @test_atomicrmw_nand_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16
; CHECK-NEXT: ret i16 [[EXTRACTED]]
;
- %res = atomicrmw nand i16 addrspace(1)* %ptr, i16 %value seq_cst
+ %res = atomicrmw nand ptr addrspace(1) %ptr, i16 %value seq_cst
ret i16 %res
}
-define i16 @test_atomicrmw_or_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
+define i16 @test_atomicrmw_or_i16_global(ptr addrspace(1) %ptr, i16 %value) {
; CHECK-LABEL: @test_atomicrmw_or_i16_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw or i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[VALOPERAND_SHIFTED]] seq_cst, align 4
+; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw or ptr addrspace(1) [[ALIGNEDADDR]], i32 [[VALOPERAND_SHIFTED]] seq_cst, align 4
; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]]
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16
; CHECK-NEXT: ret i16 [[EXTRACTED]]
;
- %res = atomicrmw or i16 addrspace(1)* %ptr, i16 %value seq_cst
+ %res = atomicrmw or ptr addrspace(1) %ptr, i16 %value seq_cst
ret i16 %res
}
-define i16 @test_atomicrmw_xor_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
+define i16 @test_atomicrmw_xor_i16_global(ptr addrspace(1) %ptr, i16 %value) {
; CHECK-LABEL: @test_atomicrmw_xor_i16_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw xor i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[VALOPERAND_SHIFTED]] seq_cst, align 4
+; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw xor ptr addrspace(1) [[ALIGNEDADDR]], i32 [[VALOPERAND_SHIFTED]] seq_cst, align 4
; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]]
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16
; CHECK-NEXT: ret i16 [[EXTRACTED]]
;
- %res = atomicrmw xor i16 addrspace(1)* %ptr, i16 %value seq_cst
+ %res = atomicrmw xor ptr addrspace(1) %ptr, i16 %value seq_cst
ret i16 %res
}
-define i16 @test_atomicrmw_max_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
+define i16 @test_atomicrmw_max_i16_global(ptr addrspace(1) %ptr, i16 %value) {
; CHECK-LABEL: @test_atomicrmw_max_i16_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -267,7 +257,7 @@ define i16 @test_atomicrmw_max_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -276,21 +266,20 @@ define i16 @test_atomicrmw_max_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i16
; CHECK-NEXT: ret i16 [[EXTRACTED4]]
;
- %res = atomicrmw max i16 addrspace(1)* %ptr, i16 %value seq_cst
+ %res = atomicrmw max ptr addrspace(1) %ptr, i16 %value seq_cst
ret i16 %res
}
-define i16 @test_atomicrmw_min_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
+define i16 @test_atomicrmw_min_i16_global(ptr addrspace(1) %ptr, i16 %value) {
; CHECK-LABEL: @test_atomicrmw_min_i16_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -302,7 +291,7 @@ define i16 @test_atomicrmw_min_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -311,21 +300,20 @@ define i16 @test_atomicrmw_min_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i16
; CHECK-NEXT: ret i16 [[EXTRACTED4]]
;
- %res = atomicrmw min i16 addrspace(1)* %ptr, i16 %value seq_cst
+ %res = atomicrmw min ptr addrspace(1) %ptr, i16 %value seq_cst
ret i16 %res
}
-define i16 @test_atomicrmw_umax_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
+define i16 @test_atomicrmw_umax_i16_global(ptr addrspace(1) %ptr, i16 %value) {
; CHECK-LABEL: @test_atomicrmw_umax_i16_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -337,7 +325,7 @@ define i16 @test_atomicrmw_umax_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -346,21 +334,20 @@ define i16 @test_atomicrmw_umax_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i16
; CHECK-NEXT: ret i16 [[EXTRACTED4]]
;
- %res = atomicrmw umax i16 addrspace(1)* %ptr, i16 %value seq_cst
+ %res = atomicrmw umax ptr addrspace(1) %ptr, i16 %value seq_cst
ret i16 %res
}
-define i16 @test_atomicrmw_umin_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
+define i16 @test_atomicrmw_umin_i16_global(ptr addrspace(1) %ptr, i16 %value) {
; CHECK-LABEL: @test_atomicrmw_umin_i16_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -372,7 +359,7 @@ define i16 @test_atomicrmw_umin_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -381,33 +368,32 @@ define i16 @test_atomicrmw_umin_i16_global(i16 addrspace(1)* %ptr, i16 %value) {
; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i16
; CHECK-NEXT: ret i16 [[EXTRACTED4]]
;
- %res = atomicrmw umin i16 addrspace(1)* %ptr, i16 %value seq_cst
+ %res = atomicrmw umin ptr addrspace(1) %ptr, i16 %value seq_cst
ret i16 %res
}
-define i16 @test_cmpxchg_i16_global(i16 addrspace(1)* %out, i16 %in, i16 %old) {
+define i16 @test_cmpxchg_i16_global(ptr addrspace(1) %out, i16 %in, i16 %old) {
; CHECK-LABEL: @test_cmpxchg_i16_global(
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr i16, i16 addrspace(1)* [[OUT:%.*]], i64 4
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[GEP]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[GEP]] to i64
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr i16, ptr addrspace(1) [[OUT:%.*]], i64 4
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[GEP]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[GEP]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[IN:%.*]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
; CHECK-NEXT: [[TMP5:%.*]] = zext i16 [[OLD:%.*]] to i32
; CHECK-NEXT: [[TMP6:%.*]] = shl i32 [[TMP5]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], [[INV_MASK]]
; CHECK-NEXT: br label [[PARTWORD_CMPXCHG_LOOP:%.*]]
; CHECK: partword.cmpxchg.loop:
; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ [[TMP8]], [[TMP0:%.*]] ], [ [[TMP15:%.*]], [[PARTWORD_CMPXCHG_FAILURE:%.*]] ]
; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP4]]
; CHECK-NEXT: [[TMP11:%.*]] = or i32 [[TMP9]], [[TMP6]]
-; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[TMP11]], i32 [[TMP10]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[TMP11]], i32 [[TMP10]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[TMP13:%.*]] = extractvalue { i32, i1 } [[TMP12]], 0
; CHECK-NEXT: [[TMP14:%.*]] = extractvalue { i32, i1 } [[TMP12]], 1
; CHECK-NEXT: br i1 [[TMP14]], label [[PARTWORD_CMPXCHG_END:%.*]], label [[PARTWORD_CMPXCHG_FAILURE]]
@@ -423,26 +409,25 @@ define i16 @test_cmpxchg_i16_global(i16 addrspace(1)* %out, i16 %in, i16 %old) {
; CHECK-NEXT: [[EXTRACT:%.*]] = extractvalue { i16, i1 } [[TMP18]], 0
; CHECK-NEXT: ret i16 [[EXTRACT]]
;
- %gep = getelementptr i16, i16 addrspace(1)* %out, i64 4
- %res = cmpxchg i16 addrspace(1)* %gep, i16 %old, i16 %in seq_cst seq_cst
+ %gep = getelementptr i16, ptr addrspace(1) %out, i64 4
+ %res = cmpxchg ptr addrspace(1) %gep, i16 %old, i16 %in seq_cst seq_cst
%extract = extractvalue {i16, i1} %res, 0
ret i16 %extract
}
-define i16 @test_cmpxchg_i16_global_align4(i16 addrspace(1)* %out, i16 %in, i16 %old) {
+define i16 @test_cmpxchg_i16_global_align4(ptr addrspace(1) %out, i16 %in, i16 %old) {
; CHECK-LABEL: @test_cmpxchg_i16_global_align4(
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr i16, i16 addrspace(1)* [[OUT:%.*]], i64 4
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = bitcast i16 addrspace(1)* [[GEP]] to i32 addrspace(1)*
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr i16, ptr addrspace(1) [[OUT:%.*]], i64 4
; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[IN:%.*]] to i32
; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[OLD:%.*]] to i32
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[GEP]], align 4
; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], -65536
; CHECK-NEXT: br label [[PARTWORD_CMPXCHG_LOOP:%.*]]
; CHECK: partword.cmpxchg.loop:
; CHECK-NEXT: [[TMP5:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[TMP11:%.*]], [[PARTWORD_CMPXCHG_FAILURE:%.*]] ]
; CHECK-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[TMP1]]
; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP5]], [[TMP2]]
-; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[TMP7]], i32 [[TMP6]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[GEP]], i32 [[TMP7]], i32 [[TMP6]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i32, i1 } [[TMP8]], 0
; CHECK-NEXT: [[TMP10:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1
; CHECK-NEXT: br i1 [[TMP10]], label [[PARTWORD_CMPXCHG_END:%.*]], label [[PARTWORD_CMPXCHG_FAILURE]]
@@ -457,30 +442,29 @@ define i16 @test_cmpxchg_i16_global_align4(i16 addrspace(1)* %out, i16 %in, i16
; CHECK-NEXT: [[EXTRACT:%.*]] = extractvalue { i16, i1 } [[TMP14]], 0
; CHECK-NEXT: ret i16 [[EXTRACT]]
;
- %gep = getelementptr i16, i16 addrspace(1)* %out, i64 4
- %res = cmpxchg i16 addrspace(1)* %gep, i16 %old, i16 %in seq_cst seq_cst, align 4
+ %gep = getelementptr i16, ptr addrspace(1) %out, i64 4
+ %res = cmpxchg ptr addrspace(1) %gep, i16 %old, i16 %in seq_cst seq_cst, align 4
%extract = extractvalue {i16, i1} %res, 0
ret i16 %extract
}
-define i16 @test_atomicrmw_xchg_i16_local(i16 addrspace(3)* %ptr, i16 %value) {
+define i16 @test_atomicrmw_xchg_i16_local(ptr addrspace(3) %ptr, i16 %value) {
; CHECK-LABEL: @test_atomicrmw_xchg_i16_local(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(3)* @llvm.ptrmask.p3i16.i32(i16 addrspace(3)* [[PTR:%.*]], i32 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(3)* [[PTR]] to i32
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i32(ptr addrspace(3) [[PTR:%.*]], i32 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i32
; CHECK-NEXT: [[PTRLSB:%.*]] = and i32 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[PTRLSB]], 3
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[TMP2]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[VALOPERAND_SHIFTED]]
-; CHECK-NEXT: [[TMP7:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP6]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP7:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP6]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -489,32 +473,31 @@ define i16 @test_atomicrmw_xchg_i16_local(i16 addrspace(3)* %ptr, i16 %value) {
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16
; CHECK-NEXT: ret i16 [[EXTRACTED]]
;
- %res = atomicrmw xchg i16 addrspace(3)* %ptr, i16 %value seq_cst
+ %res = atomicrmw xchg ptr addrspace(3) %ptr, i16 %value seq_cst
ret i16 %res
}
-define i16 @test_cmpxchg_i16_local(i16 addrspace(3)* %out, i16 %in, i16 %old) {
+define i16 @test_cmpxchg_i16_local(ptr addrspace(3) %out, i16 %in, i16 %old) {
; CHECK-LABEL: @test_cmpxchg_i16_local(
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr i16, i16 addrspace(3)* [[OUT:%.*]], i64 4
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(3)* @llvm.ptrmask.p3i16.i32(i16 addrspace(3)* [[GEP]], i32 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(3)* [[GEP]] to i32
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr i16, ptr addrspace(3) [[OUT:%.*]], i64 4
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i32(ptr addrspace(3) [[GEP]], i32 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[GEP]] to i32
; CHECK-NEXT: [[PTRLSB:%.*]] = and i32 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[PTRLSB]], 3
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[TMP2]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[IN:%.*]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = shl i32 [[TMP3]], [[TMP2]]
; CHECK-NEXT: [[TMP5:%.*]] = zext i16 [[OLD:%.*]] to i32
; CHECK-NEXT: [[TMP6:%.*]] = shl i32 [[TMP5]], [[TMP2]]
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], [[INV_MASK]]
; CHECK-NEXT: br label [[PARTWORD_CMPXCHG_LOOP:%.*]]
; CHECK: partword.cmpxchg.loop:
; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ [[TMP8]], [[TMP0:%.*]] ], [ [[TMP15:%.*]], [[PARTWORD_CMPXCHG_FAILURE:%.*]] ]
; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP4]]
; CHECK-NEXT: [[TMP11:%.*]] = or i32 [[TMP9]], [[TMP6]]
-; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[TMP11]], i32 [[TMP10]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[TMP11]], i32 [[TMP10]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[TMP13:%.*]] = extractvalue { i32, i1 } [[TMP12]], 0
; CHECK-NEXT: [[TMP14:%.*]] = extractvalue { i32, i1 } [[TMP12]], 1
; CHECK-NEXT: br i1 [[TMP14]], label [[PARTWORD_CMPXCHG_END:%.*]], label [[PARTWORD_CMPXCHG_FAILURE]]
@@ -530,20 +513,19 @@ define i16 @test_cmpxchg_i16_local(i16 addrspace(3)* %out, i16 %in, i16 %old) {
; CHECK-NEXT: [[EXTRACT:%.*]] = extractvalue { i16, i1 } [[TMP18]], 0
; CHECK-NEXT: ret i16 [[EXTRACT]]
;
- %gep = getelementptr i16, i16 addrspace(3)* %out, i64 4
- %res = cmpxchg i16 addrspace(3)* %gep, i16 %old, i16 %in seq_cst seq_cst
+ %gep = getelementptr i16, ptr addrspace(3) %out, i64 4
+ %res = cmpxchg ptr addrspace(3) %gep, i16 %old, i16 %in seq_cst seq_cst
%extract = extractvalue {i16, i1} %res, 0
ret i16 %extract
}
-define i16 @test_atomicrmw_xor_i16_local_align4(i16 addrspace(3)* %ptr, i16 %value) {
+define i16 @test_atomicrmw_xor_i16_local_align4(ptr addrspace(3) %ptr, i16 %value) {
; CHECK-LABEL: @test_atomicrmw_xor_i16_local_align4(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = bitcast i16 addrspace(3)* [[PTR:%.*]] to i32 addrspace(3)*
; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[VALUE:%.*]] to i32
-; CHECK-NEXT: [[TMP2:%.*]] = atomicrmw xor i32 addrspace(3)* [[ALIGNEDADDR]], i32 [[TMP1]] seq_cst, align 4
+; CHECK-NEXT: [[TMP2:%.*]] = atomicrmw xor ptr addrspace(3) [[PTR:%.*]], i32 [[TMP1]] seq_cst, align 4
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[TMP2]] to i16
; CHECK-NEXT: ret i16 [[EXTRACTED]]
;
- %res = atomicrmw xor i16 addrspace(3)* %ptr, i16 %value seq_cst, align 4
+ %res = atomicrmw xor ptr addrspace(3) %ptr, i16 %value seq_cst, align 4
ret i16 %res
}
diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll
index 40231cf7c9e92..073202850a6c1 100644
--- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll
+++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll
@@ -2,25 +2,24 @@
; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -atomic-expand %s | FileCheck %s
; RUN: opt -mtriple=r600-mesa-mesa3d -S -atomic-expand %s | FileCheck %s
-define i8 @test_atomicrmw_xchg_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
+define i8 @test_atomicrmw_xchg_i8_global(ptr addrspace(1) %ptr, i8 %value) {
; CHECK-LABEL: @test_atomicrmw_xchg_i8_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[VALOPERAND_SHIFTED]]
-; CHECK-NEXT: [[TMP7:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP6]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP7:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP6]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -29,23 +28,22 @@ define i8 @test_atomicrmw_xchg_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8
; CHECK-NEXT: ret i8 [[EXTRACTED]]
;
- %res = atomicrmw xchg i8 addrspace(1)* %ptr, i8 %value seq_cst
+ %res = atomicrmw xchg ptr addrspace(1) %ptr, i8 %value seq_cst
ret i8 %res
}
-define i8 @test_atomicrmw_add_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
+define i8 @test_atomicrmw_add_i8_global(ptr addrspace(1) %ptr, i8 %value) {
; CHECK-LABEL: @test_atomicrmw_add_i8_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -53,7 +51,7 @@ define i8 @test_atomicrmw_add_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[NEW]], [[MASK]]
; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP5]]
-; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP8]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -62,23 +60,22 @@ define i8 @test_atomicrmw_add_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8
; CHECK-NEXT: ret i8 [[EXTRACTED]]
;
- %res = atomicrmw add i8 addrspace(1)* %ptr, i8 %value seq_cst
+ %res = atomicrmw add ptr addrspace(1) %ptr, i8 %value seq_cst
ret i8 %res
}
-define i8 @test_atomicrmw_add_i8_global_align2(i8 addrspace(1)* %ptr, i8 %value) {
+define i8 @test_atomicrmw_add_i8_global_align2(ptr addrspace(1) %ptr, i8 %value) {
; CHECK-LABEL: @test_atomicrmw_add_i8_global_align2(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -86,7 +83,7 @@ define i8 @test_atomicrmw_add_i8_global_align2(i8 addrspace(1)* %ptr, i8 %value)
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[NEW]], [[MASK]]
; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP5]]
-; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP8]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -95,15 +92,14 @@ define i8 @test_atomicrmw_add_i8_global_align2(i8 addrspace(1)* %ptr, i8 %value)
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8
; CHECK-NEXT: ret i8 [[EXTRACTED]]
;
- %res = atomicrmw add i8 addrspace(1)* %ptr, i8 %value seq_cst, align 2
+ %res = atomicrmw add ptr addrspace(1) %ptr, i8 %value seq_cst, align 2
ret i8 %res
}
-define i8 @test_atomicrmw_add_i8_global_align4(i8 addrspace(1)* %ptr, i8 %value) {
+define i8 @test_atomicrmw_add_i8_global_align4(ptr addrspace(1) %ptr, i8 %value) {
; CHECK-LABEL: @test_atomicrmw_add_i8_global_align4(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = bitcast i8 addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[VALUE:%.*]] to i32
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -111,7 +107,7 @@ define i8 @test_atomicrmw_add_i8_global_align4(i8 addrspace(1)* %ptr, i8 %value)
; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[NEW]], 255
; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[LOADED]], -256
; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], [[TMP3]]
-; CHECK-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP5]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[TMP5]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -119,23 +115,22 @@ define i8 @test_atomicrmw_add_i8_global_align4(i8 addrspace(1)* %ptr, i8 %value)
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[NEWLOADED]] to i8
; CHECK-NEXT: ret i8 [[EXTRACTED]]
;
- %res = atomicrmw add i8 addrspace(1)* %ptr, i8 %value seq_cst, align 4
+ %res = atomicrmw add ptr addrspace(1) %ptr, i8 %value seq_cst, align 4
ret i8 %res
}
-define i8 @test_atomicrmw_sub_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
+define i8 @test_atomicrmw_sub_i8_global(ptr addrspace(1) %ptr, i8 %value) {
; CHECK-LABEL: @test_atomicrmw_sub_i8_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -143,7 +138,7 @@ define i8 @test_atomicrmw_sub_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[NEW]], [[MASK]]
; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP5]]
-; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP8]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -152,45 +147,43 @@ define i8 @test_atomicrmw_sub_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8
; CHECK-NEXT: ret i8 [[EXTRACTED]]
;
- %res = atomicrmw sub i8 addrspace(1)* %ptr, i8 %value seq_cst
+ %res = atomicrmw sub ptr addrspace(1) %ptr, i8 %value seq_cst
ret i8 %res
}
-define i8 @test_atomicrmw_and_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
+define i8 @test_atomicrmw_and_i8_global(ptr addrspace(1) %ptr, i8 %value) {
; CHECK-LABEL: @test_atomicrmw_and_i8_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[INV_MASK]], [[VALOPERAND_SHIFTED]]
-; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw and i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[ANDOPERAND]] seq_cst, align 4
+; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw and ptr addrspace(1) [[ALIGNEDADDR]], i32 [[ANDOPERAND]] seq_cst, align 4
; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]]
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8
; CHECK-NEXT: ret i8 [[EXTRACTED]]
;
- %res = atomicrmw and i8 addrspace(1)* %ptr, i8 %value seq_cst
+ %res = atomicrmw and ptr addrspace(1) %ptr, i8 %value seq_cst
ret i8 %res
}
-define i8 @test_atomicrmw_nand_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
+define i8 @test_atomicrmw_nand_i8_global(ptr addrspace(1) %ptr, i8 %value) {
; CHECK-LABEL: @test_atomicrmw_nand_i8_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -199,7 +192,7 @@ define i8 @test_atomicrmw_nand_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[NEW]], [[MASK]]
; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP8]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP9:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP8]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP9]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP9]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -208,63 +201,60 @@ define i8 @test_atomicrmw_nand_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8
; CHECK-NEXT: ret i8 [[EXTRACTED]]
;
- %res = atomicrmw nand i8 addrspace(1)* %ptr, i8 %value seq_cst
+ %res = atomicrmw nand ptr addrspace(1) %ptr, i8 %value seq_cst
ret i8 %res
}
-define i8 @test_atomicrmw_or_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
+define i8 @test_atomicrmw_or_i8_global(ptr addrspace(1) %ptr, i8 %value) {
; CHECK-LABEL: @test_atomicrmw_or_i8_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw or i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[VALOPERAND_SHIFTED]] seq_cst, align 4
+; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw or ptr addrspace(1) [[ALIGNEDADDR]], i32 [[VALOPERAND_SHIFTED]] seq_cst, align 4
; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]]
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8
; CHECK-NEXT: ret i8 [[EXTRACTED]]
;
- %res = atomicrmw or i8 addrspace(1)* %ptr, i8 %value seq_cst
+ %res = atomicrmw or ptr addrspace(1) %ptr, i8 %value seq_cst
ret i8 %res
}
-define i8 @test_atomicrmw_xor_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
+define i8 @test_atomicrmw_xor_i8_global(ptr addrspace(1) %ptr, i8 %value) {
; CHECK-LABEL: @test_atomicrmw_xor_i8_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw xor i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[VALOPERAND_SHIFTED]] seq_cst, align 4
+; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw xor ptr addrspace(1) [[ALIGNEDADDR]], i32 [[VALOPERAND_SHIFTED]] seq_cst, align 4
; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]]
; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8
; CHECK-NEXT: ret i8 [[EXTRACTED]]
;
- %res = atomicrmw xor i8 addrspace(1)* %ptr, i8 %value seq_cst
+ %res = atomicrmw xor ptr addrspace(1) %ptr, i8 %value seq_cst
ret i8 %res
}
-define i8 @test_atomicrmw_max_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
+define i8 @test_atomicrmw_max_i8_global(ptr addrspace(1) %ptr, i8 %value) {
; CHECK-LABEL: @test_atomicrmw_max_i8_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -276,7 +266,7 @@ define i8 @test_atomicrmw_max_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -285,21 +275,20 @@ define i8 @test_atomicrmw_max_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i8
; CHECK-NEXT: ret i8 [[EXTRACTED4]]
;
- %res = atomicrmw max i8 addrspace(1)* %ptr, i8 %value seq_cst
+ %res = atomicrmw max ptr addrspace(1) %ptr, i8 %value seq_cst
ret i8 %res
}
-define i8 @test_atomicrmw_min_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
+define i8 @test_atomicrmw_min_i8_global(ptr addrspace(1) %ptr, i8 %value) {
; CHECK-LABEL: @test_atomicrmw_min_i8_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -311,7 +300,7 @@ define i8 @test_atomicrmw_min_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -320,21 +309,20 @@ define i8 @test_atomicrmw_min_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i8
; CHECK-NEXT: ret i8 [[EXTRACTED4]]
;
- %res = atomicrmw min i8 addrspace(1)* %ptr, i8 %value seq_cst
+ %res = atomicrmw min ptr addrspace(1) %ptr, i8 %value seq_cst
ret i8 %res
}
-define i8 @test_atomicrmw_umax_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
+define i8 @test_atomicrmw_umax_i8_global(ptr addrspace(1) %ptr, i8 %value) {
; CHECK-LABEL: @test_atomicrmw_umax_i8_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -346,7 +334,7 @@ define i8 @test_atomicrmw_umax_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -355,21 +343,20 @@ define i8 @test_atomicrmw_umax_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i8
; CHECK-NEXT: ret i8 [[EXTRACTED4]]
;
- %res = atomicrmw umax i8 addrspace(1)* %ptr, i8 %value seq_cst
+ %res = atomicrmw umax ptr addrspace(1) %ptr, i8 %value seq_cst
ret i8 %res
}
-define i8 @test_atomicrmw_umin_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
+define i8 @test_atomicrmw_umin_i8_global(ptr addrspace(1) %ptr, i8 %value) {
; CHECK-LABEL: @test_atomicrmw_umin_i8_global(
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -381,7 +368,7 @@ define i8 @test_atomicrmw_umin_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -390,33 +377,32 @@ define i8 @test_atomicrmw_umin_i8_global(i8 addrspace(1)* %ptr, i8 %value) {
; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i8
; CHECK-NEXT: ret i8 [[EXTRACTED4]]
;
- %res = atomicrmw umin i8 addrspace(1)* %ptr, i8 %value seq_cst
+ %res = atomicrmw umin ptr addrspace(1) %ptr, i8 %value seq_cst
ret i8 %res
}
-define i8 @test_cmpxchg_i8_global(i8 addrspace(1)* %out, i8 %in, i8 %old) {
+define i8 @test_cmpxchg_i8_global(ptr addrspace(1) %out, i8 %in, i8 %old) {
; CHECK-LABEL: @test_cmpxchg_i8_global(
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, i8 addrspace(1)* [[OUT:%.*]], i64 4
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[GEP]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[GEP]] to i64
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr addrspace(1) [[OUT:%.*]], i64 4
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[GEP]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[GEP]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[IN:%.*]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[OLD:%.*]] to i32
; CHECK-NEXT: [[TMP6:%.*]] = shl i32 [[TMP5]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], [[INV_MASK]]
; CHECK-NEXT: br label [[PARTWORD_CMPXCHG_LOOP:%.*]]
; CHECK: partword.cmpxchg.loop:
; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ [[TMP8]], [[TMP0:%.*]] ], [ [[TMP15:%.*]], [[PARTWORD_CMPXCHG_FAILURE:%.*]] ]
; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP4]]
; CHECK-NEXT: [[TMP11:%.*]] = or i32 [[TMP9]], [[TMP6]]
-; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[TMP11]], i32 [[TMP10]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[TMP11]], i32 [[TMP10]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[TMP13:%.*]] = extractvalue { i32, i1 } [[TMP12]], 0
; CHECK-NEXT: [[TMP14:%.*]] = extractvalue { i32, i1 } [[TMP12]], 1
; CHECK-NEXT: br i1 [[TMP14]], label [[PARTWORD_CMPXCHG_END:%.*]], label [[PARTWORD_CMPXCHG_FAILURE]]
@@ -432,35 +418,34 @@ define i8 @test_cmpxchg_i8_global(i8 addrspace(1)* %out, i8 %in, i8 %old) {
; CHECK-NEXT: [[EXTRACT:%.*]] = extractvalue { i8, i1 } [[TMP18]], 0
; CHECK-NEXT: ret i8 [[EXTRACT]]
;
- %gep = getelementptr i8, i8 addrspace(1)* %out, i64 4
- %res = cmpxchg i8 addrspace(1)* %gep, i8 %old, i8 %in seq_cst seq_cst
+ %gep = getelementptr i8, ptr addrspace(1) %out, i64 4
+ %res = cmpxchg ptr addrspace(1) %gep, i8 %old, i8 %in seq_cst seq_cst
%extract = extractvalue {i8, i1} %res, 0
ret i8 %extract
}
-define i8 @test_cmpxchg_i8_local_align2(i8 addrspace(3)* %out, i8 %in, i8 %old) {
+define i8 @test_cmpxchg_i8_local_align2(ptr addrspace(3) %out, i8 %in, i8 %old) {
; CHECK-LABEL: @test_cmpxchg_i8_local_align2(
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, i8 addrspace(3)* [[OUT:%.*]], i64 4
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(3)* @llvm.ptrmask.p3i8.i64(i8 addrspace(3)* [[GEP]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(3)* [[GEP]] to i64
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr addrspace(3) [[OUT:%.*]], i64 4
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[GEP]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[GEP]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)*
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[IN:%.*]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[OLD:%.*]] to i32
; CHECK-NEXT: [[TMP6:%.*]] = shl i32 [[TMP5]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4
; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], [[INV_MASK]]
; CHECK-NEXT: br label [[PARTWORD_CMPXCHG_LOOP:%.*]]
; CHECK: partword.cmpxchg.loop:
; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ [[TMP8]], [[TMP0:%.*]] ], [ [[TMP15:%.*]], [[PARTWORD_CMPXCHG_FAILURE:%.*]] ]
; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP4]]
; CHECK-NEXT: [[TMP11:%.*]] = or i32 [[TMP9]], [[TMP6]]
-; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[TMP11]], i32 [[TMP10]] seq_cst seq_cst, align 4
+; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[TMP11]], i32 [[TMP10]] seq_cst seq_cst, align 4
; CHECK-NEXT: [[TMP13:%.*]] = extractvalue { i32, i1 } [[TMP12]], 0
; CHECK-NEXT: [[TMP14:%.*]] = extractvalue { i32, i1 } [[TMP12]], 1
; CHECK-NEXT: br i1 [[TMP14]], label [[PARTWORD_CMPXCHG_END:%.*]], label [[PARTWORD_CMPXCHG_FAILURE]]
@@ -476,8 +461,8 @@ define i8 @test_cmpxchg_i8_local_align2(i8 addrspace(3)* %out, i8 %in, i8 %old)
; CHECK-NEXT: [[EXTRACT:%.*]] = extractvalue { i8, i1 } [[TMP18]], 0
; CHECK-NEXT: ret i8 [[EXTRACT]]
;
- %gep = getelementptr i8, i8 addrspace(3)* %out, i64 4
- %res = cmpxchg i8 addrspace(3)* %gep, i8 %old, i8 %in seq_cst seq_cst, align 2
+ %gep = getelementptr i8, ptr addrspace(3) %out, i64 4
+ %res = cmpxchg ptr addrspace(3) %gep, i8 %old, i8 %in seq_cst seq_cst, align 2
%extract = extractvalue {i8, i1} %res, 0
ret i8 %extract
}
diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd-flat-specialization.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd-flat-specialization.ll
index 243927c45f89d..542e4a3761190 100644
--- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd-flat-specialization.ll
+++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd-flat-specialization.ll
@@ -4,17 +4,16 @@
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx940 -atomic-expand %s | FileCheck -check-prefix=GFX940 %s
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -atomic-expand %s | FileCheck -check-prefix=GFX1100 %s
-define float @syncscope_system(float* %addr, float %val) #0 {
+define float @syncscope_system(ptr %addr, float %val) #0 {
; GFX908-LABEL: @syncscope_system(
-; GFX908-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4
+; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]]
-; GFX908-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32*
; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -23,15 +22,14 @@ define float @syncscope_system(float* %addr, float %val) #0 {
; GFX908-NEXT: ret float [[TMP6]]
;
; GFX90A-LABEL: @syncscope_system(
-; GFX90A-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4
+; GFX90A-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4
; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX90A: atomicrmw.start:
; GFX90A-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX90A-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]]
-; GFX90A-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32*
; GFX90A-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX90A-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX90A-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -40,15 +38,14 @@ define float @syncscope_system(float* %addr, float %val) #0 {
; GFX90A-NEXT: ret float [[TMP6]]
;
; GFX940-LABEL: @syncscope_system(
-; GFX940-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4
+; GFX940-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4
; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX940: atomicrmw.start:
; GFX940-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX940-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]]
-; GFX940-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32*
; GFX940-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX940-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX940-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -57,15 +54,14 @@ define float @syncscope_system(float* %addr, float %val) #0 {
; GFX940-NEXT: ret float [[TMP6]]
;
; GFX1100-LABEL: @syncscope_system(
-; GFX1100-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4
+; GFX1100-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4
; GFX1100-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX1100: atomicrmw.start:
; GFX1100-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX1100-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]]
-; GFX1100-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32*
; GFX1100-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX1100-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX1100-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX1100-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX1100-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX1100-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX1100-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -74,36 +70,34 @@ define float @syncscope_system(float* %addr, float %val) #0 {
; GFX1100-NEXT: ret float [[TMP6]]
;
; GFX11-LABEL: @syncscope_system(
-; GFX11-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4
+; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4
; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX11: atomicrmw.start:
; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]]
-; GFX11-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32*
; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
; GFX11-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
; GFX11: atomicrmw.end:
; GFX11-NEXT: ret float [[TMP6]]
- %res = atomicrmw fadd float* %addr, float %val seq_cst
+ %res = atomicrmw fadd ptr %addr, float %val seq_cst
ret float %res
}
-define float @syncscope_workgroup_rtn(float* %addr, float %val) #0 {
+define float @syncscope_workgroup_rtn(ptr %addr, float %val) #0 {
; GFX908-LABEL: @syncscope_workgroup_rtn(
-; GFX908-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4
+; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]]
-; GFX908-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32*
; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4
+; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -112,27 +106,26 @@ define float @syncscope_workgroup_rtn(float* %addr, float %val) #0 {
; GFX908-NEXT: ret float [[TMP6]]
;
; GFX90A-LABEL: @syncscope_workgroup_rtn(
-; GFX90A-NEXT: [[TMP1:%.*]] = bitcast float* [[ADDR:%.*]] to i8*
; GFX90A-NEXT: br label [[ATOMICRMW_CHECK_SHARED:%.*]]
; GFX90A: atomicrmw.check.shared:
-; GFX90A-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(i8* [[TMP1]])
+; GFX90A-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[ADDR:%.*]])
; GFX90A-NEXT: br i1 [[IS_SHARED]], label [[ATOMICRMW_SHARED:%.*]], label [[ATOMICRMW_CHECK_PRIVATE:%.*]]
; GFX90A: atomicrmw.shared:
-; GFX90A-NEXT: [[TMP2:%.*]] = addrspacecast float* [[ADDR]] to float addrspace(3)*
-; GFX90A-NEXT: [[TMP3:%.*]] = atomicrmw fadd float addrspace(3)* [[TMP2]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4
+; GFX90A-NEXT: [[TMP2:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(3)
+; GFX90A-NEXT: [[TMP3:%.*]] = atomicrmw fadd ptr addrspace(3) [[TMP2]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4
; GFX90A-NEXT: br label [[ATOMICRMW_PHI:%.*]]
; GFX90A: atomicrmw.check.private:
-; GFX90A-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(i8* [[TMP1]])
+; GFX90A-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[ADDR]])
; GFX90A-NEXT: br i1 [[IS_PRIVATE]], label [[ATOMICRMW_PRIVATE:%.*]], label [[ATOMICRMW_GLOBAL:%.*]]
; GFX90A: atomicrmw.private:
-; GFX90A-NEXT: [[TMP4:%.*]] = addrspacecast float* [[ADDR]] to float addrspace(5)*
-; GFX90A-NEXT: [[LOADED_PRIVATE:%.*]] = load float, float addrspace(5)* [[TMP4]], align 4
+; GFX90A-NEXT: [[TMP4:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(5)
+; GFX90A-NEXT: [[LOADED_PRIVATE:%.*]] = load float, ptr addrspace(5) [[TMP4]], align 4
; GFX90A-NEXT: [[VAL_NEW:%.*]] = fadd float [[LOADED_PRIVATE]], [[VAL]]
-; GFX90A-NEXT: store float [[VAL_NEW]], float addrspace(5)* [[TMP4]], align 4
+; GFX90A-NEXT: store float [[VAL_NEW]], ptr addrspace(5) [[TMP4]], align 4
; GFX90A-NEXT: br label [[ATOMICRMW_PHI]]
; GFX90A: atomicrmw.global:
-; GFX90A-NEXT: [[TMP5:%.*]] = addrspacecast float* [[ADDR]] to float addrspace(1)*
-; GFX90A-NEXT: [[TMP6:%.*]] = atomicrmw fadd float addrspace(1)* [[TMP5]], float [[VAL]] syncscope("workgroup") seq_cst, align 4
+; GFX90A-NEXT: [[TMP5:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(1)
+; GFX90A-NEXT: [[TMP6:%.*]] = atomicrmw fadd ptr addrspace(1) [[TMP5]], float [[VAL]] syncscope("workgroup") seq_cst, align 4
; GFX90A-NEXT: br label [[ATOMICRMW_PHI]]
; GFX90A: atomicrmw.phi:
; GFX90A-NEXT: [[LOADED_PHI:%.*]] = phi float [ [[TMP3]], [[ATOMICRMW_SHARED]] ], [ [[LOADED_PRIVATE]], [[ATOMICRMW_PRIVATE]] ], [ [[TMP6]], [[ATOMICRMW_GLOBAL]] ]
@@ -141,56 +134,54 @@ define float @syncscope_workgroup_rtn(float* %addr, float %val) #0 {
; GFX90A-NEXT: ret float [[LOADED_PHI]]
;
; GFX940-LABEL: @syncscope_workgroup_rtn(
-; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd float* [[ADDR:%.*]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4
+; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd ptr [[ADDR:%.*]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4
; GFX940-NEXT: ret float [[RES]]
;
; GFX1100-LABEL: @syncscope_workgroup_rtn(
-; GFX1100-NEXT: [[RES:%.*]] = atomicrmw fadd float* [[ADDR:%.*]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4
+; GFX1100-NEXT: [[RES:%.*]] = atomicrmw fadd ptr [[ADDR:%.*]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4
; GFX1100-NEXT: ret float [[RES]]
;
; GFX11-LABEL: @syncscope_workgroup_rtn(
-; GFX11-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4
+; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4
; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX11: atomicrmw.start:
; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]]
-; GFX11-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32*
; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4
+; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4
; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
; GFX11-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
; GFX11: atomicrmw.end:
; GFX11-NEXT: ret float [[TMP6]]
- %res = atomicrmw fadd float* %addr, float %val syncscope("workgroup") seq_cst
+ %res = atomicrmw fadd ptr %addr, float %val syncscope("workgroup") seq_cst
ret float %res
}
-define void @syncscope_workgroup_nortn(float* %addr, float %val) #0 {
+define void @syncscope_workgroup_nortn(ptr %addr, float %val) #0 {
; GFX908-LABEL: @syncscope_workgroup_nortn(
-; GFX908-NEXT: [[TMP1:%.*]] = bitcast float* [[ADDR:%.*]] to i8*
; GFX908-NEXT: br label [[ATOMICRMW_CHECK_SHARED:%.*]]
; GFX908: atomicrmw.check.shared:
-; GFX908-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(i8* [[TMP1]])
+; GFX908-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[ADDR:%.*]])
; GFX908-NEXT: br i1 [[IS_SHARED]], label [[ATOMICRMW_SHARED:%.*]], label [[ATOMICRMW_CHECK_PRIVATE:%.*]]
; GFX908: atomicrmw.shared:
-; GFX908-NEXT: [[TMP2:%.*]] = addrspacecast float* [[ADDR]] to float addrspace(3)*
-; GFX908-NEXT: [[TMP3:%.*]] = atomicrmw fadd float addrspace(3)* [[TMP2]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4
+; GFX908-NEXT: [[TMP2:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(3)
+; GFX908-NEXT: [[TMP3:%.*]] = atomicrmw fadd ptr addrspace(3) [[TMP2]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4
; GFX908-NEXT: br label [[ATOMICRMW_PHI:%.*]]
; GFX908: atomicrmw.check.private:
-; GFX908-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(i8* [[TMP1]])
+; GFX908-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[ADDR]])
; GFX908-NEXT: br i1 [[IS_PRIVATE]], label [[ATOMICRMW_PRIVATE:%.*]], label [[ATOMICRMW_GLOBAL:%.*]]
; GFX908: atomicrmw.private:
-; GFX908-NEXT: [[TMP4:%.*]] = addrspacecast float* [[ADDR]] to float addrspace(5)*
-; GFX908-NEXT: [[LOADED_PRIVATE:%.*]] = load float, float addrspace(5)* [[TMP4]], align 4
+; GFX908-NEXT: [[TMP4:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(5)
+; GFX908-NEXT: [[LOADED_PRIVATE:%.*]] = load float, ptr addrspace(5) [[TMP4]], align 4
; GFX908-NEXT: [[VAL_NEW:%.*]] = fadd float [[LOADED_PRIVATE]], [[VAL]]
-; GFX908-NEXT: store float [[VAL_NEW]], float addrspace(5)* [[TMP4]], align 4
+; GFX908-NEXT: store float [[VAL_NEW]], ptr addrspace(5) [[TMP4]], align 4
; GFX908-NEXT: br label [[ATOMICRMW_PHI]]
; GFX908: atomicrmw.global:
-; GFX908-NEXT: [[TMP5:%.*]] = addrspacecast float* [[ADDR]] to float addrspace(1)*
-; GFX908-NEXT: [[TMP6:%.*]] = atomicrmw fadd float addrspace(1)* [[TMP5]], float [[VAL]] syncscope("workgroup") seq_cst, align 4
+; GFX908-NEXT: [[TMP5:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(1)
+; GFX908-NEXT: [[TMP6:%.*]] = atomicrmw fadd ptr addrspace(1) [[TMP5]], float [[VAL]] syncscope("workgroup") seq_cst, align 4
; GFX908-NEXT: br label [[ATOMICRMW_PHI]]
; GFX908: atomicrmw.phi:
; GFX908-NEXT: [[LOADED_PHI:%.*]] = phi float [ [[TMP3]], [[ATOMICRMW_SHARED]] ], [ [[LOADED_PRIVATE]], [[ATOMICRMW_PRIVATE]] ], [ [[TMP6]], [[ATOMICRMW_GLOBAL]] ]
@@ -199,27 +190,26 @@ define void @syncscope_workgroup_nortn(float* %addr, float %val) #0 {
; GFX908-NEXT: ret void
;
; GFX90A-LABEL: @syncscope_workgroup_nortn(
-; GFX90A-NEXT: [[TMP1:%.*]] = bitcast float* [[ADDR:%.*]] to i8*
; GFX90A-NEXT: br label [[ATOMICRMW_CHECK_SHARED:%.*]]
; GFX90A: atomicrmw.check.shared:
-; GFX90A-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(i8* [[TMP1]])
+; GFX90A-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[ADDR:%.*]])
; GFX90A-NEXT: br i1 [[IS_SHARED]], label [[ATOMICRMW_SHARED:%.*]], label [[ATOMICRMW_CHECK_PRIVATE:%.*]]
; GFX90A: atomicrmw.shared:
-; GFX90A-NEXT: [[TMP2:%.*]] = addrspacecast float* [[ADDR]] to float addrspace(3)*
-; GFX90A-NEXT: [[TMP3:%.*]] = atomicrmw fadd float addrspace(3)* [[TMP2]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4
+; GFX90A-NEXT: [[TMP2:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(3)
+; GFX90A-NEXT: [[TMP3:%.*]] = atomicrmw fadd ptr addrspace(3) [[TMP2]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4
; GFX90A-NEXT: br label [[ATOMICRMW_PHI:%.*]]
; GFX90A: atomicrmw.check.private:
-; GFX90A-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(i8* [[TMP1]])
+; GFX90A-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[ADDR]])
; GFX90A-NEXT: br i1 [[IS_PRIVATE]], label [[ATOMICRMW_PRIVATE:%.*]], label [[ATOMICRMW_GLOBAL:%.*]]
; GFX90A: atomicrmw.private:
-; GFX90A-NEXT: [[TMP4:%.*]] = addrspacecast float* [[ADDR]] to float addrspace(5)*
-; GFX90A-NEXT: [[LOADED_PRIVATE:%.*]] = load float, float addrspace(5)* [[TMP4]], align 4
+; GFX90A-NEXT: [[TMP4:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(5)
+; GFX90A-NEXT: [[LOADED_PRIVATE:%.*]] = load float, ptr addrspace(5) [[TMP4]], align 4
; GFX90A-NEXT: [[VAL_NEW:%.*]] = fadd float [[LOADED_PRIVATE]], [[VAL]]
-; GFX90A-NEXT: store float [[VAL_NEW]], float addrspace(5)* [[TMP4]], align 4
+; GFX90A-NEXT: store float [[VAL_NEW]], ptr addrspace(5) [[TMP4]], align 4
; GFX90A-NEXT: br label [[ATOMICRMW_PHI]]
; GFX90A: atomicrmw.global:
-; GFX90A-NEXT: [[TMP5:%.*]] = addrspacecast float* [[ADDR]] to float addrspace(1)*
-; GFX90A-NEXT: [[TMP6:%.*]] = atomicrmw fadd float addrspace(1)* [[TMP5]], float [[VAL]] syncscope("workgroup") seq_cst, align 4
+; GFX90A-NEXT: [[TMP5:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(1)
+; GFX90A-NEXT: [[TMP6:%.*]] = atomicrmw fadd ptr addrspace(1) [[TMP5]], float [[VAL]] syncscope("workgroup") seq_cst, align 4
; GFX90A-NEXT: br label [[ATOMICRMW_PHI]]
; GFX90A: atomicrmw.phi:
; GFX90A-NEXT: [[LOADED_PHI:%.*]] = phi float [ [[TMP3]], [[ATOMICRMW_SHARED]] ], [ [[LOADED_PRIVATE]], [[ATOMICRMW_PRIVATE]] ], [ [[TMP6]], [[ATOMICRMW_GLOBAL]] ]
@@ -228,44 +218,42 @@ define void @syncscope_workgroup_nortn(float* %addr, float %val) #0 {
; GFX90A-NEXT: ret void
;
; GFX940-LABEL: @syncscope_workgroup_nortn(
-; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd float* [[ADDR:%.*]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4
+; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd ptr [[ADDR:%.*]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4
; GFX940-NEXT: ret void
;
; GFX1100-LABEL: @syncscope_workgroup_nortn(
-; GFX1100-NEXT: [[RES:%.*]] = atomicrmw fadd float* [[ADDR:%.*]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4
+; GFX1100-NEXT: [[RES:%.*]] = atomicrmw fadd ptr [[ADDR:%.*]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4
; GFX1100-NEXT: ret void
;
; GFX11-LABEL: @syncscope_workgroup_nortn(
-; GFX11-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4
+; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4
; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX11: atomicrmw.start:
; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]]
-; GFX11-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32*
; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4
+; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4
; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
; GFX11-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
; GFX11: atomicrmw.end:
; GFX11-NEXT: ret void
- %res = atomicrmw fadd float* %addr, float %val syncscope("workgroup") seq_cst
+ %res = atomicrmw fadd ptr %addr, float %val syncscope("workgroup") seq_cst
ret void
}
-define float @no_unsafe(float* %addr, float %val) {
+define float @no_unsafe(ptr %addr, float %val) {
; GFX908-LABEL: @no_unsafe(
-; GFX908-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4
+; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]]
-; GFX908-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32*
; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4
+; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -274,15 +262,14 @@ define float @no_unsafe(float* %addr, float %val) {
; GFX908-NEXT: ret float [[TMP6]]
;
; GFX90A-LABEL: @no_unsafe(
-; GFX90A-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4
+; GFX90A-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4
; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX90A: atomicrmw.start:
; GFX90A-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX90A-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]]
-; GFX90A-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32*
; GFX90A-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX90A-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4
+; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4
; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX90A-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -291,15 +278,14 @@ define float @no_unsafe(float* %addr, float %val) {
; GFX90A-NEXT: ret float [[TMP6]]
;
; GFX940-LABEL: @no_unsafe(
-; GFX940-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4
+; GFX940-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4
; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX940: atomicrmw.start:
; GFX940-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX940-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]]
-; GFX940-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32*
; GFX940-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX940-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4
+; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4
; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX940-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -308,15 +294,14 @@ define float @no_unsafe(float* %addr, float %val) {
; GFX940-NEXT: ret float [[TMP6]]
;
; GFX1100-LABEL: @no_unsafe(
-; GFX1100-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4
+; GFX1100-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4
; GFX1100-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX1100: atomicrmw.start:
; GFX1100-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX1100-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]]
-; GFX1100-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32*
; GFX1100-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX1100-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX1100-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4
+; GFX1100-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4
; GFX1100-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX1100-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX1100-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -325,22 +310,21 @@ define float @no_unsafe(float* %addr, float %val) {
; GFX1100-NEXT: ret float [[TMP6]]
;
; GFX11-LABEL: @no_unsafe(
-; GFX11-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4
+; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4
; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX11: atomicrmw.start:
; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]]
-; GFX11-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32*
; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4
+; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4
; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
; GFX11-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
; GFX11: atomicrmw.end:
; GFX11-NEXT: ret float [[TMP6]]
- %res = atomicrmw fadd float* %addr, float %val syncscope("workgroup") seq_cst
+ %res = atomicrmw fadd ptr %addr, float %val syncscope("workgroup") seq_cst
ret float %res
}
diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
index be84ebafc51d2..35e589f958695 100644
--- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
+++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll
@@ -6,17 +6,16 @@
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx940 -atomic-expand %s | FileCheck -check-prefix=GFX940 %s
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -atomic-expand %s | FileCheck -check-prefix=GFX11 %s
-define void @test_atomicrmw_fadd_f32_global_no_use_unsafe(float addrspace(1)* %ptr, float %value) #0 {
+define void @test_atomicrmw_fadd_f32_global_no_use_unsafe(ptr addrspace(1) %ptr, float %value) #0 {
; CI-LABEL: @test_atomicrmw_fadd_f32_global_no_use_unsafe(
-; CI-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; CI-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; CI-NEXT: br label [[ATOMICRMW_START:%.*]]
; CI: atomicrmw.start:
; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CI-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4
+; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4
; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -25,15 +24,14 @@ define void @test_atomicrmw_fadd_f32_global_no_use_unsafe(float addrspace(1)* %p
; CI-NEXT: ret void
;
; GFX9-LABEL: @test_atomicrmw_fadd_f32_global_no_use_unsafe(
-; GFX9-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX9-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX9: atomicrmw.start:
; GFX9-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX9-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX9-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX9-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4
+; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4
; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX9-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -42,36 +40,35 @@ define void @test_atomicrmw_fadd_f32_global_no_use_unsafe(float addrspace(1)* %p
; GFX9-NEXT: ret void
;
; GFX908-LABEL: @test_atomicrmw_fadd_f32_global_no_use_unsafe(
-; GFX908-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(1)* [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
+; GFX908-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
; GFX908-NEXT: ret void
;
; GFX90A-LABEL: @test_atomicrmw_fadd_f32_global_no_use_unsafe(
-; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(1)* [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
+; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
; GFX90A-NEXT: ret void
;
; GFX940-LABEL: @test_atomicrmw_fadd_f32_global_no_use_unsafe(
-; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(1)* [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
+; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
; GFX940-NEXT: ret void
;
; GFX11-LABEL: @test_atomicrmw_fadd_f32_global_no_use_unsafe(
-; GFX11-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(1)* [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
+; GFX11-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
; GFX11-NEXT: ret void
;
- %res = atomicrmw fadd float addrspace(1)* %ptr, float %value syncscope("wavefront") monotonic
+ %res = atomicrmw fadd ptr addrspace(1) %ptr, float %value syncscope("wavefront") monotonic
ret void
}
-define float @test_atomicrmw_fadd_f32_global_unsafe(float addrspace(1)* %ptr, float %value) #0 {
+define float @test_atomicrmw_fadd_f32_global_unsafe(ptr addrspace(1) %ptr, float %value) #0 {
; CI-LABEL: @test_atomicrmw_fadd_f32_global_unsafe(
-; CI-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; CI-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; CI-NEXT: br label [[ATOMICRMW_START:%.*]]
; CI: atomicrmw.start:
; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CI-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4
+; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4
; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -80,15 +77,14 @@ define float @test_atomicrmw_fadd_f32_global_unsafe(float addrspace(1)* %ptr, fl
; CI-NEXT: ret float [[TMP6]]
;
; GFX9-LABEL: @test_atomicrmw_fadd_f32_global_unsafe(
-; GFX9-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX9-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX9: atomicrmw.start:
; GFX9-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX9-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX9-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX9-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4
+; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4
; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX9-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -97,15 +93,14 @@ define float @test_atomicrmw_fadd_f32_global_unsafe(float addrspace(1)* %ptr, fl
; GFX9-NEXT: ret float [[TMP6]]
;
; GFX908-LABEL: @test_atomicrmw_fadd_f32_global_unsafe(
-; GFX908-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX908-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4
+; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -114,32 +109,31 @@ define float @test_atomicrmw_fadd_f32_global_unsafe(float addrspace(1)* %ptr, fl
; GFX908-NEXT: ret float [[TMP6]]
;
; GFX90A-LABEL: @test_atomicrmw_fadd_f32_global_unsafe(
-; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(1)* [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
+; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
; GFX90A-NEXT: ret float [[RES]]
;
; GFX940-LABEL: @test_atomicrmw_fadd_f32_global_unsafe(
-; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(1)* [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
+; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
; GFX940-NEXT: ret float [[RES]]
;
; GFX11-LABEL: @test_atomicrmw_fadd_f32_global_unsafe(
-; GFX11-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(1)* [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
+; GFX11-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
; GFX11-NEXT: ret float [[RES]]
;
- %res = atomicrmw fadd float addrspace(1)* %ptr, float %value syncscope("wavefront") monotonic
+ %res = atomicrmw fadd ptr addrspace(1) %ptr, float %value syncscope("wavefront") monotonic
ret float %res
}
-define double @test_atomicrmw_fadd_f64_global_unsafe(double addrspace(1)* %ptr, double %value) #0 {
+define double @test_atomicrmw_fadd_f64_global_unsafe(ptr addrspace(1) %ptr, double %value) #0 {
; CI-LABEL: @test_atomicrmw_fadd_f64_global_unsafe(
-; CI-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8
+; CI-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8
; CI-NEXT: br label [[ATOMICRMW_START:%.*]]
; CI: atomicrmw.start:
; CI-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CI-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; CI-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)*
; CI-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; CI-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; CI-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8
+; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8
; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; CI-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -148,15 +142,14 @@ define double @test_atomicrmw_fadd_f64_global_unsafe(double addrspace(1)* %ptr,
; CI-NEXT: ret double [[TMP6]]
;
; GFX9-LABEL: @test_atomicrmw_fadd_f64_global_unsafe(
-; GFX9-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8
+; GFX9-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8
; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX9: atomicrmw.start:
; GFX9-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX9-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; GFX9-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)*
; GFX9-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GFX9-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8
+; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8
; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GFX9-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -165,15 +158,14 @@ define double @test_atomicrmw_fadd_f64_global_unsafe(double addrspace(1)* %ptr,
; GFX9-NEXT: ret double [[TMP6]]
;
; GFX908-LABEL: @test_atomicrmw_fadd_f64_global_unsafe(
-; GFX908-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8
+; GFX908-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX908-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; GFX908-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)*
; GFX908-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GFX908-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8
+; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GFX908-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -182,23 +174,22 @@ define double @test_atomicrmw_fadd_f64_global_unsafe(double addrspace(1)* %ptr,
; GFX908-NEXT: ret double [[TMP6]]
;
; GFX90A-LABEL: @test_atomicrmw_fadd_f64_global_unsafe(
-; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd double addrspace(1)* [[PTR:%.*]], double [[VALUE:%.*]] syncscope("wavefront") monotonic, align 8
+; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], double [[VALUE:%.*]] syncscope("wavefront") monotonic, align 8
; GFX90A-NEXT: ret double [[RES]]
;
; GFX940-LABEL: @test_atomicrmw_fadd_f64_global_unsafe(
-; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd double addrspace(1)* [[PTR:%.*]], double [[VALUE:%.*]] syncscope("wavefront") monotonic, align 8
+; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], double [[VALUE:%.*]] syncscope("wavefront") monotonic, align 8
; GFX940-NEXT: ret double [[RES]]
;
; GFX11-LABEL: @test_atomicrmw_fadd_f64_global_unsafe(
-; GFX11-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8
+; GFX11-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8
; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX11: atomicrmw.start:
; GFX11-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX11-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; GFX11-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)*
; GFX11-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GFX11-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8
+; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8
; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GFX11-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -206,21 +197,20 @@ define double @test_atomicrmw_fadd_f64_global_unsafe(double addrspace(1)* %ptr,
; GFX11: atomicrmw.end:
; GFX11-NEXT: ret double [[TMP6]]
;
- %res = atomicrmw fadd double addrspace(1)* %ptr, double %value syncscope("wavefront") monotonic
+ %res = atomicrmw fadd ptr addrspace(1) %ptr, double %value syncscope("wavefront") monotonic
ret double %res
}
-define float @test_atomicrmw_fadd_f32_flat_unsafe(float* %ptr, float %value) #0 {
+define float @test_atomicrmw_fadd_f32_flat_unsafe(ptr %ptr, float %value) #0 {
; CI-LABEL: @test_atomicrmw_fadd_f32_flat_unsafe(
-; CI-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; CI-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; CI-NEXT: br label [[ATOMICRMW_START:%.*]]
; CI: atomicrmw.start:
; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CI-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4
+; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4
; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -229,15 +219,14 @@ define float @test_atomicrmw_fadd_f32_flat_unsafe(float* %ptr, float %value) #0
; CI-NEXT: ret float [[TMP6]]
;
; GFX9-LABEL: @test_atomicrmw_fadd_f32_flat_unsafe(
-; GFX9-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; GFX9-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX9: atomicrmw.start:
; GFX9-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX9-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX9-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX9-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4
+; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4
; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX9-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -246,15 +235,14 @@ define float @test_atomicrmw_fadd_f32_flat_unsafe(float* %ptr, float %value) #0
; GFX9-NEXT: ret float [[TMP6]]
;
; GFX908-LABEL: @test_atomicrmw_fadd_f32_flat_unsafe(
-; GFX908-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX908-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4
+; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -263,27 +251,26 @@ define float @test_atomicrmw_fadd_f32_flat_unsafe(float* %ptr, float %value) #0
; GFX908-NEXT: ret float [[TMP6]]
;
; GFX90A-LABEL: @test_atomicrmw_fadd_f32_flat_unsafe(
-; GFX90A-NEXT: [[TMP1:%.*]] = bitcast float* [[PTR:%.*]] to i8*
; GFX90A-NEXT: br label [[ATOMICRMW_CHECK_SHARED:%.*]]
; GFX90A: atomicrmw.check.shared:
-; GFX90A-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(i8* [[TMP1]])
+; GFX90A-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[PTR:%.*]])
; GFX90A-NEXT: br i1 [[IS_SHARED]], label [[ATOMICRMW_SHARED:%.*]], label [[ATOMICRMW_CHECK_PRIVATE:%.*]]
; GFX90A: atomicrmw.shared:
-; GFX90A-NEXT: [[TMP2:%.*]] = addrspacecast float* [[PTR]] to float addrspace(3)*
-; GFX90A-NEXT: [[TMP3:%.*]] = atomicrmw fadd float addrspace(3)* [[TMP2]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
+; GFX90A-NEXT: [[TMP2:%.*]] = addrspacecast ptr [[PTR]] to ptr addrspace(3)
+; GFX90A-NEXT: [[TMP3:%.*]] = atomicrmw fadd ptr addrspace(3) [[TMP2]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
; GFX90A-NEXT: br label [[ATOMICRMW_PHI:%.*]]
; GFX90A: atomicrmw.check.private:
-; GFX90A-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(i8* [[TMP1]])
+; GFX90A-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[PTR]])
; GFX90A-NEXT: br i1 [[IS_PRIVATE]], label [[ATOMICRMW_PRIVATE:%.*]], label [[ATOMICRMW_GLOBAL:%.*]]
; GFX90A: atomicrmw.private:
-; GFX90A-NEXT: [[TMP4:%.*]] = addrspacecast float* [[PTR]] to float addrspace(5)*
-; GFX90A-NEXT: [[LOADED_PRIVATE:%.*]] = load float, float addrspace(5)* [[TMP4]], align 4
+; GFX90A-NEXT: [[TMP4:%.*]] = addrspacecast ptr [[PTR]] to ptr addrspace(5)
+; GFX90A-NEXT: [[LOADED_PRIVATE:%.*]] = load float, ptr addrspace(5) [[TMP4]], align 4
; GFX90A-NEXT: [[VAL_NEW:%.*]] = fadd float [[LOADED_PRIVATE]], [[VALUE]]
-; GFX90A-NEXT: store float [[VAL_NEW]], float addrspace(5)* [[TMP4]], align 4
+; GFX90A-NEXT: store float [[VAL_NEW]], ptr addrspace(5) [[TMP4]], align 4
; GFX90A-NEXT: br label [[ATOMICRMW_PHI]]
; GFX90A: atomicrmw.global:
-; GFX90A-NEXT: [[TMP5:%.*]] = addrspacecast float* [[PTR]] to float addrspace(1)*
-; GFX90A-NEXT: [[TMP6:%.*]] = atomicrmw fadd float addrspace(1)* [[TMP5]], float [[VALUE]] syncscope("wavefront") monotonic, align 4
+; GFX90A-NEXT: [[TMP5:%.*]] = addrspacecast ptr [[PTR]] to ptr addrspace(1)
+; GFX90A-NEXT: [[TMP6:%.*]] = atomicrmw fadd ptr addrspace(1) [[TMP5]], float [[VALUE]] syncscope("wavefront") monotonic, align 4
; GFX90A-NEXT: br label [[ATOMICRMW_PHI]]
; GFX90A: atomicrmw.phi:
; GFX90A-NEXT: [[LOADED_PHI:%.*]] = phi float [ [[TMP3]], [[ATOMICRMW_SHARED]] ], [ [[LOADED_PRIVATE]], [[ATOMICRMW_PRIVATE]] ], [ [[TMP6]], [[ATOMICRMW_GLOBAL]] ]
@@ -292,28 +279,27 @@ define float @test_atomicrmw_fadd_f32_flat_unsafe(float* %ptr, float %value) #0
; GFX90A-NEXT: ret float [[LOADED_PHI]]
;
; GFX940-LABEL: @test_atomicrmw_fadd_f32_flat_unsafe(
-; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd float* [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
+; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd ptr [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
; GFX940-NEXT: ret float [[RES]]
;
; GFX11-LABEL: @test_atomicrmw_fadd_f32_flat_unsafe(
-; GFX11-NEXT: [[RES:%.*]] = atomicrmw fadd float* [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
+; GFX11-NEXT: [[RES:%.*]] = atomicrmw fadd ptr [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4
; GFX11-NEXT: ret float [[RES]]
;
- %res = atomicrmw fadd float* %ptr, float %value syncscope("wavefront") monotonic
+ %res = atomicrmw fadd ptr %ptr, float %value syncscope("wavefront") monotonic
ret float %res
}
-define double @test_atomicrmw_fadd_f64_flat_unsafe(double* %ptr, double %value) #0 {
+define double @test_atomicrmw_fadd_f64_flat_unsafe(ptr %ptr, double %value) #0 {
; CI-LABEL: @test_atomicrmw_fadd_f64_flat_unsafe(
-; CI-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8
+; CI-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8
; CI-NEXT: br label [[ATOMICRMW_START:%.*]]
; CI: atomicrmw.start:
; CI-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CI-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; CI-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64*
; CI-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; CI-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; CI-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8
+; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8
; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; CI-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -322,15 +308,14 @@ define double @test_atomicrmw_fadd_f64_flat_unsafe(double* %ptr, double %value)
; CI-NEXT: ret double [[TMP6]]
;
; GFX9-LABEL: @test_atomicrmw_fadd_f64_flat_unsafe(
-; GFX9-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8
+; GFX9-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8
; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX9: atomicrmw.start:
; GFX9-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX9-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; GFX9-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64*
; GFX9-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GFX9-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8
+; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8
; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GFX9-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -339,15 +324,14 @@ define double @test_atomicrmw_fadd_f64_flat_unsafe(double* %ptr, double %value)
; GFX9-NEXT: ret double [[TMP6]]
;
; GFX908-LABEL: @test_atomicrmw_fadd_f64_flat_unsafe(
-; GFX908-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8
+; GFX908-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX908-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; GFX908-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64*
; GFX908-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GFX908-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8
+; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GFX908-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -356,23 +340,22 @@ define double @test_atomicrmw_fadd_f64_flat_unsafe(double* %ptr, double %value)
; GFX908-NEXT: ret double [[TMP6]]
;
; GFX90A-LABEL: @test_atomicrmw_fadd_f64_flat_unsafe(
-; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd double* [[PTR:%.*]], double [[VALUE:%.*]] syncscope("wavefront") monotonic, align 8
+; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd ptr [[PTR:%.*]], double [[VALUE:%.*]] syncscope("wavefront") monotonic, align 8
; GFX90A-NEXT: ret double [[RES]]
;
; GFX940-LABEL: @test_atomicrmw_fadd_f64_flat_unsafe(
-; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd double* [[PTR:%.*]], double [[VALUE:%.*]] syncscope("wavefront") monotonic, align 8
+; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd ptr [[PTR:%.*]], double [[VALUE:%.*]] syncscope("wavefront") monotonic, align 8
; GFX940-NEXT: ret double [[RES]]
;
; GFX11-LABEL: @test_atomicrmw_fadd_f64_flat_unsafe(
-; GFX11-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8
+; GFX11-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8
; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX11: atomicrmw.start:
; GFX11-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX11-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; GFX11-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64*
; GFX11-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GFX11-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8
+; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8
; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GFX11-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -380,21 +363,20 @@ define double @test_atomicrmw_fadd_f64_flat_unsafe(double* %ptr, double %value)
; GFX11: atomicrmw.end:
; GFX11-NEXT: ret double [[TMP6]]
;
- %res = atomicrmw fadd double* %ptr, double %value syncscope("wavefront") monotonic
+ %res = atomicrmw fadd ptr %ptr, double %value syncscope("wavefront") monotonic
ret double %res
}
-define float @test_atomicrmw_fadd_f32_flat(float* %ptr, float %value) {
+define float @test_atomicrmw_fadd_f32_flat(ptr %ptr, float %value) {
; CI-LABEL: @test_atomicrmw_fadd_f32_flat(
-; CI-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; CI-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; CI-NEXT: br label [[ATOMICRMW_START:%.*]]
; CI: atomicrmw.start:
; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CI-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -403,15 +385,14 @@ define float @test_atomicrmw_fadd_f32_flat(float* %ptr, float %value) {
; CI-NEXT: ret float [[TMP6]]
;
; GFX9-LABEL: @test_atomicrmw_fadd_f32_flat(
-; GFX9-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; GFX9-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX9: atomicrmw.start:
; GFX9-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX9-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX9-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX9-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX9-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -420,15 +401,14 @@ define float @test_atomicrmw_fadd_f32_flat(float* %ptr, float %value) {
; GFX9-NEXT: ret float [[TMP6]]
;
; GFX908-LABEL: @test_atomicrmw_fadd_f32_flat(
-; GFX908-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX908-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -437,15 +417,14 @@ define float @test_atomicrmw_fadd_f32_flat(float* %ptr, float %value) {
; GFX908-NEXT: ret float [[TMP6]]
;
; GFX90A-LABEL: @test_atomicrmw_fadd_f32_flat(
-; GFX90A-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; GFX90A-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX90A: atomicrmw.start:
; GFX90A-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX90A-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX90A-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; GFX90A-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX90A-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX90A-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -454,15 +433,14 @@ define float @test_atomicrmw_fadd_f32_flat(float* %ptr, float %value) {
; GFX90A-NEXT: ret float [[TMP6]]
;
; GFX940-LABEL: @test_atomicrmw_fadd_f32_flat(
-; GFX940-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; GFX940-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX940: atomicrmw.start:
; GFX940-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX940-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX940-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; GFX940-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX940-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX940-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -471,15 +449,14 @@ define float @test_atomicrmw_fadd_f32_flat(float* %ptr, float %value) {
; GFX940-NEXT: ret float [[TMP6]]
;
; GFX11-LABEL: @test_atomicrmw_fadd_f32_flat(
-; GFX11-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX11: atomicrmw.start:
; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX11-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -487,21 +464,20 @@ define float @test_atomicrmw_fadd_f32_flat(float* %ptr, float %value) {
; GFX11: atomicrmw.end:
; GFX11-NEXT: ret float [[TMP6]]
;
- %res = atomicrmw fadd float* %ptr, float %value seq_cst
+ %res = atomicrmw fadd ptr %ptr, float %value seq_cst
ret float %res
}
-define float @test_atomicrmw_fadd_f32_global(float addrspace(1)* %ptr, float %value) {
+define float @test_atomicrmw_fadd_f32_global(ptr addrspace(1) %ptr, float %value) {
; CI-LABEL: @test_atomicrmw_fadd_f32_global(
-; CI-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; CI-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; CI-NEXT: br label [[ATOMICRMW_START:%.*]]
; CI: atomicrmw.start:
; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CI-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -510,15 +486,14 @@ define float @test_atomicrmw_fadd_f32_global(float addrspace(1)* %ptr, float %va
; CI-NEXT: ret float [[TMP6]]
;
; GFX9-LABEL: @test_atomicrmw_fadd_f32_global(
-; GFX9-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX9-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX9: atomicrmw.start:
; GFX9-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX9-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX9-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX9-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX9-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -527,15 +502,14 @@ define float @test_atomicrmw_fadd_f32_global(float addrspace(1)* %ptr, float %va
; GFX9-NEXT: ret float [[TMP6]]
;
; GFX908-LABEL: @test_atomicrmw_fadd_f32_global(
-; GFX908-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX908-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -544,15 +518,14 @@ define float @test_atomicrmw_fadd_f32_global(float addrspace(1)* %ptr, float %va
; GFX908-NEXT: ret float [[TMP6]]
;
; GFX90A-LABEL: @test_atomicrmw_fadd_f32_global(
-; GFX90A-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX90A-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX90A: atomicrmw.start:
; GFX90A-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX90A-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX90A-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX90A-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX90A-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX90A-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -561,15 +534,14 @@ define float @test_atomicrmw_fadd_f32_global(float addrspace(1)* %ptr, float %va
; GFX90A-NEXT: ret float [[TMP6]]
;
; GFX940-LABEL: @test_atomicrmw_fadd_f32_global(
-; GFX940-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX940-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX940: atomicrmw.start:
; GFX940-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX940-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX940-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX940-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX940-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX940-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -578,15 +550,14 @@ define float @test_atomicrmw_fadd_f32_global(float addrspace(1)* %ptr, float %va
; GFX940-NEXT: ret float [[TMP6]]
;
; GFX11-LABEL: @test_atomicrmw_fadd_f32_global(
-; GFX11-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX11: atomicrmw.start:
; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX11-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -594,21 +565,20 @@ define float @test_atomicrmw_fadd_f32_global(float addrspace(1)* %ptr, float %va
; GFX11: atomicrmw.end:
; GFX11-NEXT: ret float [[TMP6]]
;
- %res = atomicrmw fadd float addrspace(1)* %ptr, float %value seq_cst
+ %res = atomicrmw fadd ptr addrspace(1) %ptr, float %value seq_cst
ret float %res
}
-define void @test_atomicrmw_fadd_f32_global_no_use_ieee(float addrspace(1)* %ptr, float %value) {
+define void @test_atomicrmw_fadd_f32_global_no_use_ieee(ptr addrspace(1) %ptr, float %value) {
; CI-LABEL: @test_atomicrmw_fadd_f32_global_no_use_ieee(
-; CI-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; CI-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; CI-NEXT: br label [[ATOMICRMW_START:%.*]]
; CI: atomicrmw.start:
; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CI-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -617,15 +587,14 @@ define void @test_atomicrmw_fadd_f32_global_no_use_ieee(float addrspace(1)* %ptr
; CI-NEXT: ret void
;
; GFX9-LABEL: @test_atomicrmw_fadd_f32_global_no_use_ieee(
-; GFX9-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX9-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX9: atomicrmw.start:
; GFX9-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX9-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX9-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX9-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX9-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -634,15 +603,14 @@ define void @test_atomicrmw_fadd_f32_global_no_use_ieee(float addrspace(1)* %ptr
; GFX9-NEXT: ret void
;
; GFX908-LABEL: @test_atomicrmw_fadd_f32_global_no_use_ieee(
-; GFX908-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX908-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -651,15 +619,14 @@ define void @test_atomicrmw_fadd_f32_global_no_use_ieee(float addrspace(1)* %ptr
; GFX908-NEXT: ret void
;
; GFX90A-LABEL: @test_atomicrmw_fadd_f32_global_no_use_ieee(
-; GFX90A-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX90A-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX90A: atomicrmw.start:
; GFX90A-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX90A-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX90A-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX90A-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX90A-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX90A-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -668,15 +635,14 @@ define void @test_atomicrmw_fadd_f32_global_no_use_ieee(float addrspace(1)* %ptr
; GFX90A-NEXT: ret void
;
; GFX940-LABEL: @test_atomicrmw_fadd_f32_global_no_use_ieee(
-; GFX940-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX940-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX940: atomicrmw.start:
; GFX940-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX940-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX940-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX940-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX940-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX940-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -685,15 +651,14 @@ define void @test_atomicrmw_fadd_f32_global_no_use_ieee(float addrspace(1)* %ptr
; GFX940-NEXT: ret void
;
; GFX11-LABEL: @test_atomicrmw_fadd_f32_global_no_use_ieee(
-; GFX11-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX11: atomicrmw.start:
; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX11-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -701,21 +666,20 @@ define void @test_atomicrmw_fadd_f32_global_no_use_ieee(float addrspace(1)* %ptr
; GFX11: atomicrmw.end:
; GFX11-NEXT: ret void
;
- %res = atomicrmw fadd float addrspace(1)* %ptr, float %value seq_cst
+ %res = atomicrmw fadd ptr addrspace(1) %ptr, float %value seq_cst
ret void
}
-define void @test_atomicrmw_fadd_f32_global_no_use_denorm_flush(float addrspace(1)* %ptr, float %value) #0 {
+define void @test_atomicrmw_fadd_f32_global_no_use_denorm_flush(ptr addrspace(1) %ptr, float %value) #0 {
; CI-LABEL: @test_atomicrmw_fadd_f32_global_no_use_denorm_flush(
-; CI-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; CI-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; CI-NEXT: br label [[ATOMICRMW_START:%.*]]
; CI: atomicrmw.start:
; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CI-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -724,15 +688,14 @@ define void @test_atomicrmw_fadd_f32_global_no_use_denorm_flush(float addrspace(
; CI-NEXT: ret void
;
; GFX9-LABEL: @test_atomicrmw_fadd_f32_global_no_use_denorm_flush(
-; GFX9-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX9-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX9: atomicrmw.start:
; GFX9-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX9-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX9-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX9-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX9-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -741,15 +704,14 @@ define void @test_atomicrmw_fadd_f32_global_no_use_denorm_flush(float addrspace(
; GFX9-NEXT: ret void
;
; GFX908-LABEL: @test_atomicrmw_fadd_f32_global_no_use_denorm_flush(
-; GFX908-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX908-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -758,15 +720,14 @@ define void @test_atomicrmw_fadd_f32_global_no_use_denorm_flush(float addrspace(
; GFX908-NEXT: ret void
;
; GFX90A-LABEL: @test_atomicrmw_fadd_f32_global_no_use_denorm_flush(
-; GFX90A-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX90A-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX90A: atomicrmw.start:
; GFX90A-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX90A-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX90A-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX90A-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX90A-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX90A-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -775,15 +736,14 @@ define void @test_atomicrmw_fadd_f32_global_no_use_denorm_flush(float addrspace(
; GFX90A-NEXT: ret void
;
; GFX940-LABEL: @test_atomicrmw_fadd_f32_global_no_use_denorm_flush(
-; GFX940-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX940-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX940: atomicrmw.start:
; GFX940-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX940-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX940-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX940-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX940-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX940-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -792,15 +752,14 @@ define void @test_atomicrmw_fadd_f32_global_no_use_denorm_flush(float addrspace(
; GFX940-NEXT: ret void
;
; GFX11-LABEL: @test_atomicrmw_fadd_f32_global_no_use_denorm_flush(
-; GFX11-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX11: atomicrmw.start:
; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX11-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -808,21 +767,20 @@ define void @test_atomicrmw_fadd_f32_global_no_use_denorm_flush(float addrspace(
; GFX11: atomicrmw.end:
; GFX11-NEXT: ret void
;
- %res = atomicrmw fadd float addrspace(1)* %ptr, float %value seq_cst
+ %res = atomicrmw fadd ptr addrspace(1) %ptr, float %value seq_cst
ret void
}
-define float @test_atomicrmw_fadd_f32_local(float addrspace(3)* %ptr, float %value) {
+define float @test_atomicrmw_fadd_f32_local(ptr addrspace(3) %ptr, float %value) {
; CI-LABEL: @test_atomicrmw_fadd_f32_local(
-; CI-NEXT: [[TMP1:%.*]] = load float, float addrspace(3)* [[PTR:%.*]], align 4
+; CI-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(3) [[PTR:%.*]], align 4
; CI-NEXT: br label [[ATOMICRMW_START:%.*]]
; CI: atomicrmw.start:
; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CI-NEXT: [[TMP2:%.*]] = bitcast float addrspace(3)* [[PTR]] to i32 addrspace(3)*
; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(3)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -831,40 +789,39 @@ define float @test_atomicrmw_fadd_f32_local(float addrspace(3)* %ptr, float %val
; CI-NEXT: ret float [[TMP6]]
;
; GFX9-LABEL: @test_atomicrmw_fadd_f32_local(
-; GFX9-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(3)* [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4
+; GFX9-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(3) [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4
; GFX9-NEXT: ret float [[RES]]
;
; GFX908-LABEL: @test_atomicrmw_fadd_f32_local(
-; GFX908-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(3)* [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4
+; GFX908-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(3) [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4
; GFX908-NEXT: ret float [[RES]]
;
; GFX90A-LABEL: @test_atomicrmw_fadd_f32_local(
-; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(3)* [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4
+; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(3) [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4
; GFX90A-NEXT: ret float [[RES]]
;
; GFX940-LABEL: @test_atomicrmw_fadd_f32_local(
-; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(3)* [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4
+; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(3) [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4
; GFX940-NEXT: ret float [[RES]]
;
; GFX11-LABEL: @test_atomicrmw_fadd_f32_local(
-; GFX11-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(3)* [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4
+; GFX11-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(3) [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4
; GFX11-NEXT: ret float [[RES]]
;
- %res = atomicrmw fadd float addrspace(3)* %ptr, float %value seq_cst
+ %res = atomicrmw fadd ptr addrspace(3) %ptr, float %value seq_cst
ret float %res
}
-define half @test_atomicrmw_fadd_f16_flat(half* %ptr, half %value) {
+define half @test_atomicrmw_fadd_f16_flat(ptr %ptr, half %value) {
; CI-LABEL: @test_atomicrmw_fadd_f16_flat(
-; CI-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4)
-; CI-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64
+; CI-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4)
+; CI-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64
; CI-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CI-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CI-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CI-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CI-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CI-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32*
-; CI-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4
+; CI-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4
; CI-NEXT: br label [[ATOMICRMW_START:%.*]]
; CI: atomicrmw.start:
; CI-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -877,7 +834,7 @@ define half @test_atomicrmw_fadd_f16_flat(half* %ptr, half %value) {
; CI-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; CI-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CI-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; CI-NEXT: [[TMP6:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; CI-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; CI-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; CI-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -888,15 +845,14 @@ define half @test_atomicrmw_fadd_f16_flat(half* %ptr, half %value) {
; CI-NEXT: ret half [[TMP7]]
;
; GFX9-LABEL: @test_atomicrmw_fadd_f16_flat(
-; GFX9-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4)
-; GFX9-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64
+; GFX9-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4)
+; GFX9-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64
; GFX9-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GFX9-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GFX9-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GFX9-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GFX9-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GFX9-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32*
-; GFX9-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4
+; GFX9-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4
; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX9: atomicrmw.start:
; GFX9-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -909,7 +865,7 @@ define half @test_atomicrmw_fadd_f16_flat(half* %ptr, half %value) {
; GFX9-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GFX9-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GFX9-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GFX9-NEXT: [[TMP6:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX9-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GFX9-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; GFX9-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -920,15 +876,14 @@ define half @test_atomicrmw_fadd_f16_flat(half* %ptr, half %value) {
; GFX9-NEXT: ret half [[TMP7]]
;
; GFX908-LABEL: @test_atomicrmw_fadd_f16_flat(
-; GFX908-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4)
-; GFX908-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64
+; GFX908-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4)
+; GFX908-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64
; GFX908-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GFX908-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GFX908-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GFX908-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GFX908-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GFX908-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32*
-; GFX908-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4
+; GFX908-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -941,7 +896,7 @@ define half @test_atomicrmw_fadd_f16_flat(half* %ptr, half %value) {
; GFX908-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GFX908-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GFX908-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GFX908-NEXT: [[TMP6:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX908-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GFX908-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; GFX908-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -952,15 +907,14 @@ define half @test_atomicrmw_fadd_f16_flat(half* %ptr, half %value) {
; GFX908-NEXT: ret half [[TMP7]]
;
; GFX90A-LABEL: @test_atomicrmw_fadd_f16_flat(
-; GFX90A-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4)
-; GFX90A-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64
+; GFX90A-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4)
+; GFX90A-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64
; GFX90A-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GFX90A-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GFX90A-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GFX90A-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GFX90A-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GFX90A-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32*
-; GFX90A-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4
+; GFX90A-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4
; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX90A: atomicrmw.start:
; GFX90A-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -973,7 +927,7 @@ define half @test_atomicrmw_fadd_f16_flat(half* %ptr, half %value) {
; GFX90A-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GFX90A-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GFX90A-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GFX90A-NEXT: [[TMP6:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX90A-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GFX90A-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; GFX90A-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -984,15 +938,14 @@ define half @test_atomicrmw_fadd_f16_flat(half* %ptr, half %value) {
; GFX90A-NEXT: ret half [[TMP7]]
;
; GFX940-LABEL: @test_atomicrmw_fadd_f16_flat(
-; GFX940-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4)
-; GFX940-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64
+; GFX940-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4)
+; GFX940-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64
; GFX940-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GFX940-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GFX940-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GFX940-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GFX940-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GFX940-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32*
-; GFX940-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4
+; GFX940-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4
; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX940: atomicrmw.start:
; GFX940-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1005,7 +958,7 @@ define half @test_atomicrmw_fadd_f16_flat(half* %ptr, half %value) {
; GFX940-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GFX940-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GFX940-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GFX940-NEXT: [[TMP6:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX940-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GFX940-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; GFX940-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1016,15 +969,14 @@ define half @test_atomicrmw_fadd_f16_flat(half* %ptr, half %value) {
; GFX940-NEXT: ret half [[TMP7]]
;
; GFX11-LABEL: @test_atomicrmw_fadd_f16_flat(
-; GFX11-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4)
-; GFX11-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64
+; GFX11-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4)
+; GFX11-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64
; GFX11-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GFX11-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GFX11-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GFX11-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GFX11-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GFX11-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32*
-; GFX11-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4
+; GFX11-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4
; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX11: atomicrmw.start:
; GFX11-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1037,7 +989,7 @@ define half @test_atomicrmw_fadd_f16_flat(half* %ptr, half %value) {
; GFX11-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GFX11-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GFX11-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GFX11-NEXT: [[TMP6:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX11-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GFX11-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; GFX11-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1047,21 +999,20 @@ define half @test_atomicrmw_fadd_f16_flat(half* %ptr, half %value) {
; GFX11-NEXT: [[TMP7:%.*]] = bitcast i16 [[EXTRACTED4]] to half
; GFX11-NEXT: ret half [[TMP7]]
;
- %res = atomicrmw fadd half* %ptr, half %value seq_cst
+ %res = atomicrmw fadd ptr %ptr, half %value seq_cst
ret half %res
}
-define half @test_atomicrmw_fadd_f16_global(half addrspace(1)* %ptr, half %value) {
+define half @test_atomicrmw_fadd_f16_global(ptr addrspace(1) %ptr, half %value) {
; CI-LABEL: @test_atomicrmw_fadd_f16_global(
-; CI-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(1)* @llvm.ptrmask.p1f16.i64(half addrspace(1)* [[PTR:%.*]], i64 -4)
-; CI-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(1)* [[PTR]] to i64
+; CI-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; CI-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; CI-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CI-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CI-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CI-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CI-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CI-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
-; CI-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; CI-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; CI-NEXT: br label [[ATOMICRMW_START:%.*]]
; CI: atomicrmw.start:
; CI-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1074,7 +1025,7 @@ define half @test_atomicrmw_fadd_f16_global(half addrspace(1)* %ptr, half %value
; CI-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; CI-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CI-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; CI-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; CI-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; CI-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; CI-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1085,15 +1036,14 @@ define half @test_atomicrmw_fadd_f16_global(half addrspace(1)* %ptr, half %value
; CI-NEXT: ret half [[TMP7]]
;
; GFX9-LABEL: @test_atomicrmw_fadd_f16_global(
-; GFX9-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(1)* @llvm.ptrmask.p1f16.i64(half addrspace(1)* [[PTR:%.*]], i64 -4)
-; GFX9-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(1)* [[PTR]] to i64
+; GFX9-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; GFX9-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; GFX9-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GFX9-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GFX9-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GFX9-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GFX9-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GFX9-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
-; GFX9-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; GFX9-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX9: atomicrmw.start:
; GFX9-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1106,7 +1056,7 @@ define half @test_atomicrmw_fadd_f16_global(half addrspace(1)* %ptr, half %value
; GFX9-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GFX9-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GFX9-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GFX9-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX9-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GFX9-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; GFX9-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1117,15 +1067,14 @@ define half @test_atomicrmw_fadd_f16_global(half addrspace(1)* %ptr, half %value
; GFX9-NEXT: ret half [[TMP7]]
;
; GFX908-LABEL: @test_atomicrmw_fadd_f16_global(
-; GFX908-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(1)* @llvm.ptrmask.p1f16.i64(half addrspace(1)* [[PTR:%.*]], i64 -4)
-; GFX908-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(1)* [[PTR]] to i64
+; GFX908-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; GFX908-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; GFX908-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GFX908-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GFX908-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GFX908-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GFX908-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GFX908-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
-; GFX908-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; GFX908-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1138,7 +1087,7 @@ define half @test_atomicrmw_fadd_f16_global(half addrspace(1)* %ptr, half %value
; GFX908-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GFX908-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GFX908-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GFX908-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX908-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GFX908-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; GFX908-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1149,15 +1098,14 @@ define half @test_atomicrmw_fadd_f16_global(half addrspace(1)* %ptr, half %value
; GFX908-NEXT: ret half [[TMP7]]
;
; GFX90A-LABEL: @test_atomicrmw_fadd_f16_global(
-; GFX90A-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(1)* @llvm.ptrmask.p1f16.i64(half addrspace(1)* [[PTR:%.*]], i64 -4)
-; GFX90A-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(1)* [[PTR]] to i64
+; GFX90A-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; GFX90A-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; GFX90A-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GFX90A-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GFX90A-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GFX90A-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GFX90A-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GFX90A-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
-; GFX90A-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; GFX90A-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX90A: atomicrmw.start:
; GFX90A-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1170,7 +1118,7 @@ define half @test_atomicrmw_fadd_f16_global(half addrspace(1)* %ptr, half %value
; GFX90A-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GFX90A-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GFX90A-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GFX90A-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX90A-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GFX90A-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; GFX90A-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1181,15 +1129,14 @@ define half @test_atomicrmw_fadd_f16_global(half addrspace(1)* %ptr, half %value
; GFX90A-NEXT: ret half [[TMP7]]
;
; GFX940-LABEL: @test_atomicrmw_fadd_f16_global(
-; GFX940-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(1)* @llvm.ptrmask.p1f16.i64(half addrspace(1)* [[PTR:%.*]], i64 -4)
-; GFX940-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(1)* [[PTR]] to i64
+; GFX940-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; GFX940-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; GFX940-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GFX940-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GFX940-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GFX940-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GFX940-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GFX940-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
-; GFX940-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; GFX940-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX940: atomicrmw.start:
; GFX940-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1202,7 +1149,7 @@ define half @test_atomicrmw_fadd_f16_global(half addrspace(1)* %ptr, half %value
; GFX940-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GFX940-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GFX940-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GFX940-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX940-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GFX940-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; GFX940-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1213,15 +1160,14 @@ define half @test_atomicrmw_fadd_f16_global(half addrspace(1)* %ptr, half %value
; GFX940-NEXT: ret half [[TMP7]]
;
; GFX11-LABEL: @test_atomicrmw_fadd_f16_global(
-; GFX11-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(1)* @llvm.ptrmask.p1f16.i64(half addrspace(1)* [[PTR:%.*]], i64 -4)
-; GFX11-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(1)* [[PTR]] to i64
+; GFX11-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; GFX11-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; GFX11-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GFX11-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GFX11-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GFX11-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GFX11-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GFX11-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
-; GFX11-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; GFX11-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX11: atomicrmw.start:
; GFX11-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1234,7 +1180,7 @@ define half @test_atomicrmw_fadd_f16_global(half addrspace(1)* %ptr, half %value
; GFX11-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GFX11-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GFX11-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GFX11-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX11-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GFX11-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; GFX11-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1244,14 +1190,13 @@ define half @test_atomicrmw_fadd_f16_global(half addrspace(1)* %ptr, half %value
; GFX11-NEXT: [[TMP7:%.*]] = bitcast i16 [[EXTRACTED4]] to half
; GFX11-NEXT: ret half [[TMP7]]
;
- %res = atomicrmw fadd half addrspace(1)* %ptr, half %value seq_cst
+ %res = atomicrmw fadd ptr addrspace(1) %ptr, half %value seq_cst
ret half %res
}
-define half @test_atomicrmw_fadd_f16_global_align4(half addrspace(1)* %ptr, half %value) {
+define half @test_atomicrmw_fadd_f16_global_align4(ptr addrspace(1) %ptr, half %value) {
; CI-LABEL: @test_atomicrmw_fadd_f16_global_align4(
-; CI-NEXT: [[ALIGNEDADDR:%.*]] = bitcast half addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)*
-; CI-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4
+; CI-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4
; CI-NEXT: br label [[ATOMICRMW_START:%.*]]
; CI: atomicrmw.start:
; CI-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1262,7 +1207,7 @@ define half @test_atomicrmw_fadd_f16_global_align4(half addrspace(1)* %ptr, half
; CI-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP3]] to i32
; CI-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], -65536
; CI-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[EXTENDED]]
-; CI-NEXT: [[TMP4:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; CI-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1
; CI-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP4]], 0
; CI-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1272,8 +1217,7 @@ define half @test_atomicrmw_fadd_f16_global_align4(half addrspace(1)* %ptr, half
; CI-NEXT: ret half [[TMP5]]
;
; GFX9-LABEL: @test_atomicrmw_fadd_f16_global_align4(
-; GFX9-NEXT: [[ALIGNEDADDR:%.*]] = bitcast half addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)*
-; GFX9-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4
+; GFX9-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX9: atomicrmw.start:
; GFX9-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1284,7 +1228,7 @@ define half @test_atomicrmw_fadd_f16_global_align4(half addrspace(1)* %ptr, half
; GFX9-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP3]] to i32
; GFX9-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], -65536
; GFX9-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[EXTENDED]]
-; GFX9-NEXT: [[TMP4:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX9-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1
; GFX9-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP4]], 0
; GFX9-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1294,8 +1238,7 @@ define half @test_atomicrmw_fadd_f16_global_align4(half addrspace(1)* %ptr, half
; GFX9-NEXT: ret half [[TMP5]]
;
; GFX908-LABEL: @test_atomicrmw_fadd_f16_global_align4(
-; GFX908-NEXT: [[ALIGNEDADDR:%.*]] = bitcast half addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)*
-; GFX908-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4
+; GFX908-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1306,7 +1249,7 @@ define half @test_atomicrmw_fadd_f16_global_align4(half addrspace(1)* %ptr, half
; GFX908-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP3]] to i32
; GFX908-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], -65536
; GFX908-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[EXTENDED]]
-; GFX908-NEXT: [[TMP4:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX908-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1
; GFX908-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP4]], 0
; GFX908-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1316,8 +1259,7 @@ define half @test_atomicrmw_fadd_f16_global_align4(half addrspace(1)* %ptr, half
; GFX908-NEXT: ret half [[TMP5]]
;
; GFX90A-LABEL: @test_atomicrmw_fadd_f16_global_align4(
-; GFX90A-NEXT: [[ALIGNEDADDR:%.*]] = bitcast half addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)*
-; GFX90A-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4
+; GFX90A-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX90A: atomicrmw.start:
; GFX90A-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1328,7 +1270,7 @@ define half @test_atomicrmw_fadd_f16_global_align4(half addrspace(1)* %ptr, half
; GFX90A-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP3]] to i32
; GFX90A-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], -65536
; GFX90A-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[EXTENDED]]
-; GFX90A-NEXT: [[TMP4:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX90A-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1
; GFX90A-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP4]], 0
; GFX90A-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1338,8 +1280,7 @@ define half @test_atomicrmw_fadd_f16_global_align4(half addrspace(1)* %ptr, half
; GFX90A-NEXT: ret half [[TMP5]]
;
; GFX940-LABEL: @test_atomicrmw_fadd_f16_global_align4(
-; GFX940-NEXT: [[ALIGNEDADDR:%.*]] = bitcast half addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)*
-; GFX940-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4
+; GFX940-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX940: atomicrmw.start:
; GFX940-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1350,7 +1291,7 @@ define half @test_atomicrmw_fadd_f16_global_align4(half addrspace(1)* %ptr, half
; GFX940-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP3]] to i32
; GFX940-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], -65536
; GFX940-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[EXTENDED]]
-; GFX940-NEXT: [[TMP4:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX940-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1
; GFX940-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP4]], 0
; GFX940-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1360,8 +1301,7 @@ define half @test_atomicrmw_fadd_f16_global_align4(half addrspace(1)* %ptr, half
; GFX940-NEXT: ret half [[TMP5]]
;
; GFX11-LABEL: @test_atomicrmw_fadd_f16_global_align4(
-; GFX11-NEXT: [[ALIGNEDADDR:%.*]] = bitcast half addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)*
-; GFX11-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4
+; GFX11-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX11: atomicrmw.start:
; GFX11-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1372,7 +1312,7 @@ define half @test_atomicrmw_fadd_f16_global_align4(half addrspace(1)* %ptr, half
; GFX11-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP3]] to i32
; GFX11-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], -65536
; GFX11-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[EXTENDED]]
-; GFX11-NEXT: [[TMP4:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX11-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1
; GFX11-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP4]], 0
; GFX11-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1381,21 +1321,20 @@ define half @test_atomicrmw_fadd_f16_global_align4(half addrspace(1)* %ptr, half
; GFX11-NEXT: [[TMP5:%.*]] = bitcast i16 [[EXTRACTED1]] to half
; GFX11-NEXT: ret half [[TMP5]]
;
- %res = atomicrmw fadd half addrspace(1)* %ptr, half %value seq_cst, align 4
+ %res = atomicrmw fadd ptr addrspace(1) %ptr, half %value seq_cst, align 4
ret half %res
}
-define half @test_atomicrmw_fadd_f16_local(half addrspace(3)* %ptr, half %value) {
+define half @test_atomicrmw_fadd_f16_local(ptr addrspace(3) %ptr, half %value) {
; CI-LABEL: @test_atomicrmw_fadd_f16_local(
-; CI-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(3)* @llvm.ptrmask.p3f16.i64(half addrspace(3)* [[PTR:%.*]], i64 -4)
-; CI-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(3)* [[PTR]] to i64
+; CI-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[PTR:%.*]], i64 -4)
+; CI-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i64
; CI-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CI-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; CI-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CI-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CI-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CI-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)*
-; CI-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4
+; CI-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4
; CI-NEXT: br label [[ATOMICRMW_START:%.*]]
; CI: atomicrmw.start:
; CI-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1408,7 +1347,7 @@ define half @test_atomicrmw_fadd_f16_local(half addrspace(3)* %ptr, half %value)
; CI-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; CI-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CI-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; CI-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; CI-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; CI-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; CI-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1419,15 +1358,14 @@ define half @test_atomicrmw_fadd_f16_local(half addrspace(3)* %ptr, half %value)
; CI-NEXT: ret half [[TMP7]]
;
; GFX9-LABEL: @test_atomicrmw_fadd_f16_local(
-; GFX9-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(3)* @llvm.ptrmask.p3f16.i64(half addrspace(3)* [[PTR:%.*]], i64 -4)
-; GFX9-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(3)* [[PTR]] to i64
+; GFX9-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[PTR:%.*]], i64 -4)
+; GFX9-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i64
; GFX9-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GFX9-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GFX9-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GFX9-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GFX9-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GFX9-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)*
-; GFX9-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4
+; GFX9-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4
; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX9: atomicrmw.start:
; GFX9-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1440,7 +1378,7 @@ define half @test_atomicrmw_fadd_f16_local(half addrspace(3)* %ptr, half %value)
; GFX9-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GFX9-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GFX9-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GFX9-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX9-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GFX9-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; GFX9-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1451,15 +1389,14 @@ define half @test_atomicrmw_fadd_f16_local(half addrspace(3)* %ptr, half %value)
; GFX9-NEXT: ret half [[TMP7]]
;
; GFX908-LABEL: @test_atomicrmw_fadd_f16_local(
-; GFX908-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(3)* @llvm.ptrmask.p3f16.i64(half addrspace(3)* [[PTR:%.*]], i64 -4)
-; GFX908-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(3)* [[PTR]] to i64
+; GFX908-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[PTR:%.*]], i64 -4)
+; GFX908-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i64
; GFX908-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GFX908-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GFX908-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GFX908-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GFX908-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GFX908-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)*
-; GFX908-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4
+; GFX908-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1472,7 +1409,7 @@ define half @test_atomicrmw_fadd_f16_local(half addrspace(3)* %ptr, half %value)
; GFX908-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GFX908-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GFX908-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GFX908-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX908-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GFX908-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; GFX908-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1483,15 +1420,14 @@ define half @test_atomicrmw_fadd_f16_local(half addrspace(3)* %ptr, half %value)
; GFX908-NEXT: ret half [[TMP7]]
;
; GFX90A-LABEL: @test_atomicrmw_fadd_f16_local(
-; GFX90A-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(3)* @llvm.ptrmask.p3f16.i64(half addrspace(3)* [[PTR:%.*]], i64 -4)
-; GFX90A-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(3)* [[PTR]] to i64
+; GFX90A-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[PTR:%.*]], i64 -4)
+; GFX90A-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i64
; GFX90A-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GFX90A-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GFX90A-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GFX90A-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GFX90A-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GFX90A-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)*
-; GFX90A-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4
+; GFX90A-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4
; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX90A: atomicrmw.start:
; GFX90A-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1504,7 +1440,7 @@ define half @test_atomicrmw_fadd_f16_local(half addrspace(3)* %ptr, half %value)
; GFX90A-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GFX90A-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GFX90A-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GFX90A-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX90A-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GFX90A-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; GFX90A-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1515,15 +1451,14 @@ define half @test_atomicrmw_fadd_f16_local(half addrspace(3)* %ptr, half %value)
; GFX90A-NEXT: ret half [[TMP7]]
;
; GFX940-LABEL: @test_atomicrmw_fadd_f16_local(
-; GFX940-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(3)* @llvm.ptrmask.p3f16.i64(half addrspace(3)* [[PTR:%.*]], i64 -4)
-; GFX940-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(3)* [[PTR]] to i64
+; GFX940-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[PTR:%.*]], i64 -4)
+; GFX940-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i64
; GFX940-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GFX940-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GFX940-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GFX940-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GFX940-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GFX940-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)*
-; GFX940-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4
+; GFX940-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4
; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX940: atomicrmw.start:
; GFX940-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1536,7 +1471,7 @@ define half @test_atomicrmw_fadd_f16_local(half addrspace(3)* %ptr, half %value)
; GFX940-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GFX940-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GFX940-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GFX940-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX940-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GFX940-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; GFX940-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1547,15 +1482,14 @@ define half @test_atomicrmw_fadd_f16_local(half addrspace(3)* %ptr, half %value)
; GFX940-NEXT: ret half [[TMP7]]
;
; GFX11-LABEL: @test_atomicrmw_fadd_f16_local(
-; GFX11-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(3)* @llvm.ptrmask.p3f16.i64(half addrspace(3)* [[PTR:%.*]], i64 -4)
-; GFX11-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(3)* [[PTR]] to i64
+; GFX11-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[PTR:%.*]], i64 -4)
+; GFX11-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i64
; GFX11-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GFX11-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GFX11-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GFX11-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GFX11-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GFX11-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)*
-; GFX11-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4
+; GFX11-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4
; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX11: atomicrmw.start:
; GFX11-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -1568,7 +1502,7 @@ define half @test_atomicrmw_fadd_f16_local(half addrspace(3)* %ptr, half %value)
; GFX11-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GFX11-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GFX11-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GFX11-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GFX11-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GFX11-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; GFX11-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -1578,21 +1512,20 @@ define half @test_atomicrmw_fadd_f16_local(half addrspace(3)* %ptr, half %value)
; GFX11-NEXT: [[TMP7:%.*]] = bitcast i16 [[EXTRACTED4]] to half
; GFX11-NEXT: ret half [[TMP7]]
;
- %res = atomicrmw fadd half addrspace(3)* %ptr, half %value seq_cst
+ %res = atomicrmw fadd ptr addrspace(3) %ptr, half %value seq_cst
ret half %res
}
-define double @test_atomicrmw_fadd_f64_flat(double* %ptr, double %value) {
+define double @test_atomicrmw_fadd_f64_flat(ptr %ptr, double %value) {
; CI-LABEL: @test_atomicrmw_fadd_f64_flat(
-; CI-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8
+; CI-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8
; CI-NEXT: br label [[ATOMICRMW_START:%.*]]
; CI: atomicrmw.start:
; CI-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CI-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; CI-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64*
; CI-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; CI-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; CI-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
+; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; CI-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -1601,15 +1534,14 @@ define double @test_atomicrmw_fadd_f64_flat(double* %ptr, double %value) {
; CI-NEXT: ret double [[TMP6]]
;
; GFX9-LABEL: @test_atomicrmw_fadd_f64_flat(
-; GFX9-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8
+; GFX9-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8
; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX9: atomicrmw.start:
; GFX9-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX9-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; GFX9-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64*
; GFX9-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GFX9-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
+; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GFX9-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -1618,15 +1550,14 @@ define double @test_atomicrmw_fadd_f64_flat(double* %ptr, double %value) {
; GFX9-NEXT: ret double [[TMP6]]
;
; GFX908-LABEL: @test_atomicrmw_fadd_f64_flat(
-; GFX908-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8
+; GFX908-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX908-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; GFX908-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64*
; GFX908-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GFX908-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
+; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GFX908-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -1635,15 +1566,14 @@ define double @test_atomicrmw_fadd_f64_flat(double* %ptr, double %value) {
; GFX908-NEXT: ret double [[TMP6]]
;
; GFX90A-LABEL: @test_atomicrmw_fadd_f64_flat(
-; GFX90A-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8
+; GFX90A-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8
; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX90A: atomicrmw.start:
; GFX90A-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX90A-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; GFX90A-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64*
; GFX90A-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GFX90A-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
+; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GFX90A-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -1652,15 +1582,14 @@ define double @test_atomicrmw_fadd_f64_flat(double* %ptr, double %value) {
; GFX90A-NEXT: ret double [[TMP6]]
;
; GFX940-LABEL: @test_atomicrmw_fadd_f64_flat(
-; GFX940-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8
+; GFX940-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8
; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX940: atomicrmw.start:
; GFX940-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX940-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; GFX940-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64*
; GFX940-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GFX940-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
+; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GFX940-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -1669,15 +1598,14 @@ define double @test_atomicrmw_fadd_f64_flat(double* %ptr, double %value) {
; GFX940-NEXT: ret double [[TMP6]]
;
; GFX11-LABEL: @test_atomicrmw_fadd_f64_flat(
-; GFX11-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8
+; GFX11-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8
; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX11: atomicrmw.start:
; GFX11-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX11-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; GFX11-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64*
; GFX11-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GFX11-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
+; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GFX11-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -1685,21 +1613,20 @@ define double @test_atomicrmw_fadd_f64_flat(double* %ptr, double %value) {
; GFX11: atomicrmw.end:
; GFX11-NEXT: ret double [[TMP6]]
;
- %res = atomicrmw fadd double* %ptr, double %value seq_cst
+ %res = atomicrmw fadd ptr %ptr, double %value seq_cst
ret double %res
}
-define double @test_atomicrmw_fadd_f64_global(double addrspace(1)* %ptr, double %value) {
+define double @test_atomicrmw_fadd_f64_global(ptr addrspace(1) %ptr, double %value) {
; CI-LABEL: @test_atomicrmw_fadd_f64_global(
-; CI-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8
+; CI-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8
; CI-NEXT: br label [[ATOMICRMW_START:%.*]]
; CI: atomicrmw.start:
; CI-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CI-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; CI-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)*
; CI-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; CI-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; CI-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
+; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; CI-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -1708,15 +1635,14 @@ define double @test_atomicrmw_fadd_f64_global(double addrspace(1)* %ptr, double
; CI-NEXT: ret double [[TMP6]]
;
; GFX9-LABEL: @test_atomicrmw_fadd_f64_global(
-; GFX9-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8
+; GFX9-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8
; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX9: atomicrmw.start:
; GFX9-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX9-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; GFX9-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)*
; GFX9-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GFX9-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
+; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GFX9-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -1725,15 +1651,14 @@ define double @test_atomicrmw_fadd_f64_global(double addrspace(1)* %ptr, double
; GFX9-NEXT: ret double [[TMP6]]
;
; GFX908-LABEL: @test_atomicrmw_fadd_f64_global(
-; GFX908-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8
+; GFX908-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX908-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; GFX908-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)*
; GFX908-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GFX908-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
+; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GFX908-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -1742,15 +1667,14 @@ define double @test_atomicrmw_fadd_f64_global(double addrspace(1)* %ptr, double
; GFX908-NEXT: ret double [[TMP6]]
;
; GFX90A-LABEL: @test_atomicrmw_fadd_f64_global(
-; GFX90A-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8
+; GFX90A-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8
; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX90A: atomicrmw.start:
; GFX90A-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX90A-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; GFX90A-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)*
; GFX90A-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GFX90A-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
+; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GFX90A-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -1759,15 +1683,14 @@ define double @test_atomicrmw_fadd_f64_global(double addrspace(1)* %ptr, double
; GFX90A-NEXT: ret double [[TMP6]]
;
; GFX940-LABEL: @test_atomicrmw_fadd_f64_global(
-; GFX940-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8
+; GFX940-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8
; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX940: atomicrmw.start:
; GFX940-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX940-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; GFX940-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)*
; GFX940-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GFX940-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
+; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GFX940-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -1776,15 +1699,14 @@ define double @test_atomicrmw_fadd_f64_global(double addrspace(1)* %ptr, double
; GFX940-NEXT: ret double [[TMP6]]
;
; GFX11-LABEL: @test_atomicrmw_fadd_f64_global(
-; GFX11-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8
+; GFX11-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8
; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX11: atomicrmw.start:
; GFX11-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX11-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; GFX11-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)*
; GFX11-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GFX11-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
+; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GFX11-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -1792,21 +1714,20 @@ define double @test_atomicrmw_fadd_f64_global(double addrspace(1)* %ptr, double
; GFX11: atomicrmw.end:
; GFX11-NEXT: ret double [[TMP6]]
;
- %res = atomicrmw fadd double addrspace(1)* %ptr, double %value seq_cst
+ %res = atomicrmw fadd ptr addrspace(1) %ptr, double %value seq_cst
ret double %res
}
-define double @test_atomicrmw_fadd_f64_local(double addrspace(3)* %ptr, double %value) {
+define double @test_atomicrmw_fadd_f64_local(ptr addrspace(3) %ptr, double %value) {
; CI-LABEL: @test_atomicrmw_fadd_f64_local(
-; CI-NEXT: [[TMP1:%.*]] = load double, double addrspace(3)* [[PTR:%.*]], align 8
+; CI-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(3) [[PTR:%.*]], align 8
; CI-NEXT: br label [[ATOMICRMW_START:%.*]]
; CI: atomicrmw.start:
; CI-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CI-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; CI-NEXT: [[TMP2:%.*]] = bitcast double addrspace(3)* [[PTR]] to i64 addrspace(3)*
; CI-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; CI-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; CI-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(3)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
+; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; CI-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -1815,15 +1736,14 @@ define double @test_atomicrmw_fadd_f64_local(double addrspace(3)* %ptr, double %
; CI-NEXT: ret double [[TMP6]]
;
; GFX9-LABEL: @test_atomicrmw_fadd_f64_local(
-; GFX9-NEXT: [[TMP1:%.*]] = load double, double addrspace(3)* [[PTR:%.*]], align 8
+; GFX9-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(3) [[PTR:%.*]], align 8
; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX9: atomicrmw.start:
; GFX9-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX9-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; GFX9-NEXT: [[TMP2:%.*]] = bitcast double addrspace(3)* [[PTR]] to i64 addrspace(3)*
; GFX9-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GFX9-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(3)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
+; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GFX9-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -1832,15 +1752,14 @@ define double @test_atomicrmw_fadd_f64_local(double addrspace(3)* %ptr, double %
; GFX9-NEXT: ret double [[TMP6]]
;
; GFX908-LABEL: @test_atomicrmw_fadd_f64_local(
-; GFX908-NEXT: [[TMP1:%.*]] = load double, double addrspace(3)* [[PTR:%.*]], align 8
+; GFX908-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(3) [[PTR:%.*]], align 8
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX908-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; GFX908-NEXT: [[TMP2:%.*]] = bitcast double addrspace(3)* [[PTR]] to i64 addrspace(3)*
; GFX908-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GFX908-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(3)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
+; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GFX908-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -1849,23 +1768,22 @@ define double @test_atomicrmw_fadd_f64_local(double addrspace(3)* %ptr, double %
; GFX908-NEXT: ret double [[TMP6]]
;
; GFX90A-LABEL: @test_atomicrmw_fadd_f64_local(
-; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd double addrspace(3)* [[PTR:%.*]], double [[VALUE:%.*]] seq_cst, align 8
+; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(3) [[PTR:%.*]], double [[VALUE:%.*]] seq_cst, align 8
; GFX90A-NEXT: ret double [[RES]]
;
; GFX940-LABEL: @test_atomicrmw_fadd_f64_local(
-; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd double addrspace(3)* [[PTR:%.*]], double [[VALUE:%.*]] seq_cst, align 8
+; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(3) [[PTR:%.*]], double [[VALUE:%.*]] seq_cst, align 8
; GFX940-NEXT: ret double [[RES]]
;
; GFX11-LABEL: @test_atomicrmw_fadd_f64_local(
-; GFX11-NEXT: [[TMP1:%.*]] = load double, double addrspace(3)* [[PTR:%.*]], align 8
+; GFX11-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(3) [[PTR:%.*]], align 8
; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX11: atomicrmw.start:
; GFX11-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX11-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; GFX11-NEXT: [[TMP2:%.*]] = bitcast double addrspace(3)* [[PTR]] to i64 addrspace(3)*
; GFX11-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GFX11-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(3)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
+; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GFX11-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -1873,21 +1791,20 @@ define double @test_atomicrmw_fadd_f64_local(double addrspace(3)* %ptr, double %
; GFX11: atomicrmw.end:
; GFX11-NEXT: ret double [[TMP6]]
;
- %res = atomicrmw fadd double addrspace(3)* %ptr, double %value seq_cst
+ %res = atomicrmw fadd ptr addrspace(3) %ptr, double %value seq_cst
ret double %res
}
-define float @test_atomicrmw_fadd_f32_global_agent(float addrspace(1)* %ptr, float %value) {
+define float @test_atomicrmw_fadd_f32_global_agent(ptr addrspace(1) %ptr, float %value) {
; CI-LABEL: @test_atomicrmw_fadd_f32_global_agent(
-; CI-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; CI-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; CI-NEXT: br label [[ATOMICRMW_START:%.*]]
; CI: atomicrmw.start:
; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CI-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4
+; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4
; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -1896,15 +1813,14 @@ define float @test_atomicrmw_fadd_f32_global_agent(float addrspace(1)* %ptr, flo
; CI-NEXT: ret float [[TMP6]]
;
; GFX9-LABEL: @test_atomicrmw_fadd_f32_global_agent(
-; GFX9-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX9-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX9: atomicrmw.start:
; GFX9-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX9-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX9-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX9-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4
+; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4
; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX9-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -1913,15 +1829,14 @@ define float @test_atomicrmw_fadd_f32_global_agent(float addrspace(1)* %ptr, flo
; GFX9-NEXT: ret float [[TMP6]]
;
; GFX908-LABEL: @test_atomicrmw_fadd_f32_global_agent(
-; GFX908-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX908-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4
+; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -1930,15 +1845,14 @@ define float @test_atomicrmw_fadd_f32_global_agent(float addrspace(1)* %ptr, flo
; GFX908-NEXT: ret float [[TMP6]]
;
; GFX90A-LABEL: @test_atomicrmw_fadd_f32_global_agent(
-; GFX90A-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX90A-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX90A: atomicrmw.start:
; GFX90A-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX90A-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX90A-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX90A-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX90A-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4
+; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4
; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX90A-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -1947,15 +1861,14 @@ define float @test_atomicrmw_fadd_f32_global_agent(float addrspace(1)* %ptr, flo
; GFX90A-NEXT: ret float [[TMP6]]
;
; GFX940-LABEL: @test_atomicrmw_fadd_f32_global_agent(
-; GFX940-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX940-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX940: atomicrmw.start:
; GFX940-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX940-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX940-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX940-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX940-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4
+; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4
; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX940-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -1964,15 +1877,14 @@ define float @test_atomicrmw_fadd_f32_global_agent(float addrspace(1)* %ptr, flo
; GFX940-NEXT: ret float [[TMP6]]
;
; GFX11-LABEL: @test_atomicrmw_fadd_f32_global_agent(
-; GFX11-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX11: atomicrmw.start:
; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX11-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4
+; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4
; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -1980,21 +1892,20 @@ define float @test_atomicrmw_fadd_f32_global_agent(float addrspace(1)* %ptr, flo
; GFX11: atomicrmw.end:
; GFX11-NEXT: ret float [[TMP6]]
;
- %res = atomicrmw fadd float addrspace(1)* %ptr, float %value syncscope("agent") monotonic
+ %res = atomicrmw fadd ptr addrspace(1) %ptr, float %value syncscope("agent") monotonic
ret float %res
}
-define float @test_atomicrmw_fadd_f32_global_one_as(float addrspace(1)* %ptr, float %value) {
+define float @test_atomicrmw_fadd_f32_global_one_as(ptr addrspace(1) %ptr, float %value) {
; CI-LABEL: @test_atomicrmw_fadd_f32_global_one_as(
-; CI-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; CI-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; CI-NEXT: br label [[ATOMICRMW_START:%.*]]
; CI: atomicrmw.start:
; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CI-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4
+; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4
; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -2003,15 +1914,14 @@ define float @test_atomicrmw_fadd_f32_global_one_as(float addrspace(1)* %ptr, fl
; CI-NEXT: ret float [[TMP6]]
;
; GFX9-LABEL: @test_atomicrmw_fadd_f32_global_one_as(
-; GFX9-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX9-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX9: atomicrmw.start:
; GFX9-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX9-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX9-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX9-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4
+; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4
; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX9-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -2020,15 +1930,14 @@ define float @test_atomicrmw_fadd_f32_global_one_as(float addrspace(1)* %ptr, fl
; GFX9-NEXT: ret float [[TMP6]]
;
; GFX908-LABEL: @test_atomicrmw_fadd_f32_global_one_as(
-; GFX908-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX908: atomicrmw.start:
; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX908-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4
+; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4
; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -2037,15 +1946,14 @@ define float @test_atomicrmw_fadd_f32_global_one_as(float addrspace(1)* %ptr, fl
; GFX908-NEXT: ret float [[TMP6]]
;
; GFX90A-LABEL: @test_atomicrmw_fadd_f32_global_one_as(
-; GFX90A-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX90A-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX90A: atomicrmw.start:
; GFX90A-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX90A-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX90A-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX90A-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX90A-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4
+; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4
; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX90A-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -2054,15 +1962,14 @@ define float @test_atomicrmw_fadd_f32_global_one_as(float addrspace(1)* %ptr, fl
; GFX90A-NEXT: ret float [[TMP6]]
;
; GFX940-LABEL: @test_atomicrmw_fadd_f32_global_one_as(
-; GFX940-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX940-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX940: atomicrmw.start:
; GFX940-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX940-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX940-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX940-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX940-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4
+; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4
; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX940-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -2071,15 +1978,14 @@ define float @test_atomicrmw_fadd_f32_global_one_as(float addrspace(1)* %ptr, fl
; GFX940-NEXT: ret float [[TMP6]]
;
; GFX11-LABEL: @test_atomicrmw_fadd_f32_global_one_as(
-; GFX11-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]]
; GFX11: atomicrmw.start:
; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; GFX11-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4
+; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4
; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -2087,7 +1993,7 @@ define float @test_atomicrmw_fadd_f32_global_one_as(float addrspace(1)* %ptr, fl
; GFX11: atomicrmw.end:
; GFX11-NEXT: ret float [[TMP6]]
;
- %res = atomicrmw fadd float addrspace(1)* %ptr, float %value syncscope("one-as") monotonic
+ %res = atomicrmw fadd ptr addrspace(1) %ptr, float %value syncscope("one-as") monotonic
ret float %res
}
diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmax.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmax.ll
index 2647abb372212..87e39d6ca4b04 100644
--- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmax.ll
+++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmax.ll
@@ -2,17 +2,16 @@
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -atomic-expand %s | FileCheck -check-prefix=GCN %s
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -atomic-expand %s | FileCheck -check-prefix=GCN %s
-define float @test_atomicrmw_fmax_f32_flat(float* %ptr, float %value) {
+define float @test_atomicrmw_fmax_f32_flat(ptr %ptr, float %value) {
; GCN-LABEL: @test_atomicrmw_fmax_f32_flat(
-; GCN-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; GCN-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ]
; GCN-NEXT: [[TMP2:%.*]] = call float @llvm.maxnum.f32(float [[LOADED]], float [[VALUE:%.*]])
-; GCN-NEXT: [[TMP3:%.*]] = bitcast float* [[PTR]] to i32*
; GCN-NEXT: [[TMP4:%.*]] = bitcast float [[TMP2]] to i32
; GCN-NEXT: [[TMP5:%.*]] = bitcast float [[LOADED]] to i32
-; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i32* [[TMP3]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0
; GCN-NEXT: [[TMP7]] = bitcast i32 [[NEWLOADED]] to float
@@ -20,21 +19,20 @@ define float @test_atomicrmw_fmax_f32_flat(float* %ptr, float %value) {
; GCN: atomicrmw.end:
; GCN-NEXT: ret float [[TMP7]]
;
- %res = atomicrmw fmax float* %ptr, float %value seq_cst
+ %res = atomicrmw fmax ptr %ptr, float %value seq_cst
ret float %res
}
-define float @test_atomicrmw_fmax_f32_global(float addrspace(1)* %ptr, float %value) {
+define float @test_atomicrmw_fmax_f32_global(ptr addrspace(1) %ptr, float %value) {
; GCN-LABEL: @test_atomicrmw_fmax_f32_global(
-; GCN-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GCN-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ]
; GCN-NEXT: [[TMP2:%.*]] = call float @llvm.maxnum.f32(float [[LOADED]], float [[VALUE:%.*]])
-; GCN-NEXT: [[TMP3:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GCN-NEXT: [[TMP4:%.*]] = bitcast float [[TMP2]] to i32
; GCN-NEXT: [[TMP5:%.*]] = bitcast float [[LOADED]] to i32
-; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[TMP3]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0
; GCN-NEXT: [[TMP7]] = bitcast i32 [[NEWLOADED]] to float
@@ -42,21 +40,20 @@ define float @test_atomicrmw_fmax_f32_global(float addrspace(1)* %ptr, float %va
; GCN: atomicrmw.end:
; GCN-NEXT: ret float [[TMP7]]
;
- %res = atomicrmw fmax float addrspace(1)* %ptr, float %value seq_cst
+ %res = atomicrmw fmax ptr addrspace(1) %ptr, float %value seq_cst
ret float %res
}
-define float @test_atomicrmw_fmax_f32_local(float addrspace(3)* %ptr, float %value) {
+define float @test_atomicrmw_fmax_f32_local(ptr addrspace(3) %ptr, float %value) {
; GCN-LABEL: @test_atomicrmw_fmax_f32_local(
-; GCN-NEXT: [[TMP1:%.*]] = load float, float addrspace(3)* [[PTR:%.*]], align 4
+; GCN-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(3) [[PTR:%.*]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ]
; GCN-NEXT: [[TMP2:%.*]] = call float @llvm.maxnum.f32(float [[LOADED]], float [[VALUE:%.*]])
-; GCN-NEXT: [[TMP3:%.*]] = bitcast float addrspace(3)* [[PTR]] to i32 addrspace(3)*
; GCN-NEXT: [[TMP4:%.*]] = bitcast float [[TMP2]] to i32
; GCN-NEXT: [[TMP5:%.*]] = bitcast float [[LOADED]] to i32
-; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(3)* [[TMP3]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0
; GCN-NEXT: [[TMP7]] = bitcast i32 [[NEWLOADED]] to float
@@ -64,21 +61,20 @@ define float @test_atomicrmw_fmax_f32_local(float addrspace(3)* %ptr, float %val
; GCN: atomicrmw.end:
; GCN-NEXT: ret float [[TMP7]]
;
- %res = atomicrmw fmax float addrspace(3)* %ptr, float %value seq_cst
+ %res = atomicrmw fmax ptr addrspace(3) %ptr, float %value seq_cst
ret float %res
}
-define half @test_atomicrmw_fmax_f16_flat(half* %ptr, half %value) {
+define half @test_atomicrmw_fmax_f16_flat(ptr %ptr, half %value) {
; GCN-LABEL: @test_atomicrmw_fmax_f16_flat(
-; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4)
-; GCN-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64
+; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4)
+; GCN-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64
; GCN-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GCN-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GCN-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GCN-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GCN-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32*
-; GCN-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4
+; GCN-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -91,7 +87,7 @@ define half @test_atomicrmw_fmax_f16_flat(half* %ptr, half %value) {
; GCN-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GCN-NEXT: [[TMP7:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP7:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1
; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0
; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -101,21 +97,20 @@ define half @test_atomicrmw_fmax_f16_flat(half* %ptr, half %value) {
; GCN-NEXT: [[TMP8:%.*]] = bitcast i16 [[EXTRACTED4]] to half
; GCN-NEXT: ret half [[TMP8]]
;
- %res = atomicrmw fmax half* %ptr, half %value seq_cst
+ %res = atomicrmw fmax ptr %ptr, half %value seq_cst
ret half %res
}
-define half @test_atomicrmw_fmax_f16_global(half addrspace(1)* %ptr, half %value) {
+define half @test_atomicrmw_fmax_f16_global(ptr addrspace(1) %ptr, half %value) {
; GCN-LABEL: @test_atomicrmw_fmax_f16_global(
-; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(1)* @llvm.ptrmask.p1f16.i64(half addrspace(1)* [[PTR:%.*]], i64 -4)
-; GCN-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(1)* [[PTR]] to i64
+; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; GCN-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; GCN-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GCN-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GCN-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GCN-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GCN-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
-; GCN-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; GCN-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -128,7 +123,7 @@ define half @test_atomicrmw_fmax_f16_global(half addrspace(1)* %ptr, half %value
; GCN-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GCN-NEXT: [[TMP7:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP7:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1
; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0
; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -138,14 +133,13 @@ define half @test_atomicrmw_fmax_f16_global(half addrspace(1)* %ptr, half %value
; GCN-NEXT: [[TMP8:%.*]] = bitcast i16 [[EXTRACTED4]] to half
; GCN-NEXT: ret half [[TMP8]]
;
- %res = atomicrmw fmax half addrspace(1)* %ptr, half %value seq_cst
+ %res = atomicrmw fmax ptr addrspace(1) %ptr, half %value seq_cst
ret half %res
}
-define half @test_atomicrmw_fmax_f16_global_align4(half addrspace(1)* %ptr, half %value) {
+define half @test_atomicrmw_fmax_f16_global_align4(ptr addrspace(1) %ptr, half %value) {
; GCN-LABEL: @test_atomicrmw_fmax_f16_global_align4(
-; GCN-NEXT: [[ALIGNEDADDR:%.*]] = bitcast half addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)*
-; GCN-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4
+; GCN-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -156,7 +150,7 @@ define half @test_atomicrmw_fmax_f16_global_align4(half addrspace(1)* %ptr, half
; GCN-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP4]] to i32
; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], -65536
; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[EXTENDED]]
-; GCN-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0
; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -165,21 +159,20 @@ define half @test_atomicrmw_fmax_f16_global_align4(half addrspace(1)* %ptr, half
; GCN-NEXT: [[TMP6:%.*]] = bitcast i16 [[EXTRACTED1]] to half
; GCN-NEXT: ret half [[TMP6]]
;
- %res = atomicrmw fmax half addrspace(1)* %ptr, half %value seq_cst, align 4
+ %res = atomicrmw fmax ptr addrspace(1) %ptr, half %value seq_cst, align 4
ret half %res
}
-define half @test_atomicrmw_fmax_f16_local(half addrspace(3)* %ptr, half %value) {
+define half @test_atomicrmw_fmax_f16_local(ptr addrspace(3) %ptr, half %value) {
; GCN-LABEL: @test_atomicrmw_fmax_f16_local(
-; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(3)* @llvm.ptrmask.p3f16.i64(half addrspace(3)* [[PTR:%.*]], i64 -4)
-; GCN-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(3)* [[PTR]] to i64
+; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[PTR:%.*]], i64 -4)
+; GCN-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i64
; GCN-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GCN-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GCN-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GCN-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GCN-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)*
-; GCN-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4
+; GCN-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -192,7 +185,7 @@ define half @test_atomicrmw_fmax_f16_local(half addrspace(3)* %ptr, half %value)
; GCN-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GCN-NEXT: [[TMP7:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP7:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1
; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0
; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -202,21 +195,20 @@ define half @test_atomicrmw_fmax_f16_local(half addrspace(3)* %ptr, half %value)
; GCN-NEXT: [[TMP8:%.*]] = bitcast i16 [[EXTRACTED4]] to half
; GCN-NEXT: ret half [[TMP8]]
;
- %res = atomicrmw fmax half addrspace(3)* %ptr, half %value seq_cst
+ %res = atomicrmw fmax ptr addrspace(3) %ptr, half %value seq_cst
ret half %res
}
-define double @test_atomicrmw_fmax_f64_flat(double* %ptr, double %value) {
+define double @test_atomicrmw_fmax_f64_flat(ptr %ptr, double %value) {
; GCN-LABEL: @test_atomicrmw_fmax_f64_flat(
-; GCN-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8
+; GCN-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ]
; GCN-NEXT: [[TMP2:%.*]] = call double @llvm.maxnum.f64(double [[LOADED]], double [[VALUE:%.*]])
-; GCN-NEXT: [[TMP3:%.*]] = bitcast double* [[PTR]] to i64*
; GCN-NEXT: [[TMP4:%.*]] = bitcast double [[TMP2]] to i64
; GCN-NEXT: [[TMP5:%.*]] = bitcast double [[LOADED]] to i64
-; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i64* [[TMP3]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8
+; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP6]], 1
; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
; GCN-NEXT: [[TMP7]] = bitcast i64 [[NEWLOADED]] to double
@@ -224,21 +216,20 @@ define double @test_atomicrmw_fmax_f64_flat(double* %ptr, double %value) {
; GCN: atomicrmw.end:
; GCN-NEXT: ret double [[TMP7]]
;
- %res = atomicrmw fmax double* %ptr, double %value seq_cst
+ %res = atomicrmw fmax ptr %ptr, double %value seq_cst
ret double %res
}
-define double @test_atomicrmw_fmax_f64_global(double addrspace(1)* %ptr, double %value) {
+define double @test_atomicrmw_fmax_f64_global(ptr addrspace(1) %ptr, double %value) {
; GCN-LABEL: @test_atomicrmw_fmax_f64_global(
-; GCN-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8
+; GCN-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ]
; GCN-NEXT: [[TMP2:%.*]] = call double @llvm.maxnum.f64(double [[LOADED]], double [[VALUE:%.*]])
-; GCN-NEXT: [[TMP3:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)*
; GCN-NEXT: [[TMP4:%.*]] = bitcast double [[TMP2]] to i64
; GCN-NEXT: [[TMP5:%.*]] = bitcast double [[LOADED]] to i64
-; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i64 addrspace(1)* [[TMP3]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8
+; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP6]], 1
; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
; GCN-NEXT: [[TMP7]] = bitcast i64 [[NEWLOADED]] to double
@@ -246,21 +237,20 @@ define double @test_atomicrmw_fmax_f64_global(double addrspace(1)* %ptr, double
; GCN: atomicrmw.end:
; GCN-NEXT: ret double [[TMP7]]
;
- %res = atomicrmw fmax double addrspace(1)* %ptr, double %value seq_cst
+ %res = atomicrmw fmax ptr addrspace(1) %ptr, double %value seq_cst
ret double %res
}
-define double @test_atomicrmw_fmax_f64_local(double addrspace(3)* %ptr, double %value) {
+define double @test_atomicrmw_fmax_f64_local(ptr addrspace(3) %ptr, double %value) {
; GCN-LABEL: @test_atomicrmw_fmax_f64_local(
-; GCN-NEXT: [[TMP1:%.*]] = load double, double addrspace(3)* [[PTR:%.*]], align 8
+; GCN-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(3) [[PTR:%.*]], align 8
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ]
; GCN-NEXT: [[TMP2:%.*]] = call double @llvm.maxnum.f64(double [[LOADED]], double [[VALUE:%.*]])
-; GCN-NEXT: [[TMP3:%.*]] = bitcast double addrspace(3)* [[PTR]] to i64 addrspace(3)*
; GCN-NEXT: [[TMP4:%.*]] = bitcast double [[TMP2]] to i64
; GCN-NEXT: [[TMP5:%.*]] = bitcast double [[LOADED]] to i64
-; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i64 addrspace(3)* [[TMP3]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8
+; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP6]], 1
; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
; GCN-NEXT: [[TMP7]] = bitcast i64 [[NEWLOADED]] to double
@@ -268,6 +258,6 @@ define double @test_atomicrmw_fmax_f64_local(double addrspace(3)* %ptr, double %
; GCN: atomicrmw.end:
; GCN-NEXT: ret double [[TMP7]]
;
- %res = atomicrmw fmax double addrspace(3)* %ptr, double %value seq_cst
+ %res = atomicrmw fmax ptr addrspace(3) %ptr, double %value seq_cst
ret double %res
}
diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmin.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmin.ll
index 68bd812e636e7..c1ed6b808658b 100644
--- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmin.ll
+++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmin.ll
@@ -2,17 +2,16 @@
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -atomic-expand %s | FileCheck -check-prefix=GCN %s
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -atomic-expand %s | FileCheck -check-prefix=GCN %s
-define float @test_atomicrmw_fmin_f32_flat(float* %ptr, float %value) {
+define float @test_atomicrmw_fmin_f32_flat(ptr %ptr, float %value) {
; GCN-LABEL: @test_atomicrmw_fmin_f32_flat(
-; GCN-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; GCN-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ]
; GCN-NEXT: [[TMP2:%.*]] = call float @llvm.minnum.f32(float [[LOADED]], float [[VALUE:%.*]])
-; GCN-NEXT: [[TMP3:%.*]] = bitcast float* [[PTR]] to i32*
; GCN-NEXT: [[TMP4:%.*]] = bitcast float [[TMP2]] to i32
; GCN-NEXT: [[TMP5:%.*]] = bitcast float [[LOADED]] to i32
-; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i32* [[TMP3]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0
; GCN-NEXT: [[TMP7]] = bitcast i32 [[NEWLOADED]] to float
@@ -20,21 +19,20 @@ define float @test_atomicrmw_fmin_f32_flat(float* %ptr, float %value) {
; GCN: atomicrmw.end:
; GCN-NEXT: ret float [[TMP7]]
;
- %res = atomicrmw fmin float* %ptr, float %value seq_cst
+ %res = atomicrmw fmin ptr %ptr, float %value seq_cst
ret float %res
}
-define float @test_atomicrmw_fmin_f32_global(float addrspace(1)* %ptr, float %value) {
+define float @test_atomicrmw_fmin_f32_global(ptr addrspace(1) %ptr, float %value) {
; GCN-LABEL: @test_atomicrmw_fmin_f32_global(
-; GCN-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GCN-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ]
; GCN-NEXT: [[TMP2:%.*]] = call float @llvm.minnum.f32(float [[LOADED]], float [[VALUE:%.*]])
-; GCN-NEXT: [[TMP3:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GCN-NEXT: [[TMP4:%.*]] = bitcast float [[TMP2]] to i32
; GCN-NEXT: [[TMP5:%.*]] = bitcast float [[LOADED]] to i32
-; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[TMP3]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0
; GCN-NEXT: [[TMP7]] = bitcast i32 [[NEWLOADED]] to float
@@ -42,21 +40,20 @@ define float @test_atomicrmw_fmin_f32_global(float addrspace(1)* %ptr, float %va
; GCN: atomicrmw.end:
; GCN-NEXT: ret float [[TMP7]]
;
- %res = atomicrmw fmin float addrspace(1)* %ptr, float %value seq_cst
+ %res = atomicrmw fmin ptr addrspace(1) %ptr, float %value seq_cst
ret float %res
}
-define float @test_atomicrmw_fmin_f32_local(float addrspace(3)* %ptr, float %value) {
+define float @test_atomicrmw_fmin_f32_local(ptr addrspace(3) %ptr, float %value) {
; GCN-LABEL: @test_atomicrmw_fmin_f32_local(
-; GCN-NEXT: [[TMP1:%.*]] = load float, float addrspace(3)* [[PTR:%.*]], align 4
+; GCN-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(3) [[PTR:%.*]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ]
; GCN-NEXT: [[TMP2:%.*]] = call float @llvm.minnum.f32(float [[LOADED]], float [[VALUE:%.*]])
-; GCN-NEXT: [[TMP3:%.*]] = bitcast float addrspace(3)* [[PTR]] to i32 addrspace(3)*
; GCN-NEXT: [[TMP4:%.*]] = bitcast float [[TMP2]] to i32
; GCN-NEXT: [[TMP5:%.*]] = bitcast float [[LOADED]] to i32
-; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(3)* [[TMP3]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0
; GCN-NEXT: [[TMP7]] = bitcast i32 [[NEWLOADED]] to float
@@ -64,21 +61,20 @@ define float @test_atomicrmw_fmin_f32_local(float addrspace(3)* %ptr, float %val
; GCN: atomicrmw.end:
; GCN-NEXT: ret float [[TMP7]]
;
- %res = atomicrmw fmin float addrspace(3)* %ptr, float %value seq_cst
+ %res = atomicrmw fmin ptr addrspace(3) %ptr, float %value seq_cst
ret float %res
}
-define half @test_atomicrmw_fmin_f16_flat(half* %ptr, half %value) {
+define half @test_atomicrmw_fmin_f16_flat(ptr %ptr, half %value) {
; GCN-LABEL: @test_atomicrmw_fmin_f16_flat(
-; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4)
-; GCN-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64
+; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4)
+; GCN-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64
; GCN-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GCN-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GCN-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GCN-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GCN-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32*
-; GCN-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4
+; GCN-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -91,7 +87,7 @@ define half @test_atomicrmw_fmin_f16_flat(half* %ptr, half %value) {
; GCN-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GCN-NEXT: [[TMP7:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP7:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1
; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0
; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -101,21 +97,20 @@ define half @test_atomicrmw_fmin_f16_flat(half* %ptr, half %value) {
; GCN-NEXT: [[TMP8:%.*]] = bitcast i16 [[EXTRACTED4]] to half
; GCN-NEXT: ret half [[TMP8]]
;
- %res = atomicrmw fmin half* %ptr, half %value seq_cst
+ %res = atomicrmw fmin ptr %ptr, half %value seq_cst
ret half %res
}
-define half @test_atomicrmw_fmin_f16_global(half addrspace(1)* %ptr, half %value) {
+define half @test_atomicrmw_fmin_f16_global(ptr addrspace(1) %ptr, half %value) {
; GCN-LABEL: @test_atomicrmw_fmin_f16_global(
-; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(1)* @llvm.ptrmask.p1f16.i64(half addrspace(1)* [[PTR:%.*]], i64 -4)
-; GCN-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(1)* [[PTR]] to i64
+; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; GCN-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; GCN-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GCN-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GCN-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GCN-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GCN-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
-; GCN-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; GCN-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -128,7 +123,7 @@ define half @test_atomicrmw_fmin_f16_global(half addrspace(1)* %ptr, half %value
; GCN-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GCN-NEXT: [[TMP7:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP7:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1
; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0
; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -138,14 +133,13 @@ define half @test_atomicrmw_fmin_f16_global(half addrspace(1)* %ptr, half %value
; GCN-NEXT: [[TMP8:%.*]] = bitcast i16 [[EXTRACTED4]] to half
; GCN-NEXT: ret half [[TMP8]]
;
- %res = atomicrmw fmin half addrspace(1)* %ptr, half %value seq_cst
+ %res = atomicrmw fmin ptr addrspace(1) %ptr, half %value seq_cst
ret half %res
}
-define half @test_atomicrmw_fmin_f16_global_align4(half addrspace(1)* %ptr, half %value) {
+define half @test_atomicrmw_fmin_f16_global_align4(ptr addrspace(1) %ptr, half %value) {
; GCN-LABEL: @test_atomicrmw_fmin_f16_global_align4(
-; GCN-NEXT: [[ALIGNEDADDR:%.*]] = bitcast half addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)*
-; GCN-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4
+; GCN-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -156,7 +150,7 @@ define half @test_atomicrmw_fmin_f16_global_align4(half addrspace(1)* %ptr, half
; GCN-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP4]] to i32
; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], -65536
; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[EXTENDED]]
-; GCN-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0
; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -165,21 +159,20 @@ define half @test_atomicrmw_fmin_f16_global_align4(half addrspace(1)* %ptr, half
; GCN-NEXT: [[TMP6:%.*]] = bitcast i16 [[EXTRACTED1]] to half
; GCN-NEXT: ret half [[TMP6]]
;
- %res = atomicrmw fmin half addrspace(1)* %ptr, half %value seq_cst, align 4
+ %res = atomicrmw fmin ptr addrspace(1) %ptr, half %value seq_cst, align 4
ret half %res
}
-define half @test_atomicrmw_fmin_f16_local(half addrspace(3)* %ptr, half %value) {
+define half @test_atomicrmw_fmin_f16_local(ptr addrspace(3) %ptr, half %value) {
; GCN-LABEL: @test_atomicrmw_fmin_f16_local(
-; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(3)* @llvm.ptrmask.p3f16.i64(half addrspace(3)* [[PTR:%.*]], i64 -4)
-; GCN-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(3)* [[PTR]] to i64
+; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[PTR:%.*]], i64 -4)
+; GCN-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i64
; GCN-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GCN-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GCN-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GCN-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GCN-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)*
-; GCN-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4
+; GCN-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -192,7 +185,7 @@ define half @test_atomicrmw_fmin_f16_local(half addrspace(3)* %ptr, half %value)
; GCN-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GCN-NEXT: [[TMP7:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP7:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1
; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0
; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -202,21 +195,20 @@ define half @test_atomicrmw_fmin_f16_local(half addrspace(3)* %ptr, half %value)
; GCN-NEXT: [[TMP8:%.*]] = bitcast i16 [[EXTRACTED4]] to half
; GCN-NEXT: ret half [[TMP8]]
;
- %res = atomicrmw fmin half addrspace(3)* %ptr, half %value seq_cst
+ %res = atomicrmw fmin ptr addrspace(3) %ptr, half %value seq_cst
ret half %res
}
-define double @test_atomicrmw_fmin_f64_flat(double* %ptr, double %value) {
+define double @test_atomicrmw_fmin_f64_flat(ptr %ptr, double %value) {
; GCN-LABEL: @test_atomicrmw_fmin_f64_flat(
-; GCN-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8
+; GCN-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ]
; GCN-NEXT: [[TMP2:%.*]] = call double @llvm.minnum.f64(double [[LOADED]], double [[VALUE:%.*]])
-; GCN-NEXT: [[TMP3:%.*]] = bitcast double* [[PTR]] to i64*
; GCN-NEXT: [[TMP4:%.*]] = bitcast double [[TMP2]] to i64
; GCN-NEXT: [[TMP5:%.*]] = bitcast double [[LOADED]] to i64
-; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i64* [[TMP3]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8
+; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP6]], 1
; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
; GCN-NEXT: [[TMP7]] = bitcast i64 [[NEWLOADED]] to double
@@ -224,21 +216,20 @@ define double @test_atomicrmw_fmin_f64_flat(double* %ptr, double %value) {
; GCN: atomicrmw.end:
; GCN-NEXT: ret double [[TMP7]]
;
- %res = atomicrmw fmin double* %ptr, double %value seq_cst
+ %res = atomicrmw fmin ptr %ptr, double %value seq_cst
ret double %res
}
-define double @test_atomicrmw_fmin_f64_global(double addrspace(1)* %ptr, double %value) {
+define double @test_atomicrmw_fmin_f64_global(ptr addrspace(1) %ptr, double %value) {
; GCN-LABEL: @test_atomicrmw_fmin_f64_global(
-; GCN-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8
+; GCN-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ]
; GCN-NEXT: [[TMP2:%.*]] = call double @llvm.minnum.f64(double [[LOADED]], double [[VALUE:%.*]])
-; GCN-NEXT: [[TMP3:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)*
; GCN-NEXT: [[TMP4:%.*]] = bitcast double [[TMP2]] to i64
; GCN-NEXT: [[TMP5:%.*]] = bitcast double [[LOADED]] to i64
-; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i64 addrspace(1)* [[TMP3]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8
+; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP6]], 1
; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
; GCN-NEXT: [[TMP7]] = bitcast i64 [[NEWLOADED]] to double
@@ -246,21 +237,20 @@ define double @test_atomicrmw_fmin_f64_global(double addrspace(1)* %ptr, double
; GCN: atomicrmw.end:
; GCN-NEXT: ret double [[TMP7]]
;
- %res = atomicrmw fmin double addrspace(1)* %ptr, double %value seq_cst
+ %res = atomicrmw fmin ptr addrspace(1) %ptr, double %value seq_cst
ret double %res
}
-define double @test_atomicrmw_fmin_f64_local(double addrspace(3)* %ptr, double %value) {
+define double @test_atomicrmw_fmin_f64_local(ptr addrspace(3) %ptr, double %value) {
; GCN-LABEL: @test_atomicrmw_fmin_f64_local(
-; GCN-NEXT: [[TMP1:%.*]] = load double, double addrspace(3)* [[PTR:%.*]], align 8
+; GCN-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(3) [[PTR:%.*]], align 8
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ]
; GCN-NEXT: [[TMP2:%.*]] = call double @llvm.minnum.f64(double [[LOADED]], double [[VALUE:%.*]])
-; GCN-NEXT: [[TMP3:%.*]] = bitcast double addrspace(3)* [[PTR]] to i64 addrspace(3)*
; GCN-NEXT: [[TMP4:%.*]] = bitcast double [[TMP2]] to i64
; GCN-NEXT: [[TMP5:%.*]] = bitcast double [[LOADED]] to i64
-; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i64 addrspace(3)* [[TMP3]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8
+; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP6]], 1
; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0
; GCN-NEXT: [[TMP7]] = bitcast i64 [[NEWLOADED]] to double
@@ -268,6 +258,6 @@ define double @test_atomicrmw_fmin_f64_local(double addrspace(3)* %ptr, double %
; GCN: atomicrmw.end:
; GCN-NEXT: ret double [[TMP7]]
;
- %res = atomicrmw fmin double addrspace(3)* %ptr, double %value seq_cst
+ %res = atomicrmw fmin ptr addrspace(3) %ptr, double %value seq_cst
ret double %res
}
diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fsub.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fsub.ll
index cb5306b3add7e..44e24466c9b63 100644
--- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fsub.ll
+++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fsub.ll
@@ -2,17 +2,16 @@
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -atomic-expand %s | FileCheck -check-prefix=GCN %s
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -atomic-expand %s | FileCheck -check-prefix=GCN %s
-define float @test_atomicrmw_fsub_f32_flat(float* %ptr, float %value) {
+define float @test_atomicrmw_fsub_f32_flat(ptr %ptr, float %value) {
; GCN-LABEL: @test_atomicrmw_fsub_f32_flat(
-; GCN-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; GCN-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GCN-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]]
-; GCN-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; GCN-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GCN-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GCN-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GCN-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -20,21 +19,20 @@ define float @test_atomicrmw_fsub_f32_flat(float* %ptr, float %value) {
; GCN: atomicrmw.end:
; GCN-NEXT: ret float [[TMP6]]
;
- %res = atomicrmw fsub float* %ptr, float %value seq_cst
+ %res = atomicrmw fsub ptr %ptr, float %value seq_cst
ret float %res
}
-define float @test_atomicrmw_fsub_f32_global(float addrspace(1)* %ptr, float %value) {
+define float @test_atomicrmw_fsub_f32_global(ptr addrspace(1) %ptr, float %value) {
; GCN-LABEL: @test_atomicrmw_fsub_f32_global(
-; GCN-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; GCN-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GCN-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]]
-; GCN-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; GCN-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GCN-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GCN-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GCN-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -42,21 +40,20 @@ define float @test_atomicrmw_fsub_f32_global(float addrspace(1)* %ptr, float %va
; GCN: atomicrmw.end:
; GCN-NEXT: ret float [[TMP6]]
;
- %res = atomicrmw fsub float addrspace(1)* %ptr, float %value seq_cst
+ %res = atomicrmw fsub ptr addrspace(1) %ptr, float %value seq_cst
ret float %res
}
-define float @test_atomicrmw_fsub_f32_local(float addrspace(3)* %ptr, float %value) {
+define float @test_atomicrmw_fsub_f32_local(ptr addrspace(3) %ptr, float %value) {
; GCN-LABEL: @test_atomicrmw_fsub_f32_local(
-; GCN-NEXT: [[TMP1:%.*]] = load float, float addrspace(3)* [[PTR:%.*]], align 4
+; GCN-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(3) [[PTR:%.*]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GCN-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]]
-; GCN-NEXT: [[TMP2:%.*]] = bitcast float addrspace(3)* [[PTR]] to i32 addrspace(3)*
; GCN-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; GCN-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; GCN-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(3)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; GCN-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -64,21 +61,20 @@ define float @test_atomicrmw_fsub_f32_local(float addrspace(3)* %ptr, float %val
; GCN: atomicrmw.end:
; GCN-NEXT: ret float [[TMP6]]
;
- %res = atomicrmw fsub float addrspace(3)* %ptr, float %value seq_cst
+ %res = atomicrmw fsub ptr addrspace(3) %ptr, float %value seq_cst
ret float %res
}
-define half @test_atomicrmw_fsub_f16_flat(half* %ptr, half %value) {
+define half @test_atomicrmw_fsub_f16_flat(ptr %ptr, half %value) {
; GCN-LABEL: @test_atomicrmw_fsub_f16_flat(
-; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4)
-; GCN-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64
+; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4)
+; GCN-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64
; GCN-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GCN-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GCN-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GCN-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GCN-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32*
-; GCN-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4
+; GCN-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -91,7 +87,7 @@ define half @test_atomicrmw_fsub_f16_flat(half* %ptr, half %value) {
; GCN-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -101,21 +97,20 @@ define half @test_atomicrmw_fsub_f16_flat(half* %ptr, half %value) {
; GCN-NEXT: [[TMP7:%.*]] = bitcast i16 [[EXTRACTED4]] to half
; GCN-NEXT: ret half [[TMP7]]
;
- %res = atomicrmw fsub half* %ptr, half %value seq_cst
+ %res = atomicrmw fsub ptr %ptr, half %value seq_cst
ret half %res
}
-define half @test_atomicrmw_fsub_f16_global(half addrspace(1)* %ptr, half %value) {
+define half @test_atomicrmw_fsub_f16_global(ptr addrspace(1) %ptr, half %value) {
; GCN-LABEL: @test_atomicrmw_fsub_f16_global(
-; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(1)* @llvm.ptrmask.p1f16.i64(half addrspace(1)* [[PTR:%.*]], i64 -4)
-; GCN-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(1)* [[PTR]] to i64
+; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4)
+; GCN-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64
; GCN-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GCN-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GCN-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GCN-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GCN-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)*
-; GCN-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4
+; GCN-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -128,7 +123,7 @@ define half @test_atomicrmw_fsub_f16_global(half addrspace(1)* %ptr, half %value
; GCN-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -138,14 +133,13 @@ define half @test_atomicrmw_fsub_f16_global(half addrspace(1)* %ptr, half %value
; GCN-NEXT: [[TMP7:%.*]] = bitcast i16 [[EXTRACTED4]] to half
; GCN-NEXT: ret half [[TMP7]]
;
- %res = atomicrmw fsub half addrspace(1)* %ptr, half %value seq_cst
+ %res = atomicrmw fsub ptr addrspace(1) %ptr, half %value seq_cst
ret half %res
}
-define half @test_atomicrmw_fsub_f16_global_align4(half addrspace(1)* %ptr, half %value) {
+define half @test_atomicrmw_fsub_f16_global_align4(ptr addrspace(1) %ptr, half %value) {
; GCN-LABEL: @test_atomicrmw_fsub_f16_global_align4(
-; GCN-NEXT: [[ALIGNEDADDR:%.*]] = bitcast half addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)*
-; GCN-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4
+; GCN-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -156,7 +150,7 @@ define half @test_atomicrmw_fsub_f16_global_align4(half addrspace(1)* %ptr, half
; GCN-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP3]] to i32
; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], -65536
; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[EXTENDED]]
-; GCN-NEXT: [[TMP4:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1
; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP4]], 0
; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -165,21 +159,20 @@ define half @test_atomicrmw_fsub_f16_global_align4(half addrspace(1)* %ptr, half
; GCN-NEXT: [[TMP5:%.*]] = bitcast i16 [[EXTRACTED1]] to half
; GCN-NEXT: ret half [[TMP5]]
;
- %res = atomicrmw fsub half addrspace(1)* %ptr, half %value seq_cst, align 4
+ %res = atomicrmw fsub ptr addrspace(1) %ptr, half %value seq_cst, align 4
ret half %res
}
-define half @test_atomicrmw_fsub_f16_local(half addrspace(3)* %ptr, half %value) {
+define half @test_atomicrmw_fsub_f16_local(ptr addrspace(3) %ptr, half %value) {
; GCN-LABEL: @test_atomicrmw_fsub_f16_local(
-; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(3)* @llvm.ptrmask.p3f16.i64(half addrspace(3)* [[PTR:%.*]], i64 -4)
-; GCN-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(3)* [[PTR]] to i64
+; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[PTR:%.*]], i64 -4)
+; GCN-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i64
; GCN-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; GCN-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3
; GCN-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; GCN-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; GCN-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)*
-; GCN-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4
+; GCN-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -192,7 +185,7 @@ define half @test_atomicrmw_fsub_f16_local(half addrspace(3)* %ptr, half %value)
; GCN-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
+; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1
; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0
; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -202,21 +195,20 @@ define half @test_atomicrmw_fsub_f16_local(half addrspace(3)* %ptr, half %value)
; GCN-NEXT: [[TMP7:%.*]] = bitcast i16 [[EXTRACTED4]] to half
; GCN-NEXT: ret half [[TMP7]]
;
- %res = atomicrmw fsub half addrspace(3)* %ptr, half %value seq_cst
+ %res = atomicrmw fsub ptr addrspace(3) %ptr, half %value seq_cst
ret half %res
}
-define double @test_atomicrmw_fsub_f64_flat(double* %ptr, double %value) {
+define double @test_atomicrmw_fsub_f64_flat(ptr %ptr, double %value) {
; GCN-LABEL: @test_atomicrmw_fsub_f64_flat(
-; GCN-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8
+; GCN-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GCN-NEXT: [[NEW:%.*]] = fsub double [[LOADED]], [[VALUE:%.*]]
-; GCN-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64*
; GCN-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GCN-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GCN-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
+; GCN-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GCN-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -224,21 +216,20 @@ define double @test_atomicrmw_fsub_f64_flat(double* %ptr, double %value) {
; GCN: atomicrmw.end:
; GCN-NEXT: ret double [[TMP6]]
;
- %res = atomicrmw fsub double* %ptr, double %value seq_cst
+ %res = atomicrmw fsub ptr %ptr, double %value seq_cst
ret double %res
}
-define double @test_atomicrmw_fsub_f64_global(double addrspace(1)* %ptr, double %value) {
+define double @test_atomicrmw_fsub_f64_global(ptr addrspace(1) %ptr, double %value) {
; GCN-LABEL: @test_atomicrmw_fsub_f64_global(
-; GCN-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8
+; GCN-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GCN-NEXT: [[NEW:%.*]] = fsub double [[LOADED]], [[VALUE:%.*]]
-; GCN-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)*
; GCN-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GCN-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GCN-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
+; GCN-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GCN-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -246,21 +237,20 @@ define double @test_atomicrmw_fsub_f64_global(double addrspace(1)* %ptr, double
; GCN: atomicrmw.end:
; GCN-NEXT: ret double [[TMP6]]
;
- %res = atomicrmw fsub double addrspace(1)* %ptr, double %value seq_cst
+ %res = atomicrmw fsub ptr addrspace(1) %ptr, double %value seq_cst
ret double %res
}
-define double @test_atomicrmw_fsub_f64_local(double addrspace(3)* %ptr, double %value) {
+define double @test_atomicrmw_fsub_f64_local(ptr addrspace(3) %ptr, double %value) {
; GCN-LABEL: @test_atomicrmw_fsub_f64_local(
-; GCN-NEXT: [[TMP1:%.*]] = load double, double addrspace(3)* [[PTR:%.*]], align 8
+; GCN-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(3) [[PTR:%.*]], align 8
; GCN-NEXT: br label [[ATOMICRMW_START:%.*]]
; GCN: atomicrmw.start:
; GCN-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; GCN-NEXT: [[NEW:%.*]] = fsub double [[LOADED]], [[VALUE:%.*]]
-; GCN-NEXT: [[TMP2:%.*]] = bitcast double addrspace(3)* [[PTR]] to i64 addrspace(3)*
; GCN-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; GCN-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; GCN-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(3)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
+; GCN-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8
; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; GCN-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -268,6 +258,6 @@ define double @test_atomicrmw_fsub_f64_local(double addrspace(3)* %ptr, double %
; GCN: atomicrmw.end:
; GCN-NEXT: ret double [[TMP6]]
;
- %res = atomicrmw fsub double addrspace(3)* %ptr, double %value seq_cst
+ %res = atomicrmw fsub ptr addrspace(3) %ptr, double %value seq_cst
ret double %res
}
diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-nand.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-nand.ll
index 95e28fa89174c..40e2af57c7e2f 100644
--- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-nand.ll
+++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-nand.ll
@@ -2,59 +2,59 @@
; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -atomic-expand %s | FileCheck %s
; RUN: opt -mtriple=r600-mesa-mesa3d -S -atomic-expand %s | FileCheck %s
-define i32 @test_atomicrmw_nand_i32_flat(i32* %ptr, i32 %value) {
+define i32 @test_atomicrmw_nand_i32_flat(ptr %ptr, i32 %value) {
; CHECK-LABEL: @test_atomicrmw_nand_i32_flat(
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[LOADED]], [[VALUE:%.*]]
; CHECK-NEXT: [[NEW:%.*]] = xor i32 [[TMP2]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg i32* [[PTR]], i32 [[LOADED]], i32 [[NEW]] seq_cst seq_cst
+; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg ptr [[PTR]], i32 [[LOADED]], i32 [[NEW]] seq_cst seq_cst
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP3]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP3]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
; CHECK: atomicrmw.end:
; CHECK-NEXT: ret i32 [[NEWLOADED]]
;
- %res = atomicrmw nand i32* %ptr, i32 %value seq_cst
+ %res = atomicrmw nand ptr %ptr, i32 %value seq_cst
ret i32 %res
}
-define i32 @test_atomicrmw_nand_i32_global(i32 addrspace(1)* %ptr, i32 %value) {
+define i32 @test_atomicrmw_nand_i32_global(ptr addrspace(1) %ptr, i32 %value) {
; CHECK-LABEL: @test_atomicrmw_nand_i32_global(
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[LOADED]], [[VALUE:%.*]]
; CHECK-NEXT: [[NEW:%.*]] = xor i32 [[TMP2]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg i32 addrspace(1)* [[PTR]], i32 [[LOADED]], i32 [[NEW]] seq_cst seq_cst
+; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[NEW]] seq_cst seq_cst
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP3]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP3]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
; CHECK: atomicrmw.end:
; CHECK-NEXT: ret i32 [[NEWLOADED]]
;
- %res = atomicrmw nand i32 addrspace(1)* %ptr, i32 %value seq_cst
+ %res = atomicrmw nand ptr addrspace(1) %ptr, i32 %value seq_cst
ret i32 %res
}
-define i32 @test_atomicrmw_nand_i32_local(i32 addrspace(3)* %ptr, i32 %value) {
+define i32 @test_atomicrmw_nand_i32_local(ptr addrspace(3) %ptr, i32 %value) {
; CHECK-LABEL: @test_atomicrmw_nand_i32_local(
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(3)* [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(3) [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[LOADED]], [[VALUE:%.*]]
; CHECK-NEXT: [[NEW:%.*]] = xor i32 [[TMP2]], -1
-; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg i32 addrspace(3)* [[PTR]], i32 [[LOADED]], i32 [[NEW]] seq_cst seq_cst
+; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i32 [[LOADED]], i32 [[NEW]] seq_cst seq_cst
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP3]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP3]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
; CHECK: atomicrmw.end:
; CHECK-NEXT: ret i32 [[NEWLOADED]]
;
- %res = atomicrmw nand i32 addrspace(3)* %ptr, i32 %value seq_cst
+ %res = atomicrmw nand ptr addrspace(3) %ptr, i32 %value seq_cst
ret i32 %res
}
diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/unaligned-atomic.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/unaligned-atomic.ll
index 56db423af6f50..bdfd90dc11dca 100644
--- a/llvm/test/Transforms/AtomicExpand/AMDGPU/unaligned-atomic.ll
+++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/unaligned-atomic.ll
@@ -2,34 +2,30 @@
; The AtomicExpand pass cannot handle missing libcalls (yet) so reports a fatal error.
; CHECK: LLVM ERROR: expandAtomicOpToLibcall shouldn't fail for Load
-define i32 @atomic_load_global_align1(i32 addrspace(1)* %ptr) {
+define i32 @atomic_load_global_align1(ptr addrspace(1) %ptr) {
; GCN-LABEL: @atomic_load_global_align1(
-; GCN-NEXT: [[TMP1:%.*]] = bitcast i32 addrspace(1)* [[PTR:%.*]] to i8 addrspace(1)*
-; GCN-NEXT: [[TMP2:%.*]] = addrspacecast i8 addrspace(1)* [[TMP1]] to i8*
+; GCN-NEXT: [[TMP2:%.*]] = addrspacecast ptr addrspace(1) [[PTR:%.*]] to ptr
; GCN-NEXT: [[TMP3:%.*]] = alloca i32, align 4
-; GCN-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP3]] to i8*
-; GCN-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]])
-; GCN-NEXT: call void @0(i64 4, i8* [[TMP2]], i8* [[TMP4]], i32 5)
-; GCN-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP3]], align 4
-; GCN-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP4]])
+; GCN-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP3]])
+; GCN-NEXT: call void @0(i64 4, ptr [[TMP2]], ptr [[TMP3]], i32 5)
+; GCN-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP3]], align 4
+; GCN-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP3]])
; GCN-NEXT: ret i32 [[TMP5]]
;
- %val = load atomic i32, i32 addrspace(1)* %ptr seq_cst, align 1
+ %val = load atomic i32, ptr addrspace(1) %ptr seq_cst, align 1
ret i32 %val
}
-define void @atomic_store_global_align1(i32 addrspace(1)* %ptr, i32 %val) {
+define void @atomic_store_global_align1(ptr addrspace(1) %ptr, i32 %val) {
; GCN-LABEL: @atomic_store_global_align1(
-; GCN-NEXT: [[TMP1:%.*]] = bitcast i32 addrspace(1)* [[PTR:%.*]] to i8 addrspace(1)*
-; GCN-NEXT: [[TMP2:%.*]] = addrspacecast i8 addrspace(1)* [[TMP1]] to i8*
+; GCN-NEXT: [[TMP2:%.*]] = addrspacecast ptr addrspace(1) [[PTR:%.*]] to ptr
; GCN-NEXT: [[TMP3:%.*]] = alloca i32, align 4
-; GCN-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP3]] to i8*
-; GCN-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]])
-; GCN-NEXT: store i32 [[VAL:%.*]], i32* [[TMP3]], align 4
-; GCN-NEXT: call void @1(i64 4, i8* [[TMP2]], i8* [[TMP4]], i32 0)
-; GCN-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP4]])
+; GCN-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP3]])
+; GCN-NEXT: store i32 [[VAL:%.*]], ptr [[TMP3]], align 4
+; GCN-NEXT: call void @1(i64 4, ptr [[TMP2]], ptr [[TMP3]], i32 0)
+; GCN-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP3]])
; GCN-NEXT: ret void
;
- store atomic i32 %val, i32 addrspace(1)* %ptr monotonic, align 1
+ store atomic i32 %val, ptr addrspace(1) %ptr monotonic, align 1
ret void
}
diff --git a/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v7.ll b/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v7.ll
index 1cc20eb9f71e4..353aafb9727a5 100644
--- a/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v7.ll
+++ b/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v7.ll
@@ -1,105 +1,104 @@
; RUN: opt -S -o - -mtriple=armv7-apple-ios7.0 -atomic-expand -codegen-opt-level=1 %s | FileCheck %s
-define i8 @test_atomic_xchg_i8(i8* %ptr, i8 %xchgend) {
+define i8 @test_atomic_xchg_i8(ptr %ptr, i8 %xchgend) {
; CHECK-LABEL: @test_atomic_xchg_i8
; CHECK-NOT: dmb
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
+; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
; CHECK: [[NEWVAL32:%.*]] = zext i8 %xchgend to i32
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]:
; CHECK-NOT: dmb
; CHECK: ret i8 [[OLDVAL]]
- %res = atomicrmw xchg i8* %ptr, i8 %xchgend monotonic
+ %res = atomicrmw xchg ptr %ptr, i8 %xchgend monotonic
ret i8 %res
}
-define i16 @test_atomic_add_i16(i16* %ptr, i16 %addend) {
+define i16 @test_atomic_add_i16(ptr %ptr, i16 %addend) {
; CHECK-LABEL: @test_atomic_add_i16
; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* elementtype(i16) %ptr)
+; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16
; CHECK: [[NEWVAL:%.*]] = add i16 [[OLDVAL]], %addend
; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* elementtype(i16) %ptr)
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i16) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]:
; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: ret i16 [[OLDVAL]]
- %res = atomicrmw add i16* %ptr, i16 %addend seq_cst
+ %res = atomicrmw add ptr %ptr, i16 %addend seq_cst
ret i16 %res
}
-define i32 @test_atomic_sub_i32(i32* %ptr, i32 %subend) {
+define i32 @test_atomic_sub_i32(ptr %ptr, i32 %subend) {
; CHECK-LABEL: @test_atomic_sub_i32
; CHECK-NOT: dmb
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %ptr)
+; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %ptr)
; CHECK: [[NEWVAL:%.*]] = sub i32 [[OLDVAL]], %subend
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 [[NEWVAL]], i32* elementtype(i32) %ptr)
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL]], ptr elementtype(i32) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]:
; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: ret i32 [[OLDVAL]]
- %res = atomicrmw sub i32* %ptr, i32 %subend acquire
+ %res = atomicrmw sub ptr %ptr, i32 %subend acquire
ret i32 %res
}
-define i8 @test_atomic_and_i8(i8* %ptr, i8 %andend) {
+define i8 @test_atomic_and_i8(ptr %ptr, i8 %andend) {
; CHECK-LABEL: @test_atomic_and_i8
; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
+; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
; CHECK: [[NEWVAL:%.*]] = and i8 [[OLDVAL]], %andend
; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]:
; CHECK-NOT: dmb
; CHECK: ret i8 [[OLDVAL]]
- %res = atomicrmw and i8* %ptr, i8 %andend release
+ %res = atomicrmw and ptr %ptr, i8 %andend release
ret i8 %res
}
-define i16 @test_atomic_nand_i16(i16* %ptr, i16 %nandend) {
+define i16 @test_atomic_nand_i16(ptr %ptr, i16 %nandend) {
; CHECK-LABEL: @test_atomic_nand_i16
; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* elementtype(i16) %ptr)
+; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16
; CHECK: [[NEWVAL_TMP:%.*]] = and i16 [[OLDVAL]], %nandend
; CHECK: [[NEWVAL:%.*]] = xor i16 [[NEWVAL_TMP]], -1
; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* elementtype(i16) %ptr)
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i16) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]:
; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: ret i16 [[OLDVAL]]
- %res = atomicrmw nand i16* %ptr, i16 %nandend seq_cst
+ %res = atomicrmw nand ptr %ptr, i16 %nandend seq_cst
ret i16 %res
}
-define i64 @test_atomic_or_i64(i64* %ptr, i64 %orend) {
+define i64 @test_atomic_or_i64(ptr %ptr, i64 %orend) {
; CHECK-LABEL: @test_atomic_or_i64
; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8*
-; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]])
+; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(ptr %ptr)
; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0
; CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1
; CHECK: [[LO64:%.*]] = zext i32 [[LO]] to i64
@@ -110,122 +109,121 @@ define i64 @test_atomic_or_i64(i64* %ptr, i64 %orend) {
; CHECK: [[NEWLO:%.*]] = trunc i64 [[NEWVAL]] to i32
; CHECK: [[NEWHI_TMP:%.*]] = lshr i64 [[NEWVAL]], 32
; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32
-; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8*
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]])
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], ptr %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]:
; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: ret i64 [[OLDVAL]]
- %res = atomicrmw or i64* %ptr, i64 %orend seq_cst
+ %res = atomicrmw or ptr %ptr, i64 %orend seq_cst
ret i64 %res
}
-define i8 @test_atomic_xor_i8(i8* %ptr, i8 %xorend) {
+define i8 @test_atomic_xor_i8(ptr %ptr, i8 %xorend) {
; CHECK-LABEL: @test_atomic_xor_i8
; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
+; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
; CHECK: [[NEWVAL:%.*]] = xor i8 [[OLDVAL]], %xorend
; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]:
; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: ret i8 [[OLDVAL]]
- %res = atomicrmw xor i8* %ptr, i8 %xorend seq_cst
+ %res = atomicrmw xor ptr %ptr, i8 %xorend seq_cst
ret i8 %res
}
-define i8 @test_atomic_max_i8(i8* %ptr, i8 %maxend) {
+define i8 @test_atomic_max_i8(ptr %ptr, i8 %maxend) {
; CHECK-LABEL: @test_atomic_max_i8
; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
+; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
; CHECK: [[WANT_OLD:%.*]] = icmp sgt i8 [[OLDVAL]], %maxend
; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %maxend
; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]:
; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: ret i8 [[OLDVAL]]
- %res = atomicrmw max i8* %ptr, i8 %maxend seq_cst
+ %res = atomicrmw max ptr %ptr, i8 %maxend seq_cst
ret i8 %res
}
-define i8 @test_atomic_min_i8(i8* %ptr, i8 %minend) {
+define i8 @test_atomic_min_i8(ptr %ptr, i8 %minend) {
; CHECK-LABEL: @test_atomic_min_i8
; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
+; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
; CHECK: [[WANT_OLD:%.*]] = icmp sle i8 [[OLDVAL]], %minend
; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %minend
; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]:
; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: ret i8 [[OLDVAL]]
- %res = atomicrmw min i8* %ptr, i8 %minend seq_cst
+ %res = atomicrmw min ptr %ptr, i8 %minend seq_cst
ret i8 %res
}
-define i8 @test_atomic_umax_i8(i8* %ptr, i8 %umaxend) {
+define i8 @test_atomic_umax_i8(ptr %ptr, i8 %umaxend) {
; CHECK-LABEL: @test_atomic_umax_i8
; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
+; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
; CHECK: [[WANT_OLD:%.*]] = icmp ugt i8 [[OLDVAL]], %umaxend
; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %umaxend
; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]:
; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: ret i8 [[OLDVAL]]
- %res = atomicrmw umax i8* %ptr, i8 %umaxend seq_cst
+ %res = atomicrmw umax ptr %ptr, i8 %umaxend seq_cst
ret i8 %res
}
-define i8 @test_atomic_umin_i8(i8* %ptr, i8 %uminend) {
+define i8 @test_atomic_umin_i8(ptr %ptr, i8 %uminend) {
; CHECK-LABEL: @test_atomic_umin_i8
; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
+; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
; CHECK: [[WANT_OLD:%.*]] = icmp ule i8 [[OLDVAL]], %uminend
; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %uminend
; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]:
; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: ret i8 [[OLDVAL]]
- %res = atomicrmw umin i8* %ptr, i8 %uminend seq_cst
+ %res = atomicrmw umin ptr %ptr, i8 %uminend seq_cst
ret i8 %res
}
-define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) {
+define i8 @test_cmpxchg_i8_seqcst_seqcst(ptr %ptr, i8 %desired, i8 %newval) {
; CHECK-LABEL: @test_cmpxchg_i8_seqcst_seqcst
; CHECK: br label %[[START:.*]]
; CHECK: [[START]]:
-; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
+; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i8 [[OLDVAL]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
@@ -237,12 +235,12 @@ define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) {
; CHECK: [[LOOP]]:
; CHECK: [[LOADED_LOOP:%.*]] = phi i8 [ [[OLDVAL]], %[[FENCED_STORE]] ], [ [[OLDVAL_LOOP:%.*]], %[[RELEASED_LOAD:.*]] ]
; CHECK: [[NEWVAL32:%.*]] = zext i8 %newval to i32
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[RELEASED_LOAD]]
; CHECK: [[RELEASED_LOAD]]:
-; CHECK: [[OLDVAL32_LOOP:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
+; CHECK: [[OLDVAL32_LOOP:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr)
; CHECK: [[OLDVAL_LOOP]] = trunc i32 [[OLDVAL32_LOOP]] to i8
; CHECK: [[SHOULD_STORE_LOOP:%.*]] = icmp eq i8 [[OLDVAL_LOOP]], %desired
; CHECK: br i1 [[SHOULD_STORE_LOOP]], label %[[LOOP]], label %[[NO_STORE_BB]]
@@ -266,17 +264,17 @@ define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) {
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
; CHECK: ret i8 [[LOADED]]
- %pairold = cmpxchg i8* %ptr, i8 %desired, i8 %newval seq_cst seq_cst
+ %pairold = cmpxchg ptr %ptr, i8 %desired, i8 %newval seq_cst seq_cst
%old = extractvalue { i8, i1 } %pairold, 0
ret i8 %old
}
-define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newval) {
+define i16 @test_cmpxchg_i16_seqcst_monotonic(ptr %ptr, i16 %desired, i16 %newval) {
; CHECK-LABEL: @test_cmpxchg_i16_seqcst_monotonic
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* elementtype(i16) %ptr)
+; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i16
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i16 [[OLDVAL]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
@@ -288,12 +286,12 @@ define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newv
; CHECK: [[LOOP]]:
; CHECK: [[LOADED_LOOP:%.*]] = phi i16 [ [[OLDVAL]], %[[FENCED_STORE]] ], [ [[OLDVAL_LOOP:%.*]], %[[RELEASED_LOAD:.*]] ]
; CHECK: [[NEWVAL32:%.*]] = zext i16 %newval to i32
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* elementtype(i16) %ptr)
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i16) %ptr)
; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[RELEASED_LOAD:.*]]
; CHECK: [[RELEASED_LOAD]]:
-; CHECK: [[OLDVAL32_LOOP:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* elementtype(i16) %ptr)
+; CHECK: [[OLDVAL32_LOOP:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %ptr)
; CHECK: [[OLDVAL_LOOP]] = trunc i32 [[OLDVAL32_LOOP]] to i16
; CHECK: [[SHOULD_STORE_LOOP:%.*]] = icmp eq i16 [[OLDVAL_LOOP]], %desired
; CHECK: br i1 [[SHOULD_STORE_LOOP]], label %[[LOOP]], label %[[NO_STORE_BB]]
@@ -317,18 +315,18 @@ define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newv
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
; CHECK: ret i16 [[LOADED]]
- %pairold = cmpxchg i16* %ptr, i16 %desired, i16 %newval seq_cst monotonic
+ %pairold = cmpxchg ptr %ptr, i16 %desired, i16 %newval seq_cst monotonic
%old = extractvalue { i16, i1 } %pairold, 0
ret i16 %old
}
-define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newval) {
+define i32 @test_cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %desired, i32 %newval) {
; CHECK-LABEL: @test_cmpxchg_i32_acquire_acquire
; CHECK-NOT: dmb
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %ptr)
+; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %ptr)
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[OLDVAL]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
@@ -337,7 +335,7 @@ define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newva
; CHECK: [[TRY_STORE]]:
; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[OLDVAL]], %[[FENCED_STORE]] ]
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %newval, i32* elementtype(i32) %ptr)
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 %newval, ptr elementtype(i32) %ptr)
; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]]
@@ -360,19 +358,18 @@ define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newva
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
; CHECK: ret i32 [[LOADED_EXIT]]
- %pairold = cmpxchg i32* %ptr, i32 %desired, i32 %newval acquire acquire
+ %pairold = cmpxchg ptr %ptr, i32 %desired, i32 %newval acquire acquire
%old = extractvalue { i32, i1 } %pairold, 0
ret i32 %old
}
-define i64 @test_cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %desired, i64 %newval) {
+define i64 @test_cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %desired, i64 %newval) {
; CHECK-LABEL: @test_cmpxchg_i64_monotonic_monotonic
; CHECK-NOT: dmb
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8*
-; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]])
+; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(ptr %ptr)
; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0
; CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1
; CHECK: [[LO64:%.*]] = zext i32 [[LO]] to i64
@@ -390,8 +387,7 @@ define i64 @test_cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %desired, i64 %n
; CHECK: [[NEWLO:%.*]] = trunc i64 %newval to i32
; CHECK: [[NEWHI_TMP:%.*]] = lshr i64 %newval, 32
; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32
-; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8*
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]])
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], ptr %ptr)
; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]]
@@ -414,18 +410,18 @@ define i64 @test_cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %desired, i64 %n
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
; CHECK: ret i64 [[LOADED_EXIT]]
- %pairold = cmpxchg i64* %ptr, i64 %desired, i64 %newval monotonic monotonic
+ %pairold = cmpxchg ptr %ptr, i64 %desired, i64 %newval monotonic monotonic
%old = extractvalue { i64, i1 } %pairold, 0
ret i64 %old
}
-define i32 @test_cmpxchg_minsize(i32* %addr, i32 %desired, i32 %new) minsize {
+define i32 @test_cmpxchg_minsize(ptr %addr, i32 %desired, i32 %new) minsize {
; CHECK-LABEL: @test_cmpxchg_minsize
; CHECK: call void @llvm.arm.dmb(i32 11)
; CHECK: br label %[[START:.*]]
; CHECK: [[START]]:
-; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr)
+; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %addr)
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
@@ -434,7 +430,7 @@ define i32 @test_cmpxchg_minsize(i32* %addr, i32 %desired, i32 %new) minsize {
; CHECK: [[TRY_STORE]]:
; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LOADED]], %[[FENCED_STORE]] ]
-; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* elementtype(i32) %addr)
+; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0(i32 %new, ptr elementtype(i32) %addr)
; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0
; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[START]]
@@ -457,7 +453,7 @@ define i32 @test_cmpxchg_minsize(i32* %addr, i32 %desired, i32 %new) minsize {
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
; CHECK: ret i32 [[LOADED_EXIT]]
- %pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst
+ %pair = cmpxchg ptr %addr, i32 %desired, i32 %new seq_cst seq_cst
%oldval = extractvalue { i32, i1 } %pair, 0
ret i32 %oldval
}
diff --git a/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v8.ll b/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v8.ll
index cce8799ad1198..bad28b2b6824e 100644
--- a/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v8.ll
+++ b/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v8.ll
@@ -1,66 +1,65 @@
; RUN: opt -S -o - -mtriple=armv8-linux-gnueabihf -atomic-expand %s -codegen-opt-level=1 | FileCheck %s
-define i8 @test_atomic_xchg_i8(i8* %ptr, i8 %xchgend) {
+define i8 @test_atomic_xchg_i8(ptr %ptr, i8 %xchgend) {
; CHECK-LABEL: @test_atomic_xchg_i8
; CHECK-NOT: fence
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr)
+; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
; CHECK: [[NEWVAL32:%.*]] = zext i8 %xchgend to i32
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]:
; CHECK-NOT: fence
; CHECK: ret i8 [[OLDVAL]]
- %res = atomicrmw xchg i8* %ptr, i8 %xchgend monotonic
+ %res = atomicrmw xchg ptr %ptr, i8 %xchgend monotonic
ret i8 %res
}
-define i16 @test_atomic_add_i16(i16* %ptr, i16 %addend) {
+define i16 @test_atomic_add_i16(ptr %ptr, i16 %addend) {
; CHECK-LABEL: @test_atomic_add_i16
; CHECK-NOT: fence
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0i16(i16* elementtype(i16) %ptr)
+; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i16) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16
; CHECK: [[NEWVAL:%.*]] = add i16 [[OLDVAL]], %addend
; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i16(i32 [[NEWVAL32]], i16* elementtype(i16) %ptr)
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0(i32 [[NEWVAL32]], ptr elementtype(i16) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]:
; CHECK-NOT: fence
; CHECK: ret i16 [[OLDVAL]]
- %res = atomicrmw add i16* %ptr, i16 %addend seq_cst
+ %res = atomicrmw add ptr %ptr, i16 %addend seq_cst
ret i16 %res
}
-define i32 @test_atomic_sub_i32(i32* %ptr, i32 %subend) {
+define i32 @test_atomic_sub_i32(ptr %ptr, i32 %subend) {
; CHECK-LABEL: @test_atomic_sub_i32
; CHECK-NOT: fence
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldaex.p0i32(i32* elementtype(i32) %ptr)
+; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %ptr)
; CHECK: [[NEWVAL:%.*]] = sub i32 [[OLDVAL]], %subend
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 [[NEWVAL]], i32* elementtype(i32) %ptr)
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL]], ptr elementtype(i32) %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]:
; CHECK-NOT: fence
; CHECK: ret i32 [[OLDVAL]]
- %res = atomicrmw sub i32* %ptr, i32 %subend acquire
+ %res = atomicrmw sub ptr %ptr, i32 %subend acquire
ret i32 %res
}
-define i64 @test_atomic_or_i64(i64* %ptr, i64 %orend) {
+define i64 @test_atomic_or_i64(ptr %ptr, i64 %orend) {
; CHECK-LABEL: @test_atomic_or_i64
; CHECK-NOT: fence
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8*
-; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldaexd(i8* [[PTR8]])
+; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldaexd(ptr %ptr)
; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0
; CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1
; CHECK: [[LO64:%.*]] = zext i32 [[LO]] to i64
@@ -71,24 +70,23 @@ define i64 @test_atomic_or_i64(i64* %ptr, i64 %orend) {
; CHECK: [[NEWLO:%.*]] = trunc i64 [[NEWVAL]] to i32
; CHECK: [[NEWHI_TMP:%.*]] = lshr i64 [[NEWVAL]], 32
; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32
-; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8*
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]])
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlexd(i32 [[NEWLO]], i32 [[NEWHI]], ptr %ptr)
; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]]
; CHECK: [[END]]:
; CHECK-NOT: fence
; CHECK: ret i64 [[OLDVAL]]
- %res = atomicrmw or i64* %ptr, i64 %orend seq_cst
+ %res = atomicrmw or ptr %ptr, i64 %orend seq_cst
ret i64 %res
}
-define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) {
+define i8 @test_cmpxchg_i8_seqcst_seqcst(ptr %ptr, i8 %desired, i8 %newval) {
; CHECK-LABEL: @test_cmpxchg_i8_seqcst_seqcst
; CHECK-NOT: fence
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0i8(i8* elementtype(i8) %ptr)
+; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i8) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i8
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i8 [[OLDVAL]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
@@ -99,7 +97,7 @@ define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) {
; CHECK: [[TRY_STORE]]:
; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i8 [ [[OLDVAL]], %[[FENCED_STORE]] ]
; CHECK: [[NEWVAL32:%.*]] = zext i8 %newval to i32
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr)
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr)
; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]]
@@ -122,18 +120,18 @@ define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) {
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
; CHECK: ret i8 [[LOADED_EXIT]]
- %pairold = cmpxchg i8* %ptr, i8 %desired, i8 %newval seq_cst seq_cst
+ %pairold = cmpxchg ptr %ptr, i8 %desired, i8 %newval seq_cst seq_cst
%old = extractvalue { i8, i1 } %pairold, 0
ret i8 %old
}
-define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newval) {
+define i16 @test_cmpxchg_i16_seqcst_monotonic(ptr %ptr, i16 %desired, i16 %newval) {
; CHECK-LABEL: @test_cmpxchg_i16_seqcst_monotonic
; CHECK-NOT: fence
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0i16(i16* elementtype(i16) %ptr)
+; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i16) %ptr)
; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i16
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i16 [[OLDVAL]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
@@ -144,7 +142,7 @@ define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newv
; CHECK: [[TRY_STORE]]:
; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i16 [ [[OLDVAL]], %[[FENCED_STORE]] ]
; CHECK: [[NEWVAL32:%.*]] = zext i16 %newval to i32
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i16(i32 [[NEWVAL32]], i16* elementtype(i16) %ptr)
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0(i32 [[NEWVAL32]], ptr elementtype(i16) %ptr)
; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]]
@@ -168,18 +166,18 @@ define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newv
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
; CHECK: ret i16 [[LOADED_EXIT]]
- %pairold = cmpxchg i16* %ptr, i16 %desired, i16 %newval seq_cst monotonic
+ %pairold = cmpxchg ptr %ptr, i16 %desired, i16 %newval seq_cst monotonic
%old = extractvalue { i16, i1 } %pairold, 0
ret i16 %old
}
-define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newval) {
+define i32 @test_cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %desired, i32 %newval) {
; CHECK-LABEL: @test_cmpxchg_i32_acquire_acquire
; CHECK-NOT: fence
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldaex.p0i32(i32* elementtype(i32) %ptr)
+; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %ptr)
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[OLDVAL]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
@@ -188,7 +186,7 @@ define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newva
; CHECK: [[TRY_STORE]]:
; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[OLDVAL]], %[[FENCED_STORE]] ]
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %newval, i32* elementtype(i32) %ptr)
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 %newval, ptr elementtype(i32) %ptr)
; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]]
@@ -211,19 +209,18 @@ define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newva
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
; CHECK: ret i32 [[LOADED_EXIT]]
- %pairold = cmpxchg i32* %ptr, i32 %desired, i32 %newval acquire acquire
+ %pairold = cmpxchg ptr %ptr, i32 %desired, i32 %newval acquire acquire
%old = extractvalue { i32, i1 } %pairold, 0
ret i32 %old
}
-define i64 @test_cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %desired, i64 %newval) {
+define i64 @test_cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %desired, i64 %newval) {
; CHECK-LABEL: @test_cmpxchg_i64_monotonic_monotonic
; CHECK-NOT: fence
; CHECK: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8*
-; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]])
+; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(ptr %ptr)
; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0
; CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1
; CHECK: [[LO64:%.*]] = zext i32 [[LO]] to i64
@@ -241,8 +238,7 @@ define i64 @test_cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %desired, i64 %n
; CHECK: [[NEWLO:%.*]] = trunc i64 %newval to i32
; CHECK: [[NEWHI_TMP:%.*]] = lshr i64 %newval, 32
; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32
-; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8*
-; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]])
+; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], ptr %ptr)
; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0
; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]]
@@ -265,7 +261,7 @@ define i64 @test_cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %desired, i64 %n
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
; CHECK: ret i64 [[LOADED_EXIT]]
- %pairold = cmpxchg i64* %ptr, i64 %desired, i64 %newval monotonic monotonic
+ %pairold = cmpxchg ptr %ptr, i64 %desired, i64 %newval monotonic monotonic
%old = extractvalue { i64, i1 } %pairold, 0
ret i64 %old
}
diff --git a/llvm/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll b/llvm/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll
index 6f8ffc1cba21f..d0268bf3e0079 100644
--- a/llvm/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll
+++ b/llvm/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll
@@ -1,18 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -mtriple=armv7-apple-ios7.0 -atomic-expand %s | FileCheck %s
-define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
+define float @test_atomicrmw_fadd_f32(ptr %ptr, float %value) {
; CHECK-LABEL: @test_atomicrmw_fadd_f32(
; CHECK-NEXT: call void @llvm.arm.dmb(i32 11)
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -21,22 +20,21 @@ define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
; CHECK-NEXT: call void @llvm.arm.dmb(i32 11)
; CHECK-NEXT: ret float [[TMP6]]
;
- %res = atomicrmw fadd float* %ptr, float %value seq_cst
+ %res = atomicrmw fadd ptr %ptr, float %value seq_cst
ret float %res
}
-define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
+define float @test_atomicrmw_fsub_f32(ptr %ptr, float %value) {
; CHECK-LABEL: @test_atomicrmw_fsub_f32(
; CHECK-NEXT: call void @llvm.arm.dmb(i32 11)
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -45,7 +43,7 @@ define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
; CHECK-NEXT: call void @llvm.arm.dmb(i32 11)
; CHECK-NEXT: ret float [[TMP6]]
;
- %res = atomicrmw fsub float* %ptr, float %value seq_cst
+ %res = atomicrmw fsub ptr %ptr, float %value seq_cst
ret float %res
}
diff --git a/llvm/test/Transforms/AtomicExpand/ARM/cmpxchg-weak.ll b/llvm/test/Transforms/AtomicExpand/ARM/cmpxchg-weak.ll
index 1b90ac999dcdb..f7a210d631bf9 100644
--- a/llvm/test/Transforms/AtomicExpand/ARM/cmpxchg-weak.ll
+++ b/llvm/test/Transforms/AtomicExpand/ARM/cmpxchg-weak.ll
@@ -1,12 +1,12 @@
; RUN: opt -atomic-expand -codegen-opt-level=1 -S -mtriple=thumbv7s-apple-ios7.0 %s | FileCheck %s
-define i32 @test_cmpxchg_seq_cst(i32* %addr, i32 %desired, i32 %new) {
+define i32 @test_cmpxchg_seq_cst(ptr %addr, i32 %desired, i32 %new) {
; CHECK-LABEL: @test_cmpxchg_seq_cst
; Intrinsic for "dmb ishst" is then expected
; CHECK: br label %[[START:.*]]
; CHECK: [[START]]:
-; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr)
+; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %addr)
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
@@ -16,7 +16,7 @@ define i32 @test_cmpxchg_seq_cst(i32* %addr, i32 %desired, i32 %new) {
; CHECK: [[TRY_STORE]]:
; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LOADED]], %[[FENCED_STORE]] ]
-; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* elementtype(i32) %addr)
+; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0(i32 %new, ptr elementtype(i32) %addr)
; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0
; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]]
@@ -39,17 +39,17 @@ define i32 @test_cmpxchg_seq_cst(i32* %addr, i32 %desired, i32 %new) {
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
; CHECK: ret i32 [[LOADED_EXIT]]
- %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst seq_cst
+ %pair = cmpxchg weak ptr %addr, i32 %desired, i32 %new seq_cst seq_cst
%oldval = extractvalue { i32, i1 } %pair, 0
ret i32 %oldval
}
-define i1 @test_cmpxchg_weak_fail(i32* %addr, i32 %desired, i32 %new) {
+define i1 @test_cmpxchg_weak_fail(ptr %addr, i32 %desired, i32 %new) {
; CHECK-LABEL: @test_cmpxchg_weak_fail
; CHECK: br label %[[START:.*]]
; CHECK: [[START]]:
-; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr)
+; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %addr)
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
@@ -58,7 +58,7 @@ define i1 @test_cmpxchg_weak_fail(i32* %addr, i32 %desired, i32 %new) {
; CHECK: br label %[[TRY_STORE:.*]]
; CHECK: [[TRY_STORE]]:
-; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* elementtype(i32) %addr)
+; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0(i32 %new, ptr elementtype(i32) %addr)
; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0
; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]]
@@ -78,18 +78,18 @@ define i1 @test_cmpxchg_weak_fail(i32* %addr, i32 %desired, i32 %new) {
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
; CHECK: ret i1 [[SUCCESS]]
- %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic
+ %pair = cmpxchg weak ptr %addr, i32 %desired, i32 %new seq_cst monotonic
%oldval = extractvalue { i32, i1 } %pair, 1
ret i1 %oldval
}
-define i32 @test_cmpxchg_monotonic(i32* %addr, i32 %desired, i32 %new) {
+define i32 @test_cmpxchg_monotonic(ptr %addr, i32 %desired, i32 %new) {
; CHECK-LABEL: @test_cmpxchg_monotonic
; CHECK-NOT: dmb
; CHECK: br label %[[START:.*]]
; CHECK: [[START]]:
-; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr)
+; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %addr)
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
@@ -98,7 +98,7 @@ define i32 @test_cmpxchg_monotonic(i32* %addr, i32 %desired, i32 %new) {
; CHECK: [[TRY_STORE]]:
; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LOADED]], %[[FENCED_STORE]] ]
-; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* elementtype(i32) %addr)
+; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0(i32 %new, ptr elementtype(i32) %addr)
; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0
; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]]
@@ -121,17 +121,17 @@ define i32 @test_cmpxchg_monotonic(i32* %addr, i32 %desired, i32 %new) {
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
; CHECK: ret i32 [[LOADED_EXIT]]
- %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new monotonic monotonic
+ %pair = cmpxchg weak ptr %addr, i32 %desired, i32 %new monotonic monotonic
%oldval = extractvalue { i32, i1 } %pair, 0
ret i32 %oldval
}
-define i32 @test_cmpxchg_seq_cst_minsize(i32* %addr, i32 %desired, i32 %new) minsize {
+define i32 @test_cmpxchg_seq_cst_minsize(ptr %addr, i32 %desired, i32 %new) minsize {
; CHECK-LABEL: @test_cmpxchg_seq_cst_minsize
; CHECK: br label %[[START:.*]]
; CHECK: [[START]]:
-; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr)
+; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %addr)
; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired
; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]]
@@ -141,7 +141,7 @@ define i32 @test_cmpxchg_seq_cst_minsize(i32* %addr, i32 %desired, i32 %new) min
; CHECK: [[TRY_STORE]]:
; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LOADED]], %[[FENCED_STORE]] ]
-; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* elementtype(i32) %addr)
+; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0(i32 %new, ptr elementtype(i32) %addr)
; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0
; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]]
@@ -164,7 +164,7 @@ define i32 @test_cmpxchg_seq_cst_minsize(i32* %addr, i32 %desired, i32 %new) min
; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ]
; CHECK: ret i32 [[LOADED_EXIT]]
- %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst seq_cst
+ %pair = cmpxchg weak ptr %addr, i32 %desired, i32 %new seq_cst seq_cst
%oldval = extractvalue { i32, i1 } %pair, 0
ret i32 %oldval
}
diff --git a/llvm/test/Transforms/AtomicExpand/Hexagon/atomicrmw-fp.ll b/llvm/test/Transforms/AtomicExpand/Hexagon/atomicrmw-fp.ll
index 7a2954ee213c7..8827eb5d8e108 100644
--- a/llvm/test/Transforms/AtomicExpand/Hexagon/atomicrmw-fp.ll
+++ b/llvm/test/Transforms/AtomicExpand/Hexagon/atomicrmw-fp.ll
@@ -1,45 +1,41 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -mtriple=hexagon-- -atomic-expand %s | FileCheck %s
-define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
+define float @test_atomicrmw_fadd_f32(ptr %ptr, float %value) {
; CHECK-LABEL: @test_atomicrmw_fadd_f32(
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[PTR:%.*]] to i32*
-; CHECK-NEXT: [[LARX:%.*]] = call i32 @llvm.hexagon.L2.loadw.locked(i32* [[TMP1]])
+; CHECK-NEXT: [[LARX:%.*]] = call i32 @llvm.hexagon.L2.loadw.locked(ptr [[PTR:%.*]])
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[LARX]] to float
; CHECK-NEXT: [[NEW:%.*]] = fadd float [[TMP2]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast float* [[PTR]] to i32*
; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[NEW]] to i32
-; CHECK-NEXT: [[STCX:%.*]] = call i32 @llvm.hexagon.S2.storew.locked(i32* [[TMP3]], i32 [[TMP4]])
+; CHECK-NEXT: [[STCX:%.*]] = call i32 @llvm.hexagon.S2.storew.locked(ptr [[PTR]], i32 [[TMP4]])
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[STCX]], 0
; CHECK-NEXT: [[TMP6:%.*]] = zext i1 [[TMP5]] to i32
; CHECK-NEXT: br i1 [[TMP5]], label [[ATOMICRMW_START]], label [[ATOMICRMW_END:%.*]]
; CHECK: atomicrmw.end:
; CHECK-NEXT: ret float [[TMP2]]
;
- %res = atomicrmw fadd float* %ptr, float %value seq_cst
+ %res = atomicrmw fadd ptr %ptr, float %value seq_cst
ret float %res
}
-define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
+define float @test_atomicrmw_fsub_f32(ptr %ptr, float %value) {
; CHECK-LABEL: @test_atomicrmw_fsub_f32(
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[PTR:%.*]] to i32*
-; CHECK-NEXT: [[LARX:%.*]] = call i32 @llvm.hexagon.L2.loadw.locked(i32* [[TMP1]])
+; CHECK-NEXT: [[LARX:%.*]] = call i32 @llvm.hexagon.L2.loadw.locked(ptr [[PTR:%.*]])
; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[LARX]] to float
; CHECK-NEXT: [[NEW:%.*]] = fsub float [[TMP2]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast float* [[PTR]] to i32*
; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[NEW]] to i32
-; CHECK-NEXT: [[STCX:%.*]] = call i32 @llvm.hexagon.S2.storew.locked(i32* [[TMP3]], i32 [[TMP4]])
+; CHECK-NEXT: [[STCX:%.*]] = call i32 @llvm.hexagon.S2.storew.locked(ptr [[PTR]], i32 [[TMP4]])
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[STCX]], 0
; CHECK-NEXT: [[TMP6:%.*]] = zext i1 [[TMP5]] to i32
; CHECK-NEXT: br i1 [[TMP5]], label [[ATOMICRMW_START]], label [[ATOMICRMW_END:%.*]]
; CHECK: atomicrmw.end:
; CHECK-NEXT: ret float [[TMP2]]
;
- %res = atomicrmw fsub float* %ptr, float %value seq_cst
+ %res = atomicrmw fsub ptr %ptr, float %value seq_cst
ret float %res
}
diff --git a/llvm/test/Transforms/AtomicExpand/Mips/atomicrmw-fp.ll b/llvm/test/Transforms/AtomicExpand/Mips/atomicrmw-fp.ll
index 7931b2bb7f3d6..2c90a70bd0ad0 100644
--- a/llvm/test/Transforms/AtomicExpand/Mips/atomicrmw-fp.ll
+++ b/llvm/test/Transforms/AtomicExpand/Mips/atomicrmw-fp.ll
@@ -1,18 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -mtriple=mips64-mti-linux-gnu -atomic-expand %s | FileCheck %s
-define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
+define float @test_atomicrmw_fadd_f32(ptr %ptr, float %value) {
; CHECK-LABEL: @test_atomicrmw_fadd_f32(
; CHECK-NEXT: fence seq_cst
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -21,22 +20,21 @@ define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
; CHECK-NEXT: fence seq_cst
; CHECK-NEXT: ret float [[TMP6]]
;
- %res = atomicrmw fadd float* %ptr, float %value seq_cst
+ %res = atomicrmw fadd ptr %ptr, float %value seq_cst
ret float %res
}
-define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
+define float @test_atomicrmw_fsub_f32(ptr %ptr, float %value) {
; CHECK-LABEL: @test_atomicrmw_fsub_f32(
; CHECK-NEXT: fence seq_cst
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -45,7 +43,7 @@ define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
; CHECK-NEXT: fence seq_cst
; CHECK-NEXT: ret float [[TMP6]]
;
- %res = atomicrmw fsub float* %ptr, float %value seq_cst
+ %res = atomicrmw fsub ptr %ptr, float %value seq_cst
ret float %res
}
diff --git a/llvm/test/Transforms/AtomicExpand/PowerPC/atomicrmw-fp.ll b/llvm/test/Transforms/AtomicExpand/PowerPC/atomicrmw-fp.ll
index d0c00d6313400..7e42735feabff 100644
--- a/llvm/test/Transforms/AtomicExpand/PowerPC/atomicrmw-fp.ll
+++ b/llvm/test/Transforms/AtomicExpand/PowerPC/atomicrmw-fp.ll
@@ -1,18 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -mtriple=powerpc64-unknown-unknown -atomic-expand %s | FileCheck %s
-define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
+define float @test_atomicrmw_fadd_f32(ptr %ptr, float %value) {
; CHECK-LABEL: @test_atomicrmw_fadd_f32(
; CHECK-NEXT: call void @llvm.ppc.sync()
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic, align 4
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -21,22 +20,21 @@ define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
; CHECK-NEXT: call void @llvm.ppc.lwsync()
; CHECK-NEXT: ret float [[TMP6]]
;
- %res = atomicrmw fadd float* %ptr, float %value seq_cst
+ %res = atomicrmw fadd ptr %ptr, float %value seq_cst
ret float %res
}
-define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
+define float @test_atomicrmw_fsub_f32(ptr %ptr, float %value) {
; CHECK-LABEL: @test_atomicrmw_fsub_f32(
; CHECK-NEXT: call void @llvm.ppc.sync()
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic, align 4
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -45,7 +43,7 @@ define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
; CHECK-NEXT: call void @llvm.ppc.lwsync()
; CHECK-NEXT: ret float [[TMP6]]
;
- %res = atomicrmw fsub float* %ptr, float %value seq_cst
+ %res = atomicrmw fsub ptr %ptr, float %value seq_cst
ret float %res
}
diff --git a/llvm/test/Transforms/AtomicExpand/PowerPC/cfence-double.ll b/llvm/test/Transforms/AtomicExpand/PowerPC/cfence-double.ll
index 92b75d0006f24..087665341e626 100644
--- a/llvm/test/Transforms/AtomicExpand/PowerPC/cfence-double.ll
+++ b/llvm/test/Transforms/AtomicExpand/PowerPC/cfence-double.ll
@@ -4,7 +4,7 @@
; RUN: opt -S -atomic-expand -mtriple=powerpc64-unknown-unknown \
; RUN: -opaque-pointers < %s 2>&1 | FileCheck %s
-define double @foo(double* %dp) {
+define double @foo(ptr %dp) {
; CHECK-LABEL: @foo(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, ptr [[DP:%.*]] monotonic, align 8
@@ -13,6 +13,6 @@ define double @foo(double* %dp) {
; CHECK-NEXT: ret double [[TMP1]]
;
entry:
- %0 = load atomic double, double* %dp acquire, align 8
+ %0 = load atomic double, ptr %dp acquire, align 8
ret double %0
}
diff --git a/llvm/test/Transforms/AtomicExpand/PowerPC/cfence-float.ll b/llvm/test/Transforms/AtomicExpand/PowerPC/cfence-float.ll
index dfbaef9c8e1bf..e3ea212b41d60 100644
--- a/llvm/test/Transforms/AtomicExpand/PowerPC/cfence-float.ll
+++ b/llvm/test/Transforms/AtomicExpand/PowerPC/cfence-float.ll
@@ -4,7 +4,7 @@
; RUN: opt -S -atomic-expand -mtriple=powerpc64-unknown-unknown \
; RUN: -opaque-pointers < %s 2>&1 | FileCheck %s
-define float @bar(float* %fp) {
+define float @bar(ptr %fp) {
; CHECK-LABEL: @bar(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, ptr [[FP:%.*]] monotonic, align 4
@@ -13,6 +13,6 @@ define float @bar(float* %fp) {
; CHECK-NEXT: ret float [[TMP1]]
;
entry:
- %0 = load atomic float, float* %fp acquire, align 4
+ %0 = load atomic float, ptr %fp acquire, align 4
ret float %0
}
diff --git a/llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll b/llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll
index eba004f730791..3ffa546063cba 100644
--- a/llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll
+++ b/llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll
@@ -4,7 +4,7 @@
; RUN: opt -atomic-expand -S -mtriple=powerpc64-unknown-unknown \
; RUN: -mcpu=pwr7 %s | FileCheck --check-prefix=PWR7 %s
-define i1 @test_cmpxchg_seq_cst(i128* %addr, i128 %desire, i128 %new) {
+define i1 @test_cmpxchg_seq_cst(ptr %addr, i128 %desire, i128 %new) {
; CHECK-LABEL: @test_cmpxchg_seq_cst(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP_LO:%.*]] = trunc i128 [[DESIRE:%.*]] to i64
@@ -13,9 +13,8 @@ define i1 @test_cmpxchg_seq_cst(i128* %addr, i128 %desire, i128 %new) {
; CHECK-NEXT: [[NEW_LO:%.*]] = trunc i128 [[NEW:%.*]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = lshr i128 [[NEW]], 64
; CHECK-NEXT: [[NEW_HI:%.*]] = trunc i128 [[TMP1]] to i64
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast i128* [[ADDR:%.*]] to i8*
; CHECK-NEXT: call void @llvm.ppc.sync()
-; CHECK-NEXT: [[TMP3:%.*]] = call { i64, i64 } @llvm.ppc.cmpxchg.i128(i8* [[TMP2]], i64 [[CMP_LO]], i64 [[CMP_HI]], i64 [[NEW_LO]], i64 [[NEW_HI]])
+; CHECK-NEXT: [[TMP3:%.*]] = call { i64, i64 } @llvm.ppc.cmpxchg.i128(ptr [[ADDR:%.*]], i64 [[CMP_LO]], i64 [[CMP_HI]], i64 [[NEW_LO]], i64 [[NEW_HI]])
; CHECK-NEXT: call void @llvm.ppc.lwsync()
; CHECK-NEXT: [[LO:%.*]] = extractvalue { i64, i64 } [[TMP3]], 0
; CHECK-NEXT: [[HI:%.*]] = extractvalue { i64, i64 } [[TMP3]], 1
@@ -31,26 +30,23 @@ define i1 @test_cmpxchg_seq_cst(i128* %addr, i128 %desire, i128 %new) {
;
; PWR7-LABEL: @test_cmpxchg_seq_cst(
; PWR7-NEXT: entry:
-; PWR7-NEXT: [[TMP0:%.*]] = bitcast i128* [[ADDR:%.*]] to i8*
; PWR7-NEXT: [[TMP1:%.*]] = alloca i128, align 8
-; PWR7-NEXT: [[TMP2:%.*]] = bitcast i128* [[TMP1]] to i8*
-; PWR7-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP2]])
-; PWR7-NEXT: store i128 [[DESIRE:%.*]], i128* [[TMP1]], align 8
+; PWR7-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr [[TMP1]])
+; PWR7-NEXT: store i128 [[DESIRE:%.*]], ptr [[TMP1]], align 8
; PWR7-NEXT: [[TMP3:%.*]] = alloca i128, align 8
-; PWR7-NEXT: [[TMP4:%.*]] = bitcast i128* [[TMP3]] to i8*
-; PWR7-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP4]])
-; PWR7-NEXT: store i128 [[NEW:%.*]], i128* [[TMP3]], align 8
-; PWR7-NEXT: [[TMP5:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 16, i8* [[TMP0]], i8* [[TMP2]], i8* [[TMP4]], i32 5, i32 5)
-; PWR7-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP4]])
-; PWR7-NEXT: [[TMP6:%.*]] = load i128, i128* [[TMP1]], align 8
-; PWR7-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP2]])
+; PWR7-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr [[TMP3]])
+; PWR7-NEXT: store i128 [[NEW:%.*]], ptr [[TMP3]], align 8
+; PWR7-NEXT: [[TMP5:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 16, ptr [[ADDR:%.*]], ptr [[TMP1]], ptr [[TMP3]], i32 5, i32 5)
+; PWR7-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[TMP3]])
+; PWR7-NEXT: [[TMP6:%.*]] = load i128, ptr [[TMP1]], align 8
+; PWR7-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[TMP1]])
; PWR7-NEXT: [[TMP7:%.*]] = insertvalue { i128, i1 } poison, i128 [[TMP6]], 0
; PWR7-NEXT: [[TMP8:%.*]] = insertvalue { i128, i1 } [[TMP7]], i1 [[TMP5]], 1
; PWR7-NEXT: [[SUCC:%.*]] = extractvalue { i128, i1 } [[TMP8]], 1
; PWR7-NEXT: ret i1 [[SUCC]]
;
entry:
- %pair = cmpxchg weak i128* %addr, i128 %desire, i128 %new seq_cst seq_cst
+ %pair = cmpxchg weak ptr %addr, i128 %desire, i128 %new seq_cst seq_cst
%succ = extractvalue {i128, i1} %pair, 1
ret i1 %succ
}
diff --git a/llvm/test/Transforms/AtomicExpand/PowerPC/issue55983.ll b/llvm/test/Transforms/AtomicExpand/PowerPC/issue55983.ll
index 707f859287e5c..a3aa456ec8bce 100644
--- a/llvm/test/Transforms/AtomicExpand/PowerPC/issue55983.ll
+++ b/llvm/test/Transforms/AtomicExpand/PowerPC/issue55983.ll
@@ -16,7 +16,7 @@ entry:
ret ptr %0
}
-define void @foobar({} addrspace(10)* addrspace(11)* %p) {
+define void @foobar(ptr addrspace(11) %p) {
; CHECK-LABEL: @foobar(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load atomic ptr addrspace(10), ptr addrspace(11) [[P:%.*]] monotonic, align 8
@@ -24,6 +24,6 @@ define void @foobar({} addrspace(10)* addrspace(11)* %p) {
; CHECK-NEXT: unreachable
;
entry:
- %0 = load atomic {} addrspace(10)*, {} addrspace(10)* addrspace(11)* %p acquire, align 8
+ %0 = load atomic ptr addrspace(10), ptr addrspace(11) %p acquire, align 8
unreachable
}
diff --git a/llvm/test/Transforms/AtomicExpand/RISCV/atomicrmw-fp.ll b/llvm/test/Transforms/AtomicExpand/RISCV/atomicrmw-fp.ll
index f3c4abbc253c1..ceaafd89990b0 100644
--- a/llvm/test/Transforms/AtomicExpand/RISCV/atomicrmw-fp.ll
+++ b/llvm/test/Transforms/AtomicExpand/RISCV/atomicrmw-fp.ll
@@ -1,22 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -mtriple=riscv32-- -atomic-expand %s | FileCheck %s
-define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
+define float @test_atomicrmw_fadd_f32(ptr %ptr, float %value) {
; CHECK-LABEL: @test_atomicrmw_fadd_f32(
; CHECK-NEXT: [[TMP1:%.*]] = alloca float, align 4
-; CHECK-NEXT: [[TMP2:%.*]] = load float, float* [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast float* [[PTR]] to i8*
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast float* [[TMP1]] to i8*
-; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]])
-; CHECK-NEXT: store float [[LOADED]], float* [[TMP1]], align 4
+; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]])
+; CHECK-NEXT: store float [[LOADED]], ptr [[TMP1]], align 4
; CHECK-NEXT: [[TMP5:%.*]] = bitcast float [[NEW]] to i32
-; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(i8* [[TMP3]], i8* [[TMP4]], i32 [[TMP5]], i32 5, i32 5)
-; CHECK-NEXT: [[TMP7:%.*]] = load float, float* [[TMP1]], align 4
-; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP4]])
+; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[PTR]], ptr [[TMP1]], i32 [[TMP5]], i32 5, i32 5)
+; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[TMP1]], align 4
+; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]])
; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { float, i1 } poison, float [[TMP7]], 0
; CHECK-NEXT: [[TMP9:%.*]] = insertvalue { float, i1 } [[TMP8]], i1 [[TMP6]], 1
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { float, i1 } [[TMP9]], 1
@@ -25,26 +23,24 @@ define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
; CHECK: atomicrmw.end:
; CHECK-NEXT: ret float [[NEWLOADED]]
;
- %res = atomicrmw fadd float* %ptr, float %value seq_cst
+ %res = atomicrmw fadd ptr %ptr, float %value seq_cst
ret float %res
}
-define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
+define float @test_atomicrmw_fsub_f32(ptr %ptr, float %value) {
; CHECK-LABEL: @test_atomicrmw_fsub_f32(
; CHECK-NEXT: [[TMP1:%.*]] = alloca float, align 4
-; CHECK-NEXT: [[TMP2:%.*]] = load float, float* [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast float* [[PTR]] to i8*
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast float* [[TMP1]] to i8*
-; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]])
-; CHECK-NEXT: store float [[LOADED]], float* [[TMP1]], align 4
+; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]])
+; CHECK-NEXT: store float [[LOADED]], ptr [[TMP1]], align 4
; CHECK-NEXT: [[TMP5:%.*]] = bitcast float [[NEW]] to i32
-; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(i8* [[TMP3]], i8* [[TMP4]], i32 [[TMP5]], i32 5, i32 5)
-; CHECK-NEXT: [[TMP7:%.*]] = load float, float* [[TMP1]], align 4
-; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP4]])
+; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[PTR]], ptr [[TMP1]], i32 [[TMP5]], i32 5, i32 5)
+; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[TMP1]], align 4
+; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]])
; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { float, i1 } poison, float [[TMP7]], 0
; CHECK-NEXT: [[TMP9:%.*]] = insertvalue { float, i1 } [[TMP8]], i1 [[TMP6]], 1
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { float, i1 } [[TMP9]], 1
@@ -53,7 +49,7 @@ define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
; CHECK: atomicrmw.end:
; CHECK-NEXT: ret float [[NEWLOADED]]
;
- %res = atomicrmw fsub float* %ptr, float %value seq_cst
+ %res = atomicrmw fsub ptr %ptr, float %value seq_cst
ret float %res
}
diff --git a/llvm/test/Transforms/AtomicExpand/SPARC/libcalls.ll b/llvm/test/Transforms/AtomicExpand/SPARC/libcalls.ll
index 4a1e3c2b671ae..4427c5e7ed23d 100644
--- a/llvm/test/Transforms/AtomicExpand/SPARC/libcalls.ll
+++ b/llvm/test/Transforms/AtomicExpand/SPARC/libcalls.ll
@@ -13,57 +13,51 @@ target triple = "sparc-unknown-unknown"
;; straightforward.
; CHECK-LABEL: @test_load_i16(
-; CHECK: %1 = bitcast i16* %arg to i8*
-; CHECK: %2 = call i16 @__atomic_load_2(i8* %1, i32 5)
-; CHECK: ret i16 %2
-define i16 @test_load_i16(i16* %arg) {
- %ret = load atomic i16, i16* %arg seq_cst, align 4
+; CHECK: %1 = call i16 @__atomic_load_2(ptr %arg, i32 5)
+; CHECK: ret i16 %1
+define i16 @test_load_i16(ptr %arg) {
+ %ret = load atomic i16, ptr %arg seq_cst, align 4
ret i16 %ret
}
; CHECK-LABEL: @test_store_i16(
-; CHECK: %1 = bitcast i16* %arg to i8*
-; CHECK: call void @__atomic_store_2(i8* %1, i16 %val, i32 5)
+; CHECK: call void @__atomic_store_2(ptr %arg, i16 %val, i32 5)
; CHECK: ret void
-define void @test_store_i16(i16* %arg, i16 %val) {
- store atomic i16 %val, i16* %arg seq_cst, align 4
+define void @test_store_i16(ptr %arg, i16 %val) {
+ store atomic i16 %val, ptr %arg seq_cst, align 4
ret void
}
; CHECK-LABEL: @test_exchange_i16(
-; CHECK: %1 = bitcast i16* %arg to i8*
-; CHECK: %2 = call i16 @__atomic_exchange_2(i8* %1, i16 %val, i32 5)
-; CHECK: ret i16 %2
-define i16 @test_exchange_i16(i16* %arg, i16 %val) {
- %ret = atomicrmw xchg i16* %arg, i16 %val seq_cst
+; CHECK: %1 = call i16 @__atomic_exchange_2(ptr %arg, i16 %val, i32 5)
+; CHECK: ret i16 %1
+define i16 @test_exchange_i16(ptr %arg, i16 %val) {
+ %ret = atomicrmw xchg ptr %arg, i16 %val seq_cst
ret i16 %ret
}
; CHECK-LABEL: @test_cmpxchg_i16(
-; CHECK: %1 = bitcast i16* %arg to i8*
-; CHECK: %2 = alloca i16, align 2
-; CHECK: %3 = bitcast i16* %2 to i8*
-; CHECK: call void @llvm.lifetime.start.p0i8(i64 2, i8* %3)
-; CHECK: store i16 %old, i16* %2, align 2
-; CHECK: %4 = call zeroext i1 @__atomic_compare_exchange_2(i8* %1, i8* %3, i16 %new, i32 5, i32 0)
-; CHECK: %5 = load i16, i16* %2, align 2
-; CHECK: call void @llvm.lifetime.end.p0i8(i64 2, i8* %3)
-; CHECK: %6 = insertvalue { i16, i1 } poison, i16 %5, 0
-; CHECK: %7 = insertvalue { i16, i1 } %6, i1 %4, 1
-; CHECK: %ret = extractvalue { i16, i1 } %7, 0
+; CHECK: %1 = alloca i16, align 2
+; CHECK: call void @llvm.lifetime.start.p0(i64 2, ptr %1)
+; CHECK: store i16 %old, ptr %1, align 2
+; CHECK: %2 = call zeroext i1 @__atomic_compare_exchange_2(ptr %arg, ptr %1, i16 %new, i32 5, i32 0)
+; CHECK: %3 = load i16, ptr %1, align 2
+; CHECK: call void @llvm.lifetime.end.p0(i64 2, ptr %1)
+; CHECK: %4 = insertvalue { i16, i1 } poison, i16 %3, 0
+; CHECK: %5 = insertvalue { i16, i1 } %4, i1 %2, 1
+; CHECK: %ret = extractvalue { i16, i1 } %5, 0
; CHECK: ret i16 %ret
-define i16 @test_cmpxchg_i16(i16* %arg, i16 %old, i16 %new) {
- %ret_succ = cmpxchg i16* %arg, i16 %old, i16 %new seq_cst monotonic
+define i16 @test_cmpxchg_i16(ptr %arg, i16 %old, i16 %new) {
+ %ret_succ = cmpxchg ptr %arg, i16 %old, i16 %new seq_cst monotonic
%ret = extractvalue { i16, i1 } %ret_succ, 0
ret i16 %ret
}
; CHECK-LABEL: @test_add_i16(
-; CHECK: %1 = bitcast i16* %arg to i8*
-; CHECK: %2 = call i16 @__atomic_fetch_add_2(i8* %1, i16 %val, i32 5)
-; CHECK: ret i16 %2
-define i16 @test_add_i16(i16* %arg, i16 %val) {
- %ret = atomicrmw add i16* %arg, i16 %val seq_cst
+; CHECK: %1 = call i16 @__atomic_fetch_add_2(ptr %arg, i16 %val, i32 5)
+; CHECK: ret i16 %1
+define i16 @test_add_i16(ptr %arg, i16 %val) {
+ %ret = atomicrmw add ptr %arg, i16 %val seq_cst
ret i16 %ret
}
@@ -73,72 +67,62 @@ define i16 @test_add_i16(i16* %arg, i16 %val) {
;; 32-bit i386.
; CHECK-LABEL: @test_load_i128(
-; CHECK: %1 = bitcast i128* %arg to i8*
-; CHECK: %2 = alloca i128, align 8
-; CHECK: %3 = bitcast i128* %2 to i8*
-; CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* %3)
-; CHECK: call void @__atomic_load(i32 16, i8* %1, i8* %3, i32 5)
-; CHECK: %4 = load i128, i128* %2, align 8
-; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* %3)
-; CHECK: ret i128 %4
-define i128 @test_load_i128(i128* %arg) {
- %ret = load atomic i128, i128* %arg seq_cst, align 16
+; CHECK: %1 = alloca i128, align 8
+; CHECK: call void @llvm.lifetime.start.p0(i64 16, ptr %1)
+; CHECK: call void @__atomic_load(i32 16, ptr %arg, ptr %1, i32 5)
+; CHECK: %2 = load i128, ptr %1, align 8
+; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr %1)
+; CHECK: ret i128 %2
+define i128 @test_load_i128(ptr %arg) {
+ %ret = load atomic i128, ptr %arg seq_cst, align 16
ret i128 %ret
}
; CHECK-LABEL: @test_store_i128(
-; CHECK: %1 = bitcast i128* %arg to i8*
-; CHECK: %2 = alloca i128, align 8
-; CHECK: %3 = bitcast i128* %2 to i8*
-; CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* %3)
-; CHECK: store i128 %val, i128* %2, align 8
-; CHECK: call void @__atomic_store(i32 16, i8* %1, i8* %3, i32 5)
-; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* %3)
+; CHECK: %1 = alloca i128, align 8
+; CHECK: call void @llvm.lifetime.start.p0(i64 16, ptr %1)
+; CHECK: store i128 %val, ptr %1, align 8
+; CHECK: call void @__atomic_store(i32 16, ptr %arg, ptr %1, i32 5)
+; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr %1)
; CHECK: ret void
-define void @test_store_i128(i128* %arg, i128 %val) {
- store atomic i128 %val, i128* %arg seq_cst, align 16
+define void @test_store_i128(ptr %arg, i128 %val) {
+ store atomic i128 %val, ptr %arg seq_cst, align 16
ret void
}
; CHECK-LABEL: @test_exchange_i128(
-; CHECK: %1 = bitcast i128* %arg to i8*
+; CHECK: %1 = alloca i128, align 8
+; CHECK: call void @llvm.lifetime.start.p0(i64 16, ptr %1)
+; CHECK: store i128 %val, ptr %1, align 8
; CHECK: %2 = alloca i128, align 8
-; CHECK: %3 = bitcast i128* %2 to i8*
-; CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* %3)
-; CHECK: store i128 %val, i128* %2, align 8
-; CHECK: %4 = alloca i128, align 8
-; CHECK: %5 = bitcast i128* %4 to i8*
-; CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* %5)
-; CHECK: call void @__atomic_exchange(i32 16, i8* %1, i8* %3, i8* %5, i32 5)
-; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* %3)
-; CHECK: %6 = load i128, i128* %4, align 8
-; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* %5)
-; CHECK: ret i128 %6
-define i128 @test_exchange_i128(i128* %arg, i128 %val) {
- %ret = atomicrmw xchg i128* %arg, i128 %val seq_cst
+; CHECK: call void @llvm.lifetime.start.p0(i64 16, ptr %2)
+; CHECK: call void @__atomic_exchange(i32 16, ptr %arg, ptr %1, ptr %2, i32 5)
+; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr %1)
+; CHECK: %3 = load i128, ptr %2, align 8
+; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr %2)
+; CHECK: ret i128 %3
+define i128 @test_exchange_i128(ptr %arg, i128 %val) {
+ %ret = atomicrmw xchg ptr %arg, i128 %val seq_cst
ret i128 %ret
}
; CHECK-LABEL: @test_cmpxchg_i128(
-; CHECK: %1 = bitcast i128* %arg to i8*
+; CHECK: %1 = alloca i128, align 8
+; CHECK: call void @llvm.lifetime.start.p0(i64 16, ptr %1)
+; CHECK: store i128 %old, ptr %1, align 8
; CHECK: %2 = alloca i128, align 8
-; CHECK: %3 = bitcast i128* %2 to i8*
-; CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* %3)
-; CHECK: store i128 %old, i128* %2, align 8
-; CHECK: %4 = alloca i128, align 8
-; CHECK: %5 = bitcast i128* %4 to i8*
-; CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* %5)
-; CHECK: store i128 %new, i128* %4, align 8
-; CHECK: %6 = call zeroext i1 @__atomic_compare_exchange(i32 16, i8* %1, i8* %3, i8* %5, i32 5, i32 0)
-; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* %5)
-; CHECK: %7 = load i128, i128* %2, align 8
-; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* %3)
-; CHECK: %8 = insertvalue { i128, i1 } poison, i128 %7, 0
-; CHECK: %9 = insertvalue { i128, i1 } %8, i1 %6, 1
-; CHECK: %ret = extractvalue { i128, i1 } %9, 0
+; CHECK: call void @llvm.lifetime.start.p0(i64 16, ptr %2)
+; CHECK: store i128 %new, ptr %2, align 8
+; CHECK: %3 = call zeroext i1 @__atomic_compare_exchange(i32 16, ptr %arg, ptr %1, ptr %2, i32 5, i32 0)
+; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr %2)
+; CHECK: %4 = load i128, ptr %1, align 8
+; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr %1)
+; CHECK: %5 = insertvalue { i128, i1 } poison, i128 %4, 0
+; CHECK: %6 = insertvalue { i128, i1 } %5, i1 %3, 1
+; CHECK: %ret = extractvalue { i128, i1 } %6, 0
; CHECK: ret i128 %ret
-define i128 @test_cmpxchg_i128(i128* %arg, i128 %old, i128 %new) {
- %ret_succ = cmpxchg i128* %arg, i128 %old, i128 %new seq_cst monotonic
+define i128 @test_cmpxchg_i128(ptr %arg, i128 %old, i128 %new) {
+ %ret_succ = cmpxchg ptr %arg, i128 %old, i128 %new seq_cst monotonic
%ret = extractvalue { i128, i1 } %ret_succ, 0
ret i128 %ret
}
@@ -150,90 +134,81 @@ define i128 @test_cmpxchg_i128(i128* %arg, i128 %old, i128 %new) {
; CHECK-LABEL: @test_add_i128(
; CHECK: %1 = alloca i128, align 8
; CHECK: %2 = alloca i128, align 8
-; CHECK: %3 = load i128, i128* %arg, align 16
+; CHECK: %3 = load i128, ptr %arg, align 16
; CHECK: br label %atomicrmw.start
; CHECK:atomicrmw.start:
; CHECK: %loaded = phi i128 [ %3, %0 ], [ %newloaded, %atomicrmw.start ]
; CHECK: %new = add i128 %loaded, %val
-; CHECK: %4 = bitcast i128* %arg to i8*
-; CHECK: %5 = bitcast i128* %1 to i8*
-; CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* %5)
-; CHECK: store i128 %loaded, i128* %1, align 8
-; CHECK: %6 = bitcast i128* %2 to i8*
-; CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* %6)
-; CHECK: store i128 %new, i128* %2, align 8
-; CHECK: %7 = call zeroext i1 @__atomic_compare_exchange(i32 16, i8* %4, i8* %5, i8* %6, i32 5, i32 5)
-; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* %6)
-; CHECK: %8 = load i128, i128* %1, align 8
-; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* %5)
-; CHECK: %9 = insertvalue { i128, i1 } poison, i128 %8, 0
-; CHECK: %10 = insertvalue { i128, i1 } %9, i1 %7, 1
-; CHECK: %success = extractvalue { i128, i1 } %10, 1
-; CHECK: %newloaded = extractvalue { i128, i1 } %10, 0
+; CHECK: call void @llvm.lifetime.start.p0(i64 16, ptr %1)
+; CHECK: store i128 %loaded, ptr %1, align 8
+; CHECK: call void @llvm.lifetime.start.p0(i64 16, ptr %2)
+; CHECK: store i128 %new, ptr %2, align 8
+; CHECK: %4 = call zeroext i1 @__atomic_compare_exchange(i32 16, ptr %arg, ptr %1, ptr %2, i32 5, i32 5)
+; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr %2)
+; CHECK: %5 = load i128, ptr %1, align 8
+; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr %1)
+; CHECK: %6 = insertvalue { i128, i1 } poison, i128 %5, 0
+; CHECK: %7 = insertvalue { i128, i1 } %6, i1 %4, 1
+; CHECK: %success = extractvalue { i128, i1 } %7, 1
+; CHECK: %newloaded = extractvalue { i128, i1 } %7, 0
; CHECK: br i1 %success, label %atomicrmw.end, label %atomicrmw.start
; CHECK:atomicrmw.end:
; CHECK: ret i128 %newloaded
-define i128 @test_add_i128(i128* %arg, i128 %val) {
- %ret = atomicrmw add i128* %arg, i128 %val seq_cst
+define i128 @test_add_i128(ptr %arg, i128 %val) {
+ %ret = atomicrmw add ptr %arg, i128 %val seq_cst
ret i128 %ret
}
;; Ensure that non-integer types get bitcast correctly on the way in and out of a libcall:
; CHECK-LABEL: @test_load_double(
-; CHECK: %1 = bitcast double* %arg to i8*
-; CHECK: %2 = call i64 @__atomic_load_8(i8* %1, i32 5)
-; CHECK: %3 = bitcast i64 %2 to double
-; CHECK: ret double %3
-define double @test_load_double(double* %arg, double %val) {
- %1 = load atomic double, double* %arg seq_cst, align 16
+; CHECK: %1 = call i64 @__atomic_load_8(ptr %arg, i32 5)
+; CHECK: %2 = bitcast i64 %1 to double
+; CHECK: ret double %2
+define double @test_load_double(ptr %arg, double %val) {
+ %1 = load atomic double, ptr %arg seq_cst, align 16
ret double %1
}
; CHECK-LABEL: @test_store_double(
-; CHECK: %1 = bitcast double* %arg to i8*
-; CHECK: %2 = bitcast double %val to i64
-; CHECK: call void @__atomic_store_8(i8* %1, i64 %2, i32 5)
+; CHECK: %1 = bitcast double %val to i64
+; CHECK: call void @__atomic_store_8(ptr %arg, i64 %1, i32 5)
; CHECK: ret void
-define void @test_store_double(double* %arg, double %val) {
- store atomic double %val, double* %arg seq_cst, align 16
+define void @test_store_double(ptr %arg, double %val) {
+ store atomic double %val, ptr %arg seq_cst, align 16
ret void
}
; CHECK-LABEL: @test_cmpxchg_ptr(
-; CHECK: %1 = bitcast i16** %arg to i8*
-; CHECK: %2 = alloca i16*, align 4
-; CHECK: %3 = bitcast i16** %2 to i8*
-; CHECK: call void @llvm.lifetime.start.p0i8(i64 4, i8* %3)
-; CHECK: store i16* %old, i16** %2, align 4
-; CHECK: %4 = ptrtoint i16* %new to i32
-; CHECK: %5 = call zeroext i1 @__atomic_compare_exchange_4(i8* %1, i8* %3, i32 %4, i32 5, i32 2)
-; CHECK: %6 = load i16*, i16** %2, align 4
-; CHECK: call void @llvm.lifetime.end.p0i8(i64 4, i8* %3)
-; CHECK: %7 = insertvalue { i16*, i1 } poison, i16* %6, 0
-; CHECK: %8 = insertvalue { i16*, i1 } %7, i1 %5, 1
-; CHECK: %ret = extractvalue { i16*, i1 } %8, 0
-; CHECK: ret i16* %ret
+; CHECK: %1 = alloca ptr, align 4
+; CHECK: call void @llvm.lifetime.start.p0(i64 4, ptr %1)
+; CHECK: store ptr %old, ptr %1, align 4
+; CHECK: %2 = ptrtoint ptr %new to i32
+; CHECK: %3 = call zeroext i1 @__atomic_compare_exchange_4(ptr %arg, ptr %1, i32 %2, i32 5, i32 2)
+; CHECK: %4 = load ptr, ptr %1, align 4
+; CHECK: call void @llvm.lifetime.end.p0(i64 4, ptr %1)
+; CHECK: %5 = insertvalue { ptr, i1 } poison, ptr %4, 0
+; CHECK: %6 = insertvalue { ptr, i1 } %5, i1 %3, 1
+; CHECK: %ret = extractvalue { ptr, i1 } %6, 0
+; CHECK: ret ptr %ret
; CHECK: }
-define i16* @test_cmpxchg_ptr(i16** %arg, i16* %old, i16* %new) {
- %ret_succ = cmpxchg i16** %arg, i16* %old, i16* %new seq_cst acquire
- %ret = extractvalue { i16*, i1 } %ret_succ, 0
- ret i16* %ret
+define ptr @test_cmpxchg_ptr(ptr %arg, ptr %old, ptr %new) {
+ %ret_succ = cmpxchg ptr %arg, ptr %old, ptr %new seq_cst acquire
+ %ret = extractvalue { ptr, i1 } %ret_succ, 0
+ ret ptr %ret
}
;; ...and for a non-integer type of large size too.
; CHECK-LABEL: @test_store_fp128
-; CHECK: %1 = bitcast fp128* %arg to i8*
-; CHECK: %2 = alloca fp128, align 8
-; CHECK: %3 = bitcast fp128* %2 to i8*
-; CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* %3)
-; CHECK: store fp128 %val, fp128* %2, align 8
-; CHECK: call void @__atomic_store(i32 16, i8* %1, i8* %3, i32 5)
-; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* %3)
+; CHECK: %1 = alloca fp128, align 8
+; CHECK: call void @llvm.lifetime.start.p0(i64 16, ptr %1)
+; CHECK: store fp128 %val, ptr %1, align 8
+; CHECK: call void @__atomic_store(i32 16, ptr %arg, ptr %1, i32 5)
+; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr %1)
; CHECK: ret void
-define void @test_store_fp128(fp128* %arg, fp128 %val) {
- store atomic fp128 %val, fp128* %arg seq_cst, align 16
+define void @test_store_fp128(ptr %arg, fp128 %val) {
+ store atomic fp128 %val, ptr %arg seq_cst, align 16
ret void
}
@@ -244,14 +219,14 @@ define void @test_store_fp128(fp128* %arg, fp128 %val) {
; CHECK-LABEL: @test_unaligned_load_i16(
; CHECK: __atomic_load(
-define i16 @test_unaligned_load_i16(i16* %arg) {
- %ret = load atomic i16, i16* %arg seq_cst, align 1
+define i16 @test_unaligned_load_i16(ptr %arg) {
+ %ret = load atomic i16, ptr %arg seq_cst, align 1
ret i16 %ret
}
; CHECK-LABEL: @test_unaligned_store_i16(
; CHECK: __atomic_store(
-define void @test_unaligned_store_i16(i16* %arg, i16 %val) {
- store atomic i16 %val, i16* %arg seq_cst, align 1
+define void @test_unaligned_store_i16(ptr %arg, i16 %val) {
+ store atomic i16 %val, ptr %arg seq_cst, align 1
ret void
}
diff --git a/llvm/test/Transforms/AtomicExpand/SPARC/partword.ll b/llvm/test/Transforms/AtomicExpand/SPARC/partword.ll
index 2a58dc743fe74..5bcb21105df8b 100644
--- a/llvm/test/Transforms/AtomicExpand/SPARC/partword.ll
+++ b/llvm/test/Transforms/AtomicExpand/SPARC/partword.ll
@@ -9,31 +9,30 @@
target datalayout = "E-m:e-i64:64-n32:64-S128"
target triple = "sparcv9-unknown-unknown"
-define i8 @test_cmpxchg_i8(i8* %arg, i8 %old, i8 %new) {
+define i8 @test_cmpxchg_i8(ptr %arg, i8 %old, i8 %new) {
; CHECK-LABEL: @test_cmpxchg_i8(
; CHECK-NEXT: entry:
; CHECK-NEXT: fence seq_cst
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8* @llvm.ptrmask.p0i8.i64(i8* [[ARG:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i8* [[ARG]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3
; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[PTRLSB]], 3
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP1]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8* [[ALIGNEDADDR]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[NEW:%.*]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[OLD:%.*]] to i32
; CHECK-NEXT: [[TMP6:%.*]] = shl i32 [[TMP5]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4
; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], [[INV_MASK]]
; CHECK-NEXT: br label [[PARTWORD_CMPXCHG_LOOP:%.*]]
; CHECK: partword.cmpxchg.loop:
; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ [[TMP8]], [[ENTRY:%.*]] ], [ [[TMP15:%.*]], [[PARTWORD_CMPXCHG_FAILURE:%.*]] ]
; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP4]]
; CHECK-NEXT: [[TMP11:%.*]] = or i32 [[TMP9]], [[TMP6]]
-; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[TMP11]], i32 [[TMP10]] monotonic monotonic, align 4
+; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[TMP11]], i32 [[TMP10]] monotonic monotonic, align 4
; CHECK-NEXT: [[TMP13:%.*]] = extractvalue { i32, i1 } [[TMP12]], 0
; CHECK-NEXT: [[TMP14:%.*]] = extractvalue { i32, i1 } [[TMP12]], 1
; CHECK-NEXT: br i1 [[TMP14]], label [[PARTWORD_CMPXCHG_END:%.*]], label [[PARTWORD_CMPXCHG_FAILURE]]
@@ -51,36 +50,35 @@ define i8 @test_cmpxchg_i8(i8* %arg, i8 %old, i8 %new) {
; CHECK-NEXT: ret i8 [[RET]]
;
entry:
- %ret_succ = cmpxchg i8* %arg, i8 %old, i8 %new seq_cst monotonic
+ %ret_succ = cmpxchg ptr %arg, i8 %old, i8 %new seq_cst monotonic
%ret = extractvalue { i8, i1 } %ret_succ, 0
ret i8 %ret
}
-define i16 @test_cmpxchg_i16(i16* %arg, i16 %old, i16 %new) {
+define i16 @test_cmpxchg_i16(ptr %arg, i16 %old, i16 %new) {
; CHECK-LABEL: @test_cmpxchg_i16(
; CHECK-NEXT: entry:
; CHECK-NEXT: fence seq_cst
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16* @llvm.ptrmask.p0i16.i64(i16* [[ARG:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i16* [[ARG]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3
; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[PTRLSB]], 2
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP1]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16* [[ALIGNEDADDR]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[NEW:%.*]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
; CHECK-NEXT: [[TMP5:%.*]] = zext i16 [[OLD:%.*]] to i32
; CHECK-NEXT: [[TMP6:%.*]] = shl i32 [[TMP5]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4
; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], [[INV_MASK]]
; CHECK-NEXT: br label [[PARTWORD_CMPXCHG_LOOP:%.*]]
; CHECK: partword.cmpxchg.loop:
; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ [[TMP8]], [[ENTRY:%.*]] ], [ [[TMP15:%.*]], [[PARTWORD_CMPXCHG_FAILURE:%.*]] ]
; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP4]]
; CHECK-NEXT: [[TMP11:%.*]] = or i32 [[TMP9]], [[TMP6]]
-; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[TMP11]], i32 [[TMP10]] monotonic monotonic, align 4
+; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[TMP11]], i32 [[TMP10]] monotonic monotonic, align 4
; CHECK-NEXT: [[TMP13:%.*]] = extractvalue { i32, i1 } [[TMP12]], 0
; CHECK-NEXT: [[TMP14:%.*]] = extractvalue { i32, i1 } [[TMP12]], 1
; CHECK-NEXT: br i1 [[TMP14]], label [[PARTWORD_CMPXCHG_END:%.*]], label [[PARTWORD_CMPXCHG_FAILURE]]
@@ -98,27 +96,26 @@ define i16 @test_cmpxchg_i16(i16* %arg, i16 %old, i16 %new) {
; CHECK-NEXT: ret i16 [[RET]]
;
entry:
- %ret_succ = cmpxchg i16* %arg, i16 %old, i16 %new seq_cst monotonic
+ %ret_succ = cmpxchg ptr %arg, i16 %old, i16 %new seq_cst monotonic
%ret = extractvalue { i16, i1 } %ret_succ, 0
ret i16 %ret
}
-define i16 @test_add_i16(i16* %arg, i16 %val) {
+define i16 @test_add_i16(ptr %arg, i16 %val) {
; CHECK-LABEL: @test_add_i16(
; CHECK-NEXT: entry:
; CHECK-NEXT: fence seq_cst
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16* @llvm.ptrmask.p0i16.i64(i16* [[ARG:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i16* [[ARG]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3
; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[PTRLSB]], 2
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP1]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16* [[ALIGNEDADDR]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VAL:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -126,7 +123,7 @@ define i16 @test_add_i16(i16* %arg, i16 %val) {
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[NEW]], [[MASK]]
; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP5]]
-; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP7]] monotonic monotonic, align 4
+; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP7]] monotonic monotonic, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP8]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -137,31 +134,30 @@ define i16 @test_add_i16(i16* %arg, i16 %val) {
; CHECK-NEXT: ret i16 [[EXTRACTED]]
;
entry:
- %ret = atomicrmw add i16* %arg, i16 %val seq_cst
+ %ret = atomicrmw add ptr %arg, i16 %val seq_cst
ret i16 %ret
}
-define i16 @test_xor_i16(i16* %arg, i16 %val) {
+define i16 @test_xor_i16(ptr %arg, i16 %val) {
; CHECK-LABEL: @test_xor_i16(
; CHECK-NEXT: entry:
; CHECK-NEXT: fence seq_cst
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16* @llvm.ptrmask.p0i16.i64(i16* [[ARG:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i16* [[ARG]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3
; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[PTRLSB]], 2
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP1]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16* [[ALIGNEDADDR]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VAL:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[NEW:%.*]] = xor i32 [[LOADED]], [[VALOPERAND_SHIFTED]]
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[NEW]] monotonic monotonic, align 4
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[NEW]] monotonic monotonic, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -172,31 +168,30 @@ define i16 @test_xor_i16(i16* %arg, i16 %val) {
; CHECK-NEXT: ret i16 [[EXTRACTED]]
;
entry:
- %ret = atomicrmw xor i16* %arg, i16 %val seq_cst
+ %ret = atomicrmw xor ptr %arg, i16 %val seq_cst
ret i16 %ret
}
-define i16 @test_or_i16(i16* %arg, i16 %val) {
+define i16 @test_or_i16(ptr %arg, i16 %val) {
; CHECK-LABEL: @test_or_i16(
; CHECK-NEXT: entry:
; CHECK-NEXT: fence seq_cst
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16* @llvm.ptrmask.p0i16.i64(i16* [[ARG:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i16* [[ARG]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3
; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[PTRLSB]], 2
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP1]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16* [[ALIGNEDADDR]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VAL:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[NEW:%.*]] = or i32 [[LOADED]], [[VALOPERAND_SHIFTED]]
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[NEW]] monotonic monotonic, align 4
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[NEW]] monotonic monotonic, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -207,32 +202,31 @@ define i16 @test_or_i16(i16* %arg, i16 %val) {
; CHECK-NEXT: ret i16 [[EXTRACTED]]
;
entry:
- %ret = atomicrmw or i16* %arg, i16 %val seq_cst
+ %ret = atomicrmw or ptr %arg, i16 %val seq_cst
ret i16 %ret
}
-define i16 @test_and_i16(i16* %arg, i16 %val) {
+define i16 @test_and_i16(ptr %arg, i16 %val) {
; CHECK-LABEL: @test_and_i16(
; CHECK-NEXT: entry:
; CHECK-NEXT: fence seq_cst
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16* @llvm.ptrmask.p0i16.i64(i16* [[ARG:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i16* [[ARG]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3
; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[PTRLSB]], 2
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP1]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16* [[ALIGNEDADDR]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VAL:%.*]] to i32
; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]]
; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[INV_MASK]], [[VALOPERAND_SHIFTED]]
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[NEW:%.*]] = and i32 [[LOADED]], [[ANDOPERAND]]
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[NEW]] monotonic monotonic, align 4
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[NEW]] monotonic monotonic, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -243,24 +237,23 @@ define i16 @test_and_i16(i16* %arg, i16 %val) {
; CHECK-NEXT: ret i16 [[EXTRACTED]]
;
entry:
- %ret = atomicrmw and i16* %arg, i16 %val seq_cst
+ %ret = atomicrmw and ptr %arg, i16 %val seq_cst
ret i16 %ret
}
-define i16 @test_min_i16(i16* %arg, i16 %val) {
+define i16 @test_min_i16(ptr %arg, i16 %val) {
; CHECK-LABEL: @test_min_i16(
; CHECK-NEXT: entry:
; CHECK-NEXT: fence seq_cst
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16* @llvm.ptrmask.p0i16.i64(i16* [[ARG:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i16* [[ARG]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3
; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[PTRLSB]], 2
; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP1]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16* [[ALIGNEDADDR]] to i32*
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -272,7 +265,7 @@ define i16 @test_min_i16(i16* %arg, i16 %val) {
; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] monotonic monotonic, align 4
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] monotonic monotonic, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -283,23 +276,22 @@ define i16 @test_min_i16(i16* %arg, i16 %val) {
; CHECK-NEXT: ret i16 [[EXTRACTED4]]
;
entry:
- %ret = atomicrmw min i16* %arg, i16 %val seq_cst
+ %ret = atomicrmw min ptr %arg, i16 %val seq_cst
ret i16 %ret
}
-define half @test_atomicrmw_fadd_f16(half* %ptr, half %value) {
+define half @test_atomicrmw_fadd_f16(ptr %ptr, half %value) {
; CHECK-LABEL: @test_atomicrmw_fadd_f16(
; CHECK-NEXT: fence seq_cst
-; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4)
-; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64
+; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4)
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64
; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[PTRLSB]], 2
; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 3
; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP3]] to i32
; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]]
; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1
-; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32*
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
@@ -312,7 +304,7 @@ define half @test_atomicrmw_fadd_f16(half* %ptr, half %value) {
; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]]
; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]]
; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]]
-; CHECK-NEXT: [[TMP7:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] monotonic monotonic, align 4
+; CHECK-NEXT: [[TMP7:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] monotonic monotonic, align 4
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -323,6 +315,6 @@ define half @test_atomicrmw_fadd_f16(half* %ptr, half %value) {
; CHECK-NEXT: fence seq_cst
; CHECK-NEXT: ret half [[TMP8]]
;
- %res = atomicrmw fadd half* %ptr, half %value seq_cst
+ %res = atomicrmw fadd ptr %ptr, half %value seq_cst
ret half %res
}
diff --git a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-libcall.ll b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-libcall.ll
index 0af14c5f43c4c..6343a0c697fd3 100644
--- a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-libcall.ll
+++ b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-libcall.ll
@@ -2,33 +2,29 @@
; RUN: opt -S -mtriple=i686-linux-gnu -atomic-expand %s | FileCheck %s
-define i256 @atomic_load256_libcall(i256* %ptr) nounwind {
+define i256 @atomic_load256_libcall(ptr %ptr) nounwind {
; CHECK-LABEL: @atomic_load256_libcall(
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast i256* [[PTR:%.*]] to i8*
; CHECK-NEXT: [[TMP2:%.*]] = alloca i256, align 8
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast i256* [[TMP2]] to i8*
-; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 32, i8* [[TMP3]])
-; CHECK-NEXT: call void @__atomic_load(i64 32, i8* [[TMP1]], i8* [[TMP3]], i32 0)
-; CHECK-NEXT: [[TMP4:%.*]] = load i256, i256* [[TMP2]], align 8
-; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 32, i8* [[TMP3]])
+; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 32, ptr [[TMP2]])
+; CHECK-NEXT: call void @__atomic_load(i64 32, ptr [[PTR:%.*]], ptr [[TMP2]], i32 0)
+; CHECK-NEXT: [[TMP4:%.*]] = load i256, ptr [[TMP2]], align 8
+; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 32, ptr [[TMP2]])
; CHECK-NEXT: ret i256 [[TMP4]]
;
- %result = load atomic i256, i256* %ptr unordered, align 16
+ %result = load atomic i256, ptr %ptr unordered, align 16
ret i256 %result
}
-define i256 @atomic_load256_libcall_as1(i256 addrspace(1)* %ptr) nounwind {
+define i256 @atomic_load256_libcall_as1(ptr addrspace(1) %ptr) nounwind {
; CHECK-LABEL: @atomic_load256_libcall_as1(
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast i256 addrspace(1)* [[PTR:%.*]] to i8 addrspace(1)*
-; CHECK-NEXT: [[TMP2:%.*]] = addrspacecast i8 addrspace(1)* [[TMP1]] to i8*
+; CHECK-NEXT: [[TMP2:%.*]] = addrspacecast ptr addrspace(1) [[PTR:%.*]] to ptr
; CHECK-NEXT: [[TMP3:%.*]] = alloca i256, align 8
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast i256* [[TMP3]] to i8*
-; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 32, i8* [[TMP4]])
-; CHECK-NEXT: call void @__atomic_load(i64 32, i8* [[TMP2]], i8* [[TMP4]], i32 0)
-; CHECK-NEXT: [[TMP5:%.*]] = load i256, i256* [[TMP3]], align 8
-; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 32, i8* [[TMP4]])
+; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 32, ptr [[TMP3]])
+; CHECK-NEXT: call void @__atomic_load(i64 32, ptr [[TMP2]], ptr [[TMP3]], i32 0)
+; CHECK-NEXT: [[TMP5:%.*]] = load i256, ptr [[TMP3]], align 8
+; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 32, ptr [[TMP3]])
; CHECK-NEXT: ret i256 [[TMP5]]
;
- %result = load atomic i256, i256 addrspace(1)* %ptr unordered, align 16
+ %result = load atomic i256, ptr addrspace(1) %ptr unordered, align 16
ret i256 %result
}
diff --git a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll
index 50cd74b0c4d86..dab7677086e91 100644
--- a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll
+++ b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll
@@ -4,164 +4,150 @@
; `llvm::convertAtomicStoreToIntegerType`. If X86 stops using this
; functionality, please move this test to a target which still is.
-define float @float_load_expand(float* %ptr) {
+define float @float_load_expand(ptr %ptr) {
; CHECK-LABEL: @float_load_expand
-; CHECK: %1 = bitcast float* %ptr to i32*
-; CHECK: %2 = load atomic i32, i32* %1 unordered, align 4
-; CHECK: %3 = bitcast i32 %2 to float
-; CHECK: ret float %3
- %res = load atomic float, float* %ptr unordered, align 4
+; CHECK: %1 = load atomic i32, ptr %ptr unordered, align 4
+; CHECK: %2 = bitcast i32 %1 to float
+; CHECK: ret float %2
+ %res = load atomic float, ptr %ptr unordered, align 4
ret float %res
}
-define float @float_load_expand_seq_cst(float* %ptr) {
+define float @float_load_expand_seq_cst(ptr %ptr) {
; CHECK-LABEL: @float_load_expand_seq_cst
-; CHECK: %1 = bitcast float* %ptr to i32*
-; CHECK: %2 = load atomic i32, i32* %1 seq_cst, align 4
-; CHECK: %3 = bitcast i32 %2 to float
-; CHECK: ret float %3
- %res = load atomic float, float* %ptr seq_cst, align 4
+; CHECK: %1 = load atomic i32, ptr %ptr seq_cst, align 4
+; CHECK: %2 = bitcast i32 %1 to float
+; CHECK: ret float %2
+ %res = load atomic float, ptr %ptr seq_cst, align 4
ret float %res
}
-define float @float_load_expand_vol(float* %ptr) {
+define float @float_load_expand_vol(ptr %ptr) {
; CHECK-LABEL: @float_load_expand_vol
-; CHECK: %1 = bitcast float* %ptr to i32*
-; CHECK: %2 = load atomic volatile i32, i32* %1 unordered, align 4
-; CHECK: %3 = bitcast i32 %2 to float
-; CHECK: ret float %3
- %res = load atomic volatile float, float* %ptr unordered, align 4
+; CHECK: %1 = load atomic volatile i32, ptr %ptr unordered, align 4
+; CHECK: %2 = bitcast i32 %1 to float
+; CHECK: ret float %2
+ %res = load atomic volatile float, ptr %ptr unordered, align 4
ret float %res
}
-define float @float_load_expand_addr1(float addrspace(1)* %ptr) {
+define float @float_load_expand_addr1(ptr addrspace(1) %ptr) {
; CHECK-LABEL: @float_load_expand_addr1
-; CHECK: %1 = bitcast float addrspace(1)* %ptr to i32 addrspace(1)*
-; CHECK: %2 = load atomic i32, i32 addrspace(1)* %1 unordered, align 4
-; CHECK: %3 = bitcast i32 %2 to float
-; CHECK: ret float %3
- %res = load atomic float, float addrspace(1)* %ptr unordered, align 4
+; CHECK: %1 = load atomic i32, ptr addrspace(1) %ptr unordered, align 4
+; CHECK: %2 = bitcast i32 %1 to float
+; CHECK: ret float %2
+ %res = load atomic float, ptr addrspace(1) %ptr unordered, align 4
ret float %res
}
-define void @float_store_expand(float* %ptr, float %v) {
+define void @float_store_expand(ptr %ptr, float %v) {
; CHECK-LABEL: @float_store_expand
; CHECK: %1 = bitcast float %v to i32
-; CHECK: %2 = bitcast float* %ptr to i32*
-; CHECK: store atomic i32 %1, i32* %2 unordered, align 4
- store atomic float %v, float* %ptr unordered, align 4
+; CHECK: store atomic i32 %1, ptr %ptr unordered, align 4
+ store atomic float %v, ptr %ptr unordered, align 4
ret void
}
-define void @float_store_expand_seq_cst(float* %ptr, float %v) {
+define void @float_store_expand_seq_cst(ptr %ptr, float %v) {
; CHECK-LABEL: @float_store_expand_seq_cst
; CHECK: %1 = bitcast float %v to i32
-; CHECK: %2 = bitcast float* %ptr to i32*
-; CHECK: store atomic i32 %1, i32* %2 seq_cst, align 4
- store atomic float %v, float* %ptr seq_cst, align 4
+; CHECK: store atomic i32 %1, ptr %ptr seq_cst, align 4
+ store atomic float %v, ptr %ptr seq_cst, align 4
ret void
}
-define void @float_store_expand_vol(float* %ptr, float %v) {
+define void @float_store_expand_vol(ptr %ptr, float %v) {
; CHECK-LABEL: @float_store_expand_vol
; CHECK: %1 = bitcast float %v to i32
-; CHECK: %2 = bitcast float* %ptr to i32*
-; CHECK: store atomic volatile i32 %1, i32* %2 unordered, align 4
- store atomic volatile float %v, float* %ptr unordered, align 4
+; CHECK: store atomic volatile i32 %1, ptr %ptr unordered, align 4
+ store atomic volatile float %v, ptr %ptr unordered, align 4
ret void
}
-define void @float_store_expand_addr1(float addrspace(1)* %ptr, float %v) {
+define void @float_store_expand_addr1(ptr addrspace(1) %ptr, float %v) {
; CHECK-LABEL: @float_store_expand_addr1
; CHECK: %1 = bitcast float %v to i32
-; CHECK: %2 = bitcast float addrspace(1)* %ptr to i32 addrspace(1)*
-; CHECK: store atomic i32 %1, i32 addrspace(1)* %2 unordered, align 4
- store atomic float %v, float addrspace(1)* %ptr unordered, align 4
+; CHECK: store atomic i32 %1, ptr addrspace(1) %ptr unordered, align 4
+ store atomic float %v, ptr addrspace(1) %ptr unordered, align 4
ret void
}
-define void @pointer_cmpxchg_expand(i8** %ptr, i8* %v) {
+define void @pointer_cmpxchg_expand(ptr %ptr, ptr %v) {
; CHECK-LABEL: @pointer_cmpxchg_expand
-; CHECK: %1 = bitcast i8** %ptr to i64*
-; CHECK: %2 = ptrtoint i8* %v to i64
-; CHECK: %3 = cmpxchg i64* %1, i64 0, i64 %2 seq_cst monotonic
-; CHECK: %4 = extractvalue { i64, i1 } %3, 0
-; CHECK: %5 = extractvalue { i64, i1 } %3, 1
-; CHECK: %6 = inttoptr i64 %4 to i8*
-; CHECK: %7 = insertvalue { i8*, i1 } poison, i8* %6, 0
-; CHECK: %8 = insertvalue { i8*, i1 } %7, i1 %5, 1
- cmpxchg i8** %ptr, i8* null, i8* %v seq_cst monotonic
+; CHECK: %1 = ptrtoint ptr %v to i64
+; CHECK: %2 = cmpxchg ptr %ptr, i64 0, i64 %1 seq_cst monotonic
+; CHECK: %3 = extractvalue { i64, i1 } %2, 0
+; CHECK: %4 = extractvalue { i64, i1 } %2, 1
+; CHECK: %5 = inttoptr i64 %3 to ptr
+; CHECK: %6 = insertvalue { ptr, i1 } poison, ptr %5, 0
+; CHECK: %7 = insertvalue { ptr, i1 } %6, i1 %4, 1
+ cmpxchg ptr %ptr, ptr null, ptr %v seq_cst monotonic
ret void
}
-define void @pointer_cmpxchg_expand2(i8** %ptr, i8* %v) {
+define void @pointer_cmpxchg_expand2(ptr %ptr, ptr %v) {
; CHECK-LABEL: @pointer_cmpxchg_expand2
-; CHECK: %1 = bitcast i8** %ptr to i64*
-; CHECK: %2 = ptrtoint i8* %v to i64
-; CHECK: %3 = cmpxchg i64* %1, i64 0, i64 %2 release monotonic
-; CHECK: %4 = extractvalue { i64, i1 } %3, 0
-; CHECK: %5 = extractvalue { i64, i1 } %3, 1
-; CHECK: %6 = inttoptr i64 %4 to i8*
-; CHECK: %7 = insertvalue { i8*, i1 } poison, i8* %6, 0
-; CHECK: %8 = insertvalue { i8*, i1 } %7, i1 %5, 1
- cmpxchg i8** %ptr, i8* null, i8* %v release monotonic
+; CHECK: %1 = ptrtoint ptr %v to i64
+; CHECK: %2 = cmpxchg ptr %ptr, i64 0, i64 %1 release monotonic
+; CHECK: %3 = extractvalue { i64, i1 } %2, 0
+; CHECK: %4 = extractvalue { i64, i1 } %2, 1
+; CHECK: %5 = inttoptr i64 %3 to ptr
+; CHECK: %6 = insertvalue { ptr, i1 } poison, ptr %5, 0
+; CHECK: %7 = insertvalue { ptr, i1 } %6, i1 %4, 1
+ cmpxchg ptr %ptr, ptr null, ptr %v release monotonic
ret void
}
-define void @pointer_cmpxchg_expand3(i8** %ptr, i8* %v) {
+define void @pointer_cmpxchg_expand3(ptr %ptr, ptr %v) {
; CHECK-LABEL: @pointer_cmpxchg_expand3
-; CHECK: %1 = bitcast i8** %ptr to i64*
-; CHECK: %2 = ptrtoint i8* %v to i64
-; CHECK: %3 = cmpxchg i64* %1, i64 0, i64 %2 seq_cst seq_cst
-; CHECK: %4 = extractvalue { i64, i1 } %3, 0
-; CHECK: %5 = extractvalue { i64, i1 } %3, 1
-; CHECK: %6 = inttoptr i64 %4 to i8*
-; CHECK: %7 = insertvalue { i8*, i1 } poison, i8* %6, 0
-; CHECK: %8 = insertvalue { i8*, i1 } %7, i1 %5, 1
- cmpxchg i8** %ptr, i8* null, i8* %v seq_cst seq_cst
+; CHECK: %1 = ptrtoint ptr %v to i64
+; CHECK: %2 = cmpxchg ptr %ptr, i64 0, i64 %1 seq_cst seq_cst
+; CHECK: %3 = extractvalue { i64, i1 } %2, 0
+; CHECK: %4 = extractvalue { i64, i1 } %2, 1
+; CHECK: %5 = inttoptr i64 %3 to ptr
+; CHECK: %6 = insertvalue { ptr, i1 } poison, ptr %5, 0
+; CHECK: %7 = insertvalue { ptr, i1 } %6, i1 %4, 1
+ cmpxchg ptr %ptr, ptr null, ptr %v seq_cst seq_cst
ret void
}
-define void @pointer_cmpxchg_expand4(i8** %ptr, i8* %v) {
+define void @pointer_cmpxchg_expand4(ptr %ptr, ptr %v) {
; CHECK-LABEL: @pointer_cmpxchg_expand4
-; CHECK: %1 = bitcast i8** %ptr to i64*
-; CHECK: %2 = ptrtoint i8* %v to i64
-; CHECK: %3 = cmpxchg weak i64* %1, i64 0, i64 %2 seq_cst seq_cst
-; CHECK: %4 = extractvalue { i64, i1 } %3, 0
-; CHECK: %5 = extractvalue { i64, i1 } %3, 1
-; CHECK: %6 = inttoptr i64 %4 to i8*
-; CHECK: %7 = insertvalue { i8*, i1 } poison, i8* %6, 0
-; CHECK: %8 = insertvalue { i8*, i1 } %7, i1 %5, 1
- cmpxchg weak i8** %ptr, i8* null, i8* %v seq_cst seq_cst
+; CHECK: %1 = ptrtoint ptr %v to i64
+; CHECK: %2 = cmpxchg weak ptr %ptr, i64 0, i64 %1 seq_cst seq_cst
+; CHECK: %3 = extractvalue { i64, i1 } %2, 0
+; CHECK: %4 = extractvalue { i64, i1 } %2, 1
+; CHECK: %5 = inttoptr i64 %3 to ptr
+; CHECK: %6 = insertvalue { ptr, i1 } poison, ptr %5, 0
+; CHECK: %7 = insertvalue { ptr, i1 } %6, i1 %4, 1
+ cmpxchg weak ptr %ptr, ptr null, ptr %v seq_cst seq_cst
ret void
}
-define void @pointer_cmpxchg_expand5(i8** %ptr, i8* %v) {
+define void @pointer_cmpxchg_expand5(ptr %ptr, ptr %v) {
; CHECK-LABEL: @pointer_cmpxchg_expand5
-; CHECK: %1 = bitcast i8** %ptr to i64*
-; CHECK: %2 = ptrtoint i8* %v to i64
-; CHECK: %3 = cmpxchg volatile i64* %1, i64 0, i64 %2 seq_cst seq_cst
-; CHECK: %4 = extractvalue { i64, i1 } %3, 0
-; CHECK: %5 = extractvalue { i64, i1 } %3, 1
-; CHECK: %6 = inttoptr i64 %4 to i8*
-; CHECK: %7 = insertvalue { i8*, i1 } poison, i8* %6, 0
-; CHECK: %8 = insertvalue { i8*, i1 } %7, i1 %5, 1
- cmpxchg volatile i8** %ptr, i8* null, i8* %v seq_cst seq_cst
+; CHECK: %1 = ptrtoint ptr %v to i64
+; CHECK: %2 = cmpxchg volatile ptr %ptr, i64 0, i64 %1 seq_cst seq_cst
+; CHECK: %3 = extractvalue { i64, i1 } %2, 0
+; CHECK: %4 = extractvalue { i64, i1 } %2, 1
+; CHECK: %5 = inttoptr i64 %3 to ptr
+; CHECK: %6 = insertvalue { ptr, i1 } poison, ptr %5, 0
+; CHECK: %7 = insertvalue { ptr, i1 } %6, i1 %4, 1
+ cmpxchg volatile ptr %ptr, ptr null, ptr %v seq_cst seq_cst
ret void
}
-define void @pointer_cmpxchg_expand6(i8 addrspace(2)* addrspace(1)* %ptr,
- i8 addrspace(2)* %v) {
+define void @pointer_cmpxchg_expand6(ptr addrspace(1) %ptr,
+ ptr addrspace(2) %v) {
; CHECK-LABEL: @pointer_cmpxchg_expand6
-; CHECK: %1 = bitcast i8 addrspace(2)* addrspace(1)* %ptr to i64 addrspace(1)*
-; CHECK: %2 = ptrtoint i8 addrspace(2)* %v to i64
-; CHECK: %3 = cmpxchg i64 addrspace(1)* %1, i64 0, i64 %2 seq_cst seq_cst
-; CHECK: %4 = extractvalue { i64, i1 } %3, 0
-; CHECK: %5 = extractvalue { i64, i1 } %3, 1
-; CHECK: %6 = inttoptr i64 %4 to i8 addrspace(2)*
-; CHECK: %7 = insertvalue { i8 addrspace(2)*, i1 } poison, i8 addrspace(2)* %6, 0
-; CHECK: %8 = insertvalue { i8 addrspace(2)*, i1 } %7, i1 %5, 1
- cmpxchg i8 addrspace(2)* addrspace(1)* %ptr, i8 addrspace(2)* null, i8 addrspace(2)* %v seq_cst seq_cst
+; CHECK: %1 = ptrtoint ptr addrspace(2) %v to i64
+; CHECK: %2 = cmpxchg ptr addrspace(1) %ptr, i64 0, i64 %1 seq_cst seq_cst
+; CHECK: %3 = extractvalue { i64, i1 } %2, 0
+; CHECK: %4 = extractvalue { i64, i1 } %2, 1
+; CHECK: %5 = inttoptr i64 %3 to ptr addrspace(2)
+; CHECK: %6 = insertvalue { ptr addrspace(2), i1 } poison, ptr addrspace(2) %5, 0
+; CHECK: %7 = insertvalue { ptr addrspace(2), i1 } %6, i1 %4, 1
+ cmpxchg ptr addrspace(1) %ptr, ptr addrspace(2) null, ptr addrspace(2) %v seq_cst seq_cst
ret void
}
diff --git a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-rmw-fp.ll b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-rmw-fp.ll
index e37f9bb7d5697..69837b96a90d0 100644
--- a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-rmw-fp.ll
+++ b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-rmw-fp.ll
@@ -1,17 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -mtriple=i686-linux-gnu -atomic-expand %s | FileCheck %s
-define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
+define float @test_atomicrmw_fadd_f32(ptr %ptr, float %value) {
; CHECK-LABEL: @test_atomicrmw_fadd_f32(
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -19,21 +18,20 @@ define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
; CHECK: atomicrmw.end:
; CHECK-NEXT: ret float [[TMP6]]
;
- %res = atomicrmw fadd float* %ptr, float %value seq_cst
+ %res = atomicrmw fadd ptr %ptr, float %value seq_cst
ret float %res
}
-define double @test_atomicrmw_fadd_f64(double* %ptr, double %value) {
+define double @test_atomicrmw_fadd_f64(ptr %ptr, double %value) {
; CHECK-LABEL: @test_atomicrmw_fadd_f64(
-; CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8
+; CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64*
; CHECK-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; CHECK-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -41,21 +39,20 @@ define double @test_atomicrmw_fadd_f64(double* %ptr, double %value) {
; CHECK: atomicrmw.end:
; CHECK-NEXT: ret double [[TMP6]]
;
- %res = atomicrmw fadd double* %ptr, double %value seq_cst
+ %res = atomicrmw fadd ptr %ptr, double %value seq_cst
ret double %res
}
-define float @test_atomicrmw_fadd_f32_as1(float addrspace(1)* %ptr, float %value) {
+define float @test_atomicrmw_fadd_f32_as1(ptr addrspace(1) %ptr, float %value) {
; CHECK-LABEL: @test_atomicrmw_fadd_f32_as1(
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)*
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -63,21 +60,20 @@ define float @test_atomicrmw_fadd_f32_as1(float addrspace(1)* %ptr, float %value
; CHECK: atomicrmw.end:
; CHECK-NEXT: ret float [[TMP6]]
;
- %res = atomicrmw fadd float addrspace(1)* %ptr, float %value seq_cst
+ %res = atomicrmw fadd ptr addrspace(1) %ptr, float %value seq_cst
ret float %res
}
-define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
+define float @test_atomicrmw_fsub_f32(ptr %ptr, float %value) {
; CHECK-LABEL: @test_atomicrmw_fsub_f32(
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
@@ -85,21 +81,20 @@ define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
; CHECK: atomicrmw.end:
; CHECK-NEXT: ret float [[TMP6]]
;
- %res = atomicrmw fsub float* %ptr, float %value seq_cst
+ %res = atomicrmw fsub ptr %ptr, float %value seq_cst
ret float %res
}
-define double @test_atomicrmw_fsub_f64(double* %ptr, double %value) {
+define double @test_atomicrmw_fsub_f64(ptr %ptr, double %value) {
; CHECK-LABEL: @test_atomicrmw_fsub_f64(
-; CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8
+; CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
; CHECK-NEXT: [[NEW:%.*]] = fsub double [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64*
; CHECK-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst
+; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; CHECK-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double
@@ -107,6 +102,6 @@ define double @test_atomicrmw_fsub_f64(double* %ptr, double %value) {
; CHECK: atomicrmw.end:
; CHECK-NEXT: ret double [[TMP6]]
;
- %res = atomicrmw fsub double* %ptr, double %value seq_cst
+ %res = atomicrmw fsub ptr %ptr, double %value seq_cst
ret double %res
}
diff --git a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-rmw-initial-load.ll b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-rmw-initial-load.ll
index 029a0e7b3e926..fba1512368ea2 100644
--- a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-rmw-initial-load.ll
+++ b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-rmw-initial-load.ll
@@ -3,9 +3,9 @@
; This file tests the function `llvm::expandAtomicRMWToCmpXchg`.
; It isn't technically target specific, but is exposed through a pass that is.
-define i8 @test_initial_load(i8* %ptr, i8 %value) {
- %res = atomicrmw nand i8* %ptr, i8 %value seq_cst
+define i8 @test_initial_load(ptr %ptr, i8 %value) {
+ %res = atomicrmw nand ptr %ptr, i8 %value seq_cst
ret i8 %res
}
; CHECK-LABEL: @test_initial_load
-; CHECK-NEXT: %1 = load i8, i8* %ptr, align 1
+; CHECK-NEXT: %1 = load i8, ptr %ptr, align 1
diff --git a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-xchg-fp.ll b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-xchg-fp.ll
index e7a540df986e5..2464af3336ef3 100644
--- a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-xchg-fp.ll
+++ b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-xchg-fp.ll
@@ -1,14 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -mtriple=i686-linux-gnu -atomic-expand %s | FileCheck %s
-define double @atomic_xchg_f64(double* %ptr) nounwind {
+define double @atomic_xchg_f64(ptr %ptr) nounwind {
; CHECK-LABEL: @atomic_xchg_f64(
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast double* [[PTR:%.*]] to i64*
-; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* [[TMP1]], align 8
+; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[PTR:%.*]], align 8
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
-; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg i64* [[TMP1]], i64 [[LOADED]], i64 4616189618054758400 seq_cst seq_cst, align 8
+; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg ptr [[PTR]], i64 [[LOADED]], i64 4616189618054758400 seq_cst seq_cst, align 8
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP3]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP3]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -16,18 +15,17 @@ define double @atomic_xchg_f64(double* %ptr) nounwind {
; CHECK-NEXT: [[TMP4:%.*]] = bitcast i64 [[NEWLOADED]] to double
; CHECK-NEXT: ret double [[TMP4]]
;
- %result = atomicrmw xchg double* %ptr, double 4.0 seq_cst
+ %result = atomicrmw xchg ptr %ptr, double 4.0 seq_cst
ret double %result
}
-define double @atomic_xchg_f64_as1(double addrspace(1)* %ptr) nounwind {
+define double @atomic_xchg_f64_as1(ptr addrspace(1) %ptr) nounwind {
; CHECK-LABEL: @atomic_xchg_f64_as1(
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast double addrspace(1)* [[PTR:%.*]] to i64 addrspace(1)*
-; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64 addrspace(1)* [[TMP1]], align 8
+; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr addrspace(1) [[PTR:%.*]], align 8
; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
; CHECK: atomicrmw.start:
; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ]
-; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg i64 addrspace(1)* [[TMP1]], i64 [[LOADED]], i64 4616189618054758400 seq_cst seq_cst, align 8
+; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[LOADED]], i64 4616189618054758400 seq_cst seq_cst, align 8
; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP3]], 1
; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP3]], 0
; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
@@ -35,6 +33,6 @@ define double @atomic_xchg_f64_as1(double addrspace(1)* %ptr) nounwind {
; CHECK-NEXT: [[TMP4:%.*]] = bitcast i64 [[NEWLOADED]] to double
; CHECK-NEXT: ret double [[TMP4]]
;
- %result = atomicrmw xchg double addrspace(1)* %ptr, double 4.0 seq_cst
+ %result = atomicrmw xchg ptr addrspace(1) %ptr, double 4.0 seq_cst
ret double %result
}
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