[PATCH] D98101: [RISCV] Enable the LocalStackSlotAllocation pass support

[LiDongjin via Phabricator via llvm-commits]

LiDongjin updated this revision to Diff 478127.
LiDongjin added a comment.

For the failures in the llvm-testsuite, it seems some problems for Add instruction which generates wrong frame index.
Also in Arm and AArch64, No need to support for Add instruction.
Therefore load/store(exclude vector load/store) instruction is enough for LocalStackSlotAllocation pass.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98101/new/

https://reviews.llvm.org/D98101

Files:
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll

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