[llvm] 1c55cc6 - PhaseOrdering: Convert tests to opaque pointers
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 27 18:41:22 PST 2022
Author: Matt Arsenault
Date: 2022-11-27T21:26:41-05:00
New Revision: 1c55cc600e99a963233d6f467373c8f16a1b8826
URL: https://github.com/llvm/llvm-project/commit/1c55cc600e99a963233d6f467373c8f16a1b8826
DIFF: https://github.com/llvm/llvm-project/commit/1c55cc600e99a963233d6f467373c8f16a1b8826.diff
LOG: PhaseOrdering: Convert tests to opaque pointers
Required manually running update_test_checks:
AArch64/hoisting-sinking-required-for-vectorization.ll
AArch64/peel-multiple-unreachable-exits-for-vectorization.ll
ARM/arm_mult_q15.ll
X86/hoist-load-of-baseptr.ll
X86/spurious-peeling.ll
Added:
Modified:
llvm/test/Transforms/PhaseOrdering/2010-03-22-empty-baseclass.ll
llvm/test/Transforms/PhaseOrdering/AArch64/globals-aa-required-for-vectorization.ll
llvm/test/Transforms/PhaseOrdering/AArch64/hoisting-sinking-required-for-vectorization.ll
llvm/test/Transforms/PhaseOrdering/AArch64/loopflatten.ll
llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
llvm/test/Transforms/PhaseOrdering/AArch64/mul-ov.ll
llvm/test/Transforms/PhaseOrdering/AArch64/peel-multiple-unreachable-exits-for-vectorization.ll
llvm/test/Transforms/PhaseOrdering/ARM/arm_add_q7.ll
llvm/test/Transforms/PhaseOrdering/ARM/arm_fill_q7.ll
llvm/test/Transforms/PhaseOrdering/ARM/arm_mult_q15.ll
llvm/test/Transforms/PhaseOrdering/PR6627.ll
llvm/test/Transforms/PhaseOrdering/X86/SROA-after-final-loop-unrolling-2.ll
llvm/test/Transforms/PhaseOrdering/X86/SROA-after-loop-unrolling.ll
llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
llvm/test/Transforms/PhaseOrdering/X86/addsub.ll
llvm/test/Transforms/PhaseOrdering/X86/earlycse-after-simplifycfg-two-entry-phi-node-folding.ll
llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll
llvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll
llvm/test/Transforms/PhaseOrdering/X86/masked-memory-ops.ll
llvm/test/Transforms/PhaseOrdering/X86/merge-functions.ll
llvm/test/Transforms/PhaseOrdering/X86/nancvt.ll
llvm/test/Transforms/PhaseOrdering/X86/peel-before-lv-to-enable-vectorization.ll
llvm/test/Transforms/PhaseOrdering/X86/pixel-splat.ll
llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll
llvm/test/Transforms/PhaseOrdering/X86/pr50555.ll
llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll
llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll
llvm/test/Transforms/PhaseOrdering/X86/store-constant-merge.ll
llvm/test/Transforms/PhaseOrdering/X86/vdiv-nounroll.ll
llvm/test/Transforms/PhaseOrdering/X86/vdiv.ll
llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll
llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
llvm/test/Transforms/PhaseOrdering/assume-explosion.ll
llvm/test/Transforms/PhaseOrdering/basic.ll
llvm/test/Transforms/PhaseOrdering/cmp-logic.ll
llvm/test/Transforms/PhaseOrdering/d83507-knowledge-retention-bug.ll
llvm/test/Transforms/PhaseOrdering/dce-after-argument-promotion.ll
llvm/test/Transforms/PhaseOrdering/deletion-of-loops-that-became-side-effect-free.ll
llvm/test/Transforms/PhaseOrdering/expect.ll
llvm/test/Transforms/PhaseOrdering/fast-reassociate-gvn.ll
llvm/test/Transforms/PhaseOrdering/gdce.ll
llvm/test/Transforms/PhaseOrdering/globalaa-retained.ll
llvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll
llvm/test/Transforms/PhaseOrdering/instcombine-sroa-inttoptr.ll
llvm/test/Transforms/PhaseOrdering/lifetime-sanitizer.ll
llvm/test/Transforms/PhaseOrdering/loop-rotation-vs-common-code-hoisting.ll
llvm/test/Transforms/PhaseOrdering/lto-licm.ll
llvm/test/Transforms/PhaseOrdering/openmp-opt-module.ll
llvm/test/Transforms/PhaseOrdering/pr32544.ll
llvm/test/Transforms/PhaseOrdering/pr36760.ll
llvm/test/Transforms/PhaseOrdering/pr39282.ll
llvm/test/Transforms/PhaseOrdering/pr40750.ll
llvm/test/Transforms/PhaseOrdering/pr45682.ll
llvm/test/Transforms/PhaseOrdering/reassociate-after-unroll.ll
llvm/test/Transforms/PhaseOrdering/recompute-globalsaa.ll
llvm/test/Transforms/PhaseOrdering/scev-custom-dl.ll
llvm/test/Transforms/PhaseOrdering/scev.ll
llvm/test/Transforms/PhaseOrdering/simplifycfg-options.ll
llvm/test/Transforms/PhaseOrdering/two-shifts-by-sext.ll
llvm/test/Transforms/PhaseOrdering/vector-select.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/PhaseOrdering/2010-03-22-empty-baseclass.ll b/llvm/test/Transforms/PhaseOrdering/2010-03-22-empty-baseclass.ll
index 13404a8b6a719..42e846c138734 100644
--- a/llvm/test/Transforms/PhaseOrdering/2010-03-22-empty-baseclass.ll
+++ b/llvm/test/Transforms/PhaseOrdering/2010-03-22-empty-baseclass.ll
@@ -8,155 +8,154 @@ target triple = "x86_64-apple-darwin11.1"
%struct.empty_base_t = type <{ i8 }>
%struct.empty_t = type <{ i8 }>
- at .str = private constant [25 x i8] c"x.second() was clobbered\00", align 1 ; <[25 x i8]*> [#uses=1]
+ at .str = private constant [25 x i8] c"x.second() was clobbered\00", align 1 ; <ptr> [#uses=1]
-define i32 @main(i32 %argc, i8** %argv) ssp {
+define i32 @main(i32 %argc, ptr %argv) ssp {
entry:
- %argc_addr = alloca i32, align 4 ; <i32*> [#uses=1]
- %argv_addr = alloca i8**, align 8 ; <i8***> [#uses=1]
- %retval = alloca i32 ; <i32*> [#uses=2]
- %0 = alloca i32 ; <i32*> [#uses=2]
- %retval.1 = alloca i8 ; <i8*> [#uses=2]
- %1 = alloca %struct.empty_base_t ; <%struct.empty_base_t*> [#uses=1]
- %2 = alloca %struct.empty_base_t* ; <%struct.empty_base_t**> [#uses=1]
- %x = alloca %"struct.boost::compressed_pair<empty_t,int>" ; <%"struct.boost::compressed_pair<empty_t,int>"*> [#uses=3]
+ %argc_addr = alloca i32, align 4 ; <ptr> [#uses=1]
+ %argv_addr = alloca ptr, align 8 ; <ptr> [#uses=1]
+ %retval = alloca i32 ; <ptr> [#uses=2]
+ %0 = alloca i32 ; <ptr> [#uses=2]
+ %retval.1 = alloca i8 ; <ptr> [#uses=2]
+ %1 = alloca %struct.empty_base_t ; <ptr> [#uses=1]
+ %2 = alloca ptr ; <ptr> [#uses=1]
+ %x = alloca %"struct.boost::compressed_pair<empty_t,int>" ; <ptr> [#uses=3]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
- store i32 %argc, i32* %argc_addr
- store i8** %argv, i8*** %argv_addr
- %3 = call i32* @_ZN5boost15compressed_pairI7empty_tiE6secondEv(%"struct.boost::compressed_pair<empty_t,int>"* %x) ssp ; <i32*> [#uses=1]
- store i32 -3, i32* %3, align 4
- %4 = call %struct.empty_base_t* @_ZN5boost15compressed_pairI7empty_tiE5firstEv(%"struct.boost::compressed_pair<empty_t,int>"* %x) ssp ; <%struct.empty_base_t*> [#uses=1]
- store %struct.empty_base_t* %4, %struct.empty_base_t** %2, align 8
- call void @_ZN7empty_tC1Ev(%struct.empty_base_t* %1) nounwind
- %5 = call i32* @_ZN5boost15compressed_pairI7empty_tiE6secondEv(%"struct.boost::compressed_pair<empty_t,int>"* %x) ssp ; <i32*> [#uses=1]
- %6 = load i32, i32* %5, align 4 ; <i32> [#uses=1]
+ store i32 %argc, ptr %argc_addr
+ store ptr %argv, ptr %argv_addr
+ %3 = call ptr @_ZN5boost15compressed_pairI7empty_tiE6secondEv(ptr %x) ssp ; <ptr> [#uses=1]
+ store i32 -3, ptr %3, align 4
+ %4 = call ptr @_ZN5boost15compressed_pairI7empty_tiE5firstEv(ptr %x) ssp ; <ptr> [#uses=1]
+ store ptr %4, ptr %2, align 8
+ call void @_ZN7empty_tC1Ev(ptr %1) nounwind
+ %5 = call ptr @_ZN5boost15compressed_pairI7empty_tiE6secondEv(ptr %x) ssp ; <ptr> [#uses=1]
+ %6 = load i32, ptr %5, align 4 ; <i32> [#uses=1]
%7 = icmp ne i32 %6, -3 ; <i1> [#uses=1]
%8 = zext i1 %7 to i8 ; <i8> [#uses=1]
- store i8 %8, i8* %retval.1, align 1
- %9 = load i8, i8* %retval.1, align 1 ; <i8> [#uses=1]
+ store i8 %8, ptr %retval.1, align 1
+ %9 = load i8, ptr %retval.1, align 1 ; <i8> [#uses=1]
%toBool = icmp ne i8 %9, 0 ; <i1> [#uses=1]
br i1 %toBool, label %bb, label %bb1
bb: ; preds = %entry
- %10 = call i32 @puts(i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i64 0, i64 0)) ; <i32> [#uses=0]
+ %10 = call i32 @puts(ptr @.str) ; <i32> [#uses=0]
call void @abort() noreturn
unreachable
bb1: ; preds = %entry
- store i32 0, i32* %0, align 4
- %11 = load i32, i32* %0, align 4 ; <i32> [#uses=1]
- store i32 %11, i32* %retval, align 4
+ store i32 0, ptr %0, align 4
+ %11 = load i32, ptr %0, align 4 ; <i32> [#uses=1]
+ store i32 %11, ptr %retval, align 4
br label %return
; CHECK-NOT: x.second() was clobbered
; CHECK: ret i32
return: ; preds = %bb1
- %retval2 = load i32, i32* %retval ; <i32> [#uses=1]
+ %retval2 = load i32, ptr %retval ; <i32> [#uses=1]
ret i32 %retval2
}
-define linkonce_odr void @_ZN12empty_base_tC2Ev(%struct.empty_base_t* %this) nounwind ssp align 2 {
+define linkonce_odr void @_ZN12empty_base_tC2Ev(ptr %this) nounwind ssp align 2 {
entry:
- %this_addr = alloca %struct.empty_base_t*, align 8 ; <%struct.empty_base_t**> [#uses=1]
+ %this_addr = alloca ptr, align 8 ; <ptr> [#uses=1]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
- store %struct.empty_base_t* %this, %struct.empty_base_t** %this_addr
+ store ptr %this, ptr %this_addr
br label %return
return: ; preds = %entry
ret void
}
-define linkonce_odr void @_ZN7empty_tC1Ev(%struct.empty_base_t* %this) nounwind ssp align 2 {
+define linkonce_odr void @_ZN7empty_tC1Ev(ptr %this) nounwind ssp align 2 {
entry:
- %this_addr = alloca %struct.empty_base_t*, align 8 ; <%struct.empty_base_t**> [#uses=2]
+ %this_addr = alloca ptr, align 8 ; <ptr> [#uses=2]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
- store %struct.empty_base_t* %this, %struct.empty_base_t** %this_addr
- %0 = load %struct.empty_base_t*, %struct.empty_base_t** %this_addr, align 8 ; <%struct.empty_base_t*> [#uses=1]
- call void @_ZN12empty_base_tC2Ev(%struct.empty_base_t* %0) nounwind
+ store ptr %this, ptr %this_addr
+ %0 = load ptr, ptr %this_addr, align 8 ; <ptr> [#uses=1]
+ call void @_ZN12empty_base_tC2Ev(ptr %0) nounwind
br label %return
return: ; preds = %entry
ret void
}
-define linkonce_odr i32* @_ZN5boost7details19compressed_pair_impI7empty_tiLi1EE6secondEv(%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %this) nounwind ssp align 2 {
+define linkonce_odr ptr @_ZN5boost7details19compressed_pair_impI7empty_tiLi1EE6secondEv(ptr %this) nounwind ssp align 2 {
entry:
- %this_addr = alloca %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*, align 8 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"**> [#uses=2]
- %retval = alloca i32* ; <i32**> [#uses=2]
- %0 = alloca i32* ; <i32**> [#uses=2]
+ %this_addr = alloca ptr, align 8 ; <ptr> [#uses=2]
+ %retval = alloca ptr ; <ptr> [#uses=2]
+ %0 = alloca ptr ; <ptr> [#uses=2]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
- store %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %this, %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"** %this_addr
- %1 = load %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*, %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"** %this_addr, align 8 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*> [#uses=1]
- %2 = getelementptr inbounds %"struct.boost::details::compressed_pair_imp<empty_t,int,1>", %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %1, i32 0, i32 0 ; <i32*> [#uses=1]
- store i32* %2, i32** %0, align 8
- %3 = load i32*, i32** %0, align 8 ; <i32*> [#uses=1]
- store i32* %3, i32** %retval, align 8
+ store ptr %this, ptr %this_addr
+ %1 = load ptr, ptr %this_addr, align 8 ; <ptr> [#uses=1]
+ %2 = getelementptr inbounds %"struct.boost::details::compressed_pair_imp<empty_t,int,1>", ptr %1, i32 0, i32 0 ; <ptr> [#uses=1]
+ store ptr %2, ptr %0, align 8
+ %3 = load ptr, ptr %0, align 8 ; <ptr> [#uses=1]
+ store ptr %3, ptr %retval, align 8
br label %return
return: ; preds = %entry
- %retval1 = load i32*, i32** %retval ; <i32*> [#uses=1]
- ret i32* %retval1
+ %retval1 = load ptr, ptr %retval ; <ptr> [#uses=1]
+ ret ptr %retval1
}
-define linkonce_odr i32* @_ZN5boost15compressed_pairI7empty_tiE6secondEv(%"struct.boost::compressed_pair<empty_t,int>"* %this) ssp align 2 {
+define linkonce_odr ptr @_ZN5boost15compressed_pairI7empty_tiE6secondEv(ptr %this) ssp align 2 {
entry:
- %this_addr = alloca %"struct.boost::compressed_pair<empty_t,int>"*, align 8 ; <%"struct.boost::compressed_pair<empty_t,int>"**> [#uses=2]
- %retval = alloca i32* ; <i32**> [#uses=2]
- %0 = alloca i32* ; <i32**> [#uses=2]
+ %this_addr = alloca ptr, align 8 ; <ptr> [#uses=2]
+ %retval = alloca ptr ; <ptr> [#uses=2]
+ %0 = alloca ptr ; <ptr> [#uses=2]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
- store %"struct.boost::compressed_pair<empty_t,int>"* %this, %"struct.boost::compressed_pair<empty_t,int>"** %this_addr
- %1 = load %"struct.boost::compressed_pair<empty_t,int>"*, %"struct.boost::compressed_pair<empty_t,int>"** %this_addr, align 8 ; <%"struct.boost::compressed_pair<empty_t,int>"*> [#uses=1]
- %2 = getelementptr inbounds %"struct.boost::compressed_pair<empty_t,int>", %"struct.boost::compressed_pair<empty_t,int>"* %1, i32 0, i32 0 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*> [#uses=1]
- %3 = call i32* @_ZN5boost7details19compressed_pair_impI7empty_tiLi1EE6secondEv(%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %2) nounwind ; <i32*> [#uses=1]
- store i32* %3, i32** %0, align 8
- %4 = load i32*, i32** %0, align 8 ; <i32*> [#uses=1]
- store i32* %4, i32** %retval, align 8
+ store ptr %this, ptr %this_addr
+ %1 = load ptr, ptr %this_addr, align 8 ; <ptr> [#uses=1]
+ %2 = getelementptr inbounds %"struct.boost::compressed_pair<empty_t,int>", ptr %1, i32 0, i32 0 ; <ptr> [#uses=1]
+ %3 = call ptr @_ZN5boost7details19compressed_pair_impI7empty_tiLi1EE6secondEv(ptr %2) nounwind ; <ptr> [#uses=1]
+ store ptr %3, ptr %0, align 8
+ %4 = load ptr, ptr %0, align 8 ; <ptr> [#uses=1]
+ store ptr %4, ptr %retval, align 8
br label %return
return: ; preds = %entry
- %retval1 = load i32*, i32** %retval ; <i32*> [#uses=1]
- ret i32* %retval1
+ %retval1 = load ptr, ptr %retval ; <ptr> [#uses=1]
+ ret ptr %retval1
}
-define linkonce_odr %struct.empty_base_t* @_ZN5boost7details19compressed_pair_impI7empty_tiLi1EE5firstEv(%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %this) nounwind ssp align 2 {
+define linkonce_odr ptr @_ZN5boost7details19compressed_pair_impI7empty_tiLi1EE5firstEv(ptr %this) nounwind ssp align 2 {
entry:
- %this_addr = alloca %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*, align 8 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"**> [#uses=2]
- %retval = alloca %struct.empty_base_t* ; <%struct.empty_base_t**> [#uses=2]
- %0 = alloca %struct.empty_base_t* ; <%struct.empty_base_t**> [#uses=2]
+ %this_addr = alloca ptr, align 8 ; <ptr> [#uses=2]
+ %retval = alloca ptr ; <ptr> [#uses=2]
+ %0 = alloca ptr ; <ptr> [#uses=2]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
- store %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %this, %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"** %this_addr
- %1 = load %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*, %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"** %this_addr, align 8 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*> [#uses=1]
- %2 = bitcast %"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %1 to %struct.empty_base_t* ; <%struct.empty_base_t*> [#uses=1]
- store %struct.empty_base_t* %2, %struct.empty_base_t** %0, align 8
- %3 = load %struct.empty_base_t*, %struct.empty_base_t** %0, align 8 ; <%struct.empty_base_t*> [#uses=1]
- store %struct.empty_base_t* %3, %struct.empty_base_t** %retval, align 8
+ store ptr %this, ptr %this_addr
+ %1 = load ptr, ptr %this_addr, align 8 ; <ptr> [#uses=1]
+ store ptr %1, ptr %0, align 8
+ %2 = load ptr, ptr %0, align 8 ; <ptr> [#uses=1]
+ store ptr %2, ptr %retval, align 8
br label %return
return: ; preds = %entry
- %retval1 = load %struct.empty_base_t*, %struct.empty_base_t** %retval ; <%struct.empty_base_t*> [#uses=1]
- ret %struct.empty_base_t* %retval1
+ %retval1 = load ptr, ptr %retval ; <ptr> [#uses=1]
+ ret ptr %retval1
}
-define linkonce_odr %struct.empty_base_t* @_ZN5boost15compressed_pairI7empty_tiE5firstEv(%"struct.boost::compressed_pair<empty_t,int>"* %this) ssp align 2 {
+define linkonce_odr ptr @_ZN5boost15compressed_pairI7empty_tiE5firstEv(ptr %this) ssp align 2 {
entry:
- %this_addr = alloca %"struct.boost::compressed_pair<empty_t,int>"*, align 8 ; <%"struct.boost::compressed_pair<empty_t,int>"**> [#uses=2]
- %retval = alloca %struct.empty_base_t* ; <%struct.empty_base_t**> [#uses=2]
- %0 = alloca %struct.empty_base_t* ; <%struct.empty_base_t**> [#uses=2]
+ %this_addr = alloca ptr, align 8 ; <ptr> [#uses=2]
+ %retval = alloca ptr ; <ptr> [#uses=2]
+ %0 = alloca ptr ; <ptr> [#uses=2]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
- store %"struct.boost::compressed_pair<empty_t,int>"* %this, %"struct.boost::compressed_pair<empty_t,int>"** %this_addr
- %1 = load %"struct.boost::compressed_pair<empty_t,int>"*, %"struct.boost::compressed_pair<empty_t,int>"** %this_addr, align 8 ; <%"struct.boost::compressed_pair<empty_t,int>"*> [#uses=1]
- %2 = getelementptr inbounds %"struct.boost::compressed_pair<empty_t,int>", %"struct.boost::compressed_pair<empty_t,int>"* %1, i32 0, i32 0 ; <%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"*> [#uses=1]
- %3 = call %struct.empty_base_t* @_ZN5boost7details19compressed_pair_impI7empty_tiLi1EE5firstEv(%"struct.boost::details::compressed_pair_imp<empty_t,int,1>"* %2) nounwind ; <%struct.empty_base_t*> [#uses=1]
- store %struct.empty_base_t* %3, %struct.empty_base_t** %0, align 8
- %4 = load %struct.empty_base_t*, %struct.empty_base_t** %0, align 8 ; <%struct.empty_base_t*> [#uses=1]
- store %struct.empty_base_t* %4, %struct.empty_base_t** %retval, align 8
+ store ptr %this, ptr %this_addr
+ %1 = load ptr, ptr %this_addr, align 8 ; <ptr> [#uses=1]
+ %2 = getelementptr inbounds %"struct.boost::compressed_pair<empty_t,int>", ptr %1, i32 0, i32 0 ; <ptr> [#uses=1]
+ %3 = call ptr @_ZN5boost7details19compressed_pair_impI7empty_tiLi1EE5firstEv(ptr %2) nounwind ; <ptr> [#uses=1]
+ store ptr %3, ptr %0, align 8
+ %4 = load ptr, ptr %0, align 8 ; <ptr> [#uses=1]
+ store ptr %4, ptr %retval, align 8
br label %return
return: ; preds = %entry
- %retval1 = load %struct.empty_base_t*, %struct.empty_base_t** %retval ; <%struct.empty_base_t*> [#uses=1]
- ret %struct.empty_base_t* %retval1
+ %retval1 = load ptr, ptr %retval ; <ptr> [#uses=1]
+ ret ptr %retval1
}
-declare i32 @puts(i8*)
+declare i32 @puts(ptr)
declare void @abort() noreturn
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/globals-aa-required-for-vectorization.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/globals-aa-required-for-vectorization.ll
index 130b176b9f776..4f7348f7c6e5a 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/globals-aa-required-for-vectorization.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/globals-aa-required-for-vectorization.ll
@@ -2,8 +2,8 @@
target triple = "arm64e-apple-darwin"
- at A = external unnamed_addr global i8**, align 8
- at B = external unnamed_addr global i8**, align 8
+ at A = external unnamed_addr global ptr, align 8
+ at B = external unnamed_addr global ptr, align 8
@C = internal unnamed_addr global i32 0, align 4
@D = external unnamed_addr global i32, align 4
@@ -12,27 +12,25 @@ target triple = "arm64e-apple-darwin"
;
define void @fn() {
entry:
- %v.D = load i32, i32* @D, align 4
- store i32 %v.D, i32* @C, align 4
+ %v.D = load i32, ptr @D, align 4
+ store i32 %v.D, ptr @C, align 4
call void @clobber()
- %v.B = load i8**, i8*** @B, align 8
- %v.A = load i8**, i8*** @A, align 8
- %gep.1 = getelementptr inbounds i8*, i8** %v.A, i64 0
- %v.gep.1 = load i8*, i8** %gep.1, align 8
- %gep.2 = getelementptr inbounds i8*, i8** %v.B, i64 0
- %v.gep.2 = load i8*, i8** %gep.2, align 8
- %cmp = icmp eq i8* %v.gep.2, null
+ %v.B = load ptr, ptr @B, align 8
+ %v.A = load ptr, ptr @A, align 8
+ %v.gep.1 = load ptr, ptr %v.A, align 8
+ %v.gep.2 = load ptr, ptr %v.B, align 8
+ %cmp = icmp eq ptr %v.gep.2, null
br i1 %cmp, label %exit, label %loop
loop:
%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
- %gep.3 = getelementptr inbounds i8, i8* %v.gep.2, i32 %iv
- %v.gep.3 = load i8, i8* %gep.3, align 1
- %gep.4 = getelementptr inbounds i8, i8* %v.gep.1, i32 %iv
- store i8 %v.gep.3, i8* %gep.4, align 1
+ %gep.3 = getelementptr inbounds i8, ptr %v.gep.2, i32 %iv
+ %v.gep.3 = load i8, ptr %gep.3, align 1
+ %gep.4 = getelementptr inbounds i8, ptr %v.gep.1, i32 %iv
+ store i8 %v.gep.3, ptr %gep.4, align 1
%iv.next = add nuw nsw i32 %iv, 1
- %v.C = load i32, i32* @C, align 4
+ %v.C = load i32, ptr @C, align 4
%exit.cond = icmp sgt i32 %iv, %v.C
br i1 %exit.cond, label %exit, label %loop
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/hoisting-sinking-required-for-vectorization.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/hoisting-sinking-required-for-vectorization.ll
index caf794e965160..5dc938b61785d 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/hoisting-sinking-required-for-vectorization.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/hoisting-sinking-required-for-vectorization.ll
@@ -10,124 +10,118 @@ define internal double @clamp(double %v) {
entry:
%retval = alloca double, align 8
%v.addr = alloca double, align 8
- store double %v, double* %v.addr, align 8
- %0 = load double, double* %v.addr, align 8
+ store double %v, ptr %v.addr, align 8
+ %0 = load double, ptr %v.addr, align 8
%cmp = fcmp olt double %0, 0.000000e+00
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
- store double 0.000000e+00, double* %retval, align 8
+ store double 0.000000e+00, ptr %retval, align 8
br label %return
if.end: ; preds = %entry
- %1 = load double, double* %v.addr, align 8
+ %1 = load double, ptr %v.addr, align 8
%cmp1 = fcmp ogt double %1, 6.000000e+00
br i1 %cmp1, label %if.then2, label %if.end3
if.then2: ; preds = %if.end
- store double 6.000000e+00, double* %retval, align 8
+ store double 6.000000e+00, ptr %retval, align 8
br label %return
if.end3: ; preds = %if.end
- %2 = load double, double* %v.addr, align 8
- store double %2, double* %retval, align 8
+ %2 = load double, ptr %v.addr, align 8
+ store double %2, ptr %retval, align 8
br label %return
return: ; preds = %if.end3, %if.then2, %if.then
- %3 = load double, double* %retval, align 8
+ %3 = load double, ptr %retval, align 8
ret double %3
}
-define void @loop(double* %X, double* %Y) {
+define void @loop(ptr %X, ptr %Y) {
; CHECK-LABEL: @loop(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[X6:%.*]] = ptrtoint double* [[X:%.*]] to i64
-; CHECK-NEXT: [[Y7:%.*]] = ptrtoint double* [[Y:%.*]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[X6]], [[Y7]]
+; CHECK-NEXT: [[X5:%.*]] = ptrtoint ptr [[X:%.*]] to i64
+; CHECK-NEXT: [[Y6:%.*]] = ptrtoint ptr [[Y:%.*]] to i64
+; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[X5]], [[Y6]]
; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], 32
; CHECK-NEXT: br i1 [[DIFF_CHECK]], label [[FOR_BODY:%.*]], label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ], [ 0, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[INDEX]] to i64
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds double, double* [[Y]], i64 [[TMP0]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast double* [[TMP1]] to <2 x double>*
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x double>, <2 x double>* [[TMP2]], align 8
-; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, double* [[TMP1]], i64 2
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast double* [[TMP3]] to <2 x double>*
-; CHECK-NEXT: [[WIDE_LOAD11:%.*]] = load <2 x double>, <2 x double>* [[TMP4]]
-; CHECK-NEXT: [[TMP5:%.*]] = fcmp olt <2 x double> [[WIDE_LOAD]], zeroinitializer
-; CHECK-NEXT: [[TMP6:%.*]] = fcmp olt <2 x double> [[WIDE_LOAD11]], zeroinitializer
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp ogt <2 x double> [[WIDE_LOAD]], <double 6.000000e+00, double 6.000000e+00>
-; CHECK-NEXT: [[TMP8:%.*]] = fcmp ogt <2 x double> [[WIDE_LOAD11]], <double 6.000000e+00, double 6.000000e+00>
-; CHECK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP7]], <2 x double> <double 6.000000e+00, double 6.000000e+00>, <2 x double> [[WIDE_LOAD]]
-; CHECK-NEXT: [[TMP10:%.*]] = select <2 x i1> [[TMP8]], <2 x double> <double 6.000000e+00, double 6.000000e+00>, <2 x double> [[WIDE_LOAD11]]
+; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[INDEX]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds double, ptr [[Y]], i64 [[TMP1]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x double>, ptr [[TMP2]], align 8
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, ptr [[TMP2]], i64 2
+; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <2 x double>, ptr [[TMP3]], align 8
+; CHECK-NEXT: [[TMP4:%.*]] = fcmp olt <2 x double> [[WIDE_LOAD]], zeroinitializer
+; CHECK-NEXT: [[TMP5:%.*]] = fcmp olt <2 x double> [[WIDE_LOAD7]], zeroinitializer
+; CHECK-NEXT: [[TMP6:%.*]] = fcmp ogt <2 x double> [[WIDE_LOAD]], <double 6.000000e+00, double 6.000000e+00>
+; CHECK-NEXT: [[TMP7:%.*]] = fcmp ogt <2 x double> [[WIDE_LOAD7]], <double 6.000000e+00, double 6.000000e+00>
+; CHECK-NEXT: [[TMP8:%.*]] = select <2 x i1> [[TMP6]], <2 x double> <double 6.000000e+00, double 6.000000e+00>, <2 x double> [[WIDE_LOAD]]
+; CHECK-NEXT: [[TMP9:%.*]] = select <2 x i1> [[TMP7]], <2 x double> <double 6.000000e+00, double 6.000000e+00>, <2 x double> [[WIDE_LOAD7]]
+; CHECK-NEXT: [[TMP10:%.*]] = select <2 x i1> [[TMP4]], <2 x double> zeroinitializer, <2 x double> [[TMP8]]
; CHECK-NEXT: [[TMP11:%.*]] = select <2 x i1> [[TMP5]], <2 x double> zeroinitializer, <2 x double> [[TMP9]]
-; CHECK-NEXT: [[TMP12:%.*]] = select <2 x i1> [[TMP6]], <2 x double> zeroinitializer, <2 x double> [[TMP10]]
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds double, double* [[X]], i64 [[TMP0]]
-; CHECK-NEXT: [[TMP14:%.*]] = bitcast double* [[TMP13]] to <2 x double>*
-; CHECK-NEXT: store <2 x double> [[TMP11]], <2 x double>* [[TMP14]], align 8
-; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds double, double* [[TMP13]], i64 2
-; CHECK-NEXT: [[TMP16:%.*]] = bitcast double* [[TMP15]] to <2 x double>*
-; CHECK-NEXT: store <2 x double> [[TMP12]], <2 x double>* [[TMP16]], align 8
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds double, ptr [[X]], i64 [[TMP1]]
+; CHECK-NEXT: store <2 x double> [[TMP10]], ptr [[TMP12]], align 8
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds double, ptr [[TMP12]], i64 2
+; CHECK-NEXT: store <2 x double> [[TMP11]], ptr [[TMP13]], align 8
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
-; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i32 [[INDEX_NEXT]], 20000
-; CHECK-NEXT: br i1 [[TMP17]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[INDEX_NEXT]], 20000
+; CHECK-NEXT: br i1 [[TMP14]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: for.cond.cleanup:
; CHECK-NEXT: ret void
; CHECK: for.body:
-; CHECK-NEXT: [[I_05:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY]] ]
-; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[I_05]] to i64
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[Y]], i64 [[IDXPROM]]
-; CHECK-NEXT: [[TMP18:%.*]] = load double, double* [[ARRAYIDX]], align 8
-; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt double [[TMP18]], 0.000000e+00
-; CHECK-NEXT: [[CMP1_I:%.*]] = fcmp ogt double [[TMP18]], 6.000000e+00
-; CHECK-NEXT: [[DOTV_I:%.*]] = select i1 [[CMP1_I]], double 6.000000e+00, double [[TMP18]]
+; CHECK-NEXT: [[I_04:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY]] ]
+; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[I_04]] to i64
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[Y]], i64 [[IDXPROM]]
+; CHECK-NEXT: [[TMP15:%.*]] = load double, ptr [[ARRAYIDX]], align 8
+; CHECK-NEXT: [[CMP_I:%.*]] = fcmp olt double [[TMP15]], 0.000000e+00
+; CHECK-NEXT: [[CMP1_I:%.*]] = fcmp ogt double [[TMP15]], 6.000000e+00
+; CHECK-NEXT: [[DOTV_I:%.*]] = select i1 [[CMP1_I]], double 6.000000e+00, double [[TMP15]]
; CHECK-NEXT: [[RETVAL_0_I:%.*]] = select i1 [[CMP_I]], double 0.000000e+00, double [[DOTV_I]]
-; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[X]], i64 [[IDXPROM]]
-; CHECK-NEXT: store double [[RETVAL_0_I]], double* [[ARRAYIDX2]], align 8
-; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_05]], 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[I_05]], 19999
-; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_COND_CLEANUP]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[X]], i64 [[IDXPROM]]
+; CHECK-NEXT: store double [[RETVAL_0_I]], ptr [[ARRAYIDX2]], align 8
+; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_04]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[I_04]], 19999
+; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_COND_CLEANUP]], !llvm.loop [[LOOP2:![0-9]+]]
;
entry:
- %X.addr = alloca double*, align 8
- %Y.addr = alloca double*, align 8
+ %X.addr = alloca ptr, align 8
+ %Y.addr = alloca ptr, align 8
%i = alloca i32, align 4
- store double* %X, double** %X.addr, align 8
- store double* %Y, double** %Y.addr, align 8
- %0 = bitcast i32* %i to i8*
- call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #2
- store i32 0, i32* %i, align 4
+ store ptr %X, ptr %X.addr, align 8
+ store ptr %Y, ptr %Y.addr, align 8
+ call void @llvm.lifetime.start.p0(i64 4, ptr %i) #2
+ store i32 0, ptr %i, align 4
br label %for.cond
for.cond: ; preds = %for.inc, %entry
- %1 = load i32, i32* %i, align 4
- %cmp = icmp ult i32 %1, 20000
+ %0 = load i32, ptr %i, align 4
+ %cmp = icmp ult i32 %0, 20000
br i1 %cmp, label %for.body, label %for.cond.cleanup
for.cond.cleanup: ; preds = %for.cond
- %2 = bitcast i32* %i to i8*
- call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #2
+ call void @llvm.lifetime.end.p0(i64 4, ptr %i) #2
br label %for.end
for.body: ; preds = %for.cond
- %3 = load double*, double** %Y.addr, align 8
- %4 = load i32, i32* %i, align 4
- %idxprom = zext i32 %4 to i64
- %arrayidx = getelementptr inbounds double, double* %3, i64 %idxprom
- %5 = load double, double* %arrayidx, align 8
- %call = call double @clamp(double %5)
- %6 = load double*, double** %X.addr, align 8
- %7 = load i32, i32* %i, align 4
- %idxprom1 = zext i32 %7 to i64
- %arrayidx2 = getelementptr inbounds double, double* %6, i64 %idxprom1
- store double %call, double* %arrayidx2, align 8
+ %1 = load ptr, ptr %Y.addr, align 8
+ %2 = load i32, ptr %i, align 4
+ %idxprom = zext i32 %2 to i64
+ %arrayidx = getelementptr inbounds double, ptr %1, i64 %idxprom
+ %3 = load double, ptr %arrayidx, align 8
+ %call = call double @clamp(double %3)
+ %4 = load ptr, ptr %X.addr, align 8
+ %5 = load i32, ptr %i, align 4
+ %idxprom1 = zext i32 %5 to i64
+ %arrayidx2 = getelementptr inbounds double, ptr %4, i64 %idxprom1
+ store double %call, ptr %arrayidx2, align 8
br label %for.inc
for.inc: ; preds = %for.body
- %8 = load i32, i32* %i, align 4
- %inc = add i32 %8, 1
- store i32 %inc, i32* %i, align 4
+ %6 = load i32, ptr %i, align 4
+ %inc = add i32 %6, 1
+ store i32 %inc, ptr %i, align 4
br label %for.cond
for.end: ; preds = %for.cond.cleanup
@@ -136,21 +130,19 @@ for.end: ; preds = %for.cond.cleanup
; Test that requires sinking/hoisting of instructions for vectorization.
-define void @loop2(float* %A, float* %B, i32* %C, float %x) {
+define void @loop2(ptr %A, ptr %B, ptr %C, float %x) {
; CHECK-LABEL: @loop2(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr float, float* [[B:%.*]], i64 10000
-; CHECK-NEXT: [[SCEVGEP6:%.*]] = getelementptr i32, i32* [[C:%.*]], i64 10000
-; CHECK-NEXT: [[SCEVGEP9:%.*]] = getelementptr float, float* [[A:%.*]], i64 10000
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[SCEVGEP6]] to float*
-; CHECK-NEXT: [[BOUND0:%.*]] = icmp ugt float* [[TMP0]], [[B]]
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[SCEVGEP]] to i32*
-; CHECK-NEXT: [[BOUND1:%.*]] = icmp ugt i32* [[TMP1]], [[C]]
+; CHECK-NEXT: [[UGLYGEP:%.*]] = getelementptr i8, ptr [[B:%.*]], i64 40000
+; CHECK-NEXT: [[UGLYGEP2:%.*]] = getelementptr i8, ptr [[C:%.*]], i64 40000
+; CHECK-NEXT: [[UGLYGEP3:%.*]] = getelementptr i8, ptr [[A:%.*]], i64 40000
+; CHECK-NEXT: [[BOUND0:%.*]] = icmp ugt ptr [[UGLYGEP2]], [[B]]
+; CHECK-NEXT: [[BOUND1:%.*]] = icmp ugt ptr [[UGLYGEP]], [[C]]
; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
-; CHECK-NEXT: [[BOUND011:%.*]] = icmp ugt float* [[SCEVGEP9]], [[B]]
-; CHECK-NEXT: [[BOUND112:%.*]] = icmp ugt float* [[SCEVGEP]], [[A]]
-; CHECK-NEXT: [[FOUND_CONFLICT13:%.*]] = and i1 [[BOUND011]], [[BOUND112]]
-; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT13]]
+; CHECK-NEXT: [[BOUND04:%.*]] = icmp ugt ptr [[UGLYGEP3]], [[B]]
+; CHECK-NEXT: [[BOUND15:%.*]] = icmp ugt ptr [[UGLYGEP]], [[A]]
+; CHECK-NEXT: [[FOUND_CONFLICT6:%.*]] = and i1 [[BOUND04]], [[BOUND15]]
+; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[FOUND_CONFLICT]], [[FOUND_CONFLICT6]]
; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label [[LOOP_BODY:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i64 0
@@ -158,44 +150,40 @@ define void @loop2(float* %A, float* %B, i32* %C, float %x) {
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, i32* [[C]], i64 [[INDEX]]
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32* [[TMP2]] to <4 x i32>*
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP3]], align 4, !alias.scope !3
-; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD]], <i32 20, i32 20, i32 20, i32 20>
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[INDEX]]
-; CHECK-NEXT: [[TMP6:%.*]] = bitcast float* [[TMP5]] to <4 x float>*
-; CHECK-NEXT: [[WIDE_LOAD14:%.*]] = load <4 x float>, <4 x float>* [[TMP6]], align 4, !alias.scope !6
-; CHECK-NEXT: [[TMP7:%.*]] = fmul <4 x float> [[WIDE_LOAD14]], [[BROADCAST_SPLAT]]
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr float, float* [[B]], i64 [[INDEX]]
-; CHECK-NEXT: [[TMP9:%.*]] = bitcast float* [[TMP8]] to <4 x float>*
-; CHECK-NEXT: [[WIDE_LOAD15:%.*]] = load <4 x float>, <4 x float>* [[TMP9]], align 4, !alias.scope !8, !noalias !10
-; CHECK-NEXT: [[TMP10:%.*]] = select <4 x i1> [[TMP4]], <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, <4 x float> [[WIDE_LOAD15]]
-; CHECK-NEXT: [[PREDPHI:%.*]] = fadd <4 x float> [[TMP7]], [[TMP10]]
-; CHECK-NEXT: [[TMP11:%.*]] = bitcast float* [[TMP8]] to <4 x float>*
-; CHECK-NEXT: store <4 x float> [[PREDPHI]], <4 x float>* [[TMP11]], align 4, !alias.scope !8, !noalias !10
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[INDEX]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4, !alias.scope !3
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <4 x i32> [[WIDE_LOAD]], <i32 20, i32 20, i32 20, i32 20>
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDEX]]
+; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x float>, ptr [[TMP2]], align 4, !alias.scope !6
+; CHECK-NEXT: [[TMP3:%.*]] = fmul <4 x float> [[WIDE_LOAD7]], [[BROADCAST_SPLAT]]
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr float, ptr [[B]], i64 [[INDEX]]
+; CHECK-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x float>, ptr [[TMP4]], align 4, !alias.scope !8, !noalias !10
+; CHECK-NEXT: [[TMP5:%.*]] = select <4 x i1> [[TMP1]], <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, <4 x float> [[WIDE_LOAD8]]
+; CHECK-NEXT: [[PREDPHI:%.*]] = fadd <4 x float> [[TMP3]], [[TMP5]]
+; CHECK-NEXT: store <4 x float> [[PREDPHI]], ptr [[TMP4]], align 4, !alias.scope !8, !noalias !10
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
-; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 10000
-; CHECK-NEXT: br i1 [[TMP12]], label [[EXIT:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
+; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 10000
+; CHECK-NEXT: br i1 [[TMP6]], label [[EXIT:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
; CHECK: loop.body:
; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[C_GEP:%.*]] = getelementptr inbounds i32, i32* [[C]], i64 [[IV1]]
-; CHECK-NEXT: [[C_LV:%.*]] = load i32, i32* [[C_GEP]], align 4
+; CHECK-NEXT: [[C_GEP:%.*]] = getelementptr inbounds i32, ptr [[C]], i64 [[IV1]]
+; CHECK-NEXT: [[C_LV:%.*]] = load i32, ptr [[C_GEP]], align 4
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[C_LV]], 20
-; CHECK-NEXT: [[A_GEP_0:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[IV1]]
-; CHECK-NEXT: [[A_LV_0:%.*]] = load float, float* [[A_GEP_0]], align 4
+; CHECK-NEXT: [[A_GEP_0:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV1]]
+; CHECK-NEXT: [[A_LV_0:%.*]] = load float, ptr [[A_GEP_0]], align 4
; CHECK-NEXT: [[MUL2_I81_I:%.*]] = fmul float [[A_LV_0]], [[X]]
-; CHECK-NEXT: [[B_GEP_0:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[IV1]]
+; CHECK-NEXT: [[B_GEP_0:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV1]]
; CHECK-NEXT: br i1 [[CMP]], label [[LOOP_LATCH]], label [[ELSE:%.*]]
; CHECK: else:
-; CHECK-NEXT: [[B_LV:%.*]] = load float, float* [[B_GEP_0]], align 4
+; CHECK-NEXT: [[B_LV:%.*]] = load float, ptr [[B_GEP_0]], align 4
; CHECK-NEXT: [[ADD:%.*]] = fadd float [[MUL2_I81_I]], [[B_LV]]
; CHECK-NEXT: br label [[LOOP_LATCH]]
; CHECK: loop.latch:
; CHECK-NEXT: [[ADD_SINK:%.*]] = phi float [ [[ADD]], [[ELSE]] ], [ [[MUL2_I81_I]], [[LOOP_BODY]] ]
-; CHECK-NEXT: store float [[ADD_SINK]], float* [[B_GEP_0]], align 4
+; CHECK-NEXT: store float [[ADD_SINK]], ptr [[B_GEP_0]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1
; CHECK-NEXT: [[CMP_0:%.*]] = icmp ult i64 [[IV1]], 9999
-; CHECK-NEXT: br i1 [[CMP_0]], label [[LOOP_BODY]], label [[EXIT]], !llvm.loop [[LOOP17:![0-9]+]]
+; CHECK-NEXT: br i1 [[CMP_0]], label [[LOOP_BODY]], label [[EXIT]], !llvm.loop [[LOOP12:![0-9]+]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
@@ -208,27 +196,27 @@ loop.header:
br i1 %cmp.0, label %loop.body, label %exit
loop.body:
- %C.gep = getelementptr inbounds i32, i32* %C, i64 %iv
- %C.lv = load i32, i32* %C.gep
+ %C.gep = getelementptr inbounds i32, ptr %C, i64 %iv
+ %C.lv = load i32, ptr %C.gep
%cmp = icmp eq i32 %C.lv, 20
br i1 %cmp, label %then, label %else
then:
- %A.gep.0 = getelementptr inbounds float, float* %A, i64 %iv
- %A.lv.0 = load float, float* %A.gep.0, align 4
+ %A.gep.0 = getelementptr inbounds float, ptr %A, i64 %iv
+ %A.lv.0 = load float, ptr %A.gep.0, align 4
%mul2.i81.i = fmul float %A.lv.0, %x
- %B.gep.0 = getelementptr inbounds float, float* %B, i64 %iv
- store float %mul2.i81.i, float* %B.gep.0, align 4
+ %B.gep.0 = getelementptr inbounds float, ptr %B, i64 %iv
+ store float %mul2.i81.i, ptr %B.gep.0, align 4
br label %loop.latch
else:
- %A.gep.1 = getelementptr inbounds float, float* %A, i64 %iv
- %A.lv.1 = load float, float* %A.gep.1, align 4
+ %A.gep.1 = getelementptr inbounds float, ptr %A, i64 %iv
+ %A.lv.1 = load float, ptr %A.gep.1, align 4
%mul2 = fmul float %A.lv.1, %x
- %B.gep.1 = getelementptr inbounds float, float* %B, i64 %iv
- %B.lv = load float, float* %B.gep.1, align 4
+ %B.gep.1 = getelementptr inbounds float, ptr %B, i64 %iv
+ %B.lv = load float, ptr %B.gep.1, align 4
%add = fadd float %mul2, %B.lv
- store float %add, float* %B.gep.1, align 4
+ store float %add, ptr %B.gep.1, align 4
br label %loop.latch
loop.latch:
@@ -239,6 +227,6 @@ exit:
ret void
}
-declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
-declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/loopflatten.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/loopflatten.ll
index 5ef5bb185ab02..2150026ab5e0d 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/loopflatten.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/loopflatten.ll
@@ -4,7 +4,7 @@
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
-define dso_local void @_Z3fooPiii(i32* %A, i32 %N, i32 %M) #0 {
+define dso_local void @_Z3fooPiii(ptr %A, i32 %N, i32 %M) #0 {
; CHECK-LABEL: @_Z3fooPiii(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[N:%.*]], 0
@@ -18,8 +18,8 @@ define dso_local void @_Z3fooPiii(i32* %A, i32 %N, i32 %M) #0 {
; CHECK-NEXT: br label [[FOR_COND1_PREHEADER_US:%.*]]
; CHECK: for.cond1.preheader.us:
; CHECK-NEXT: [[INDVAR6:%.*]] = phi i64 [ [[INDVAR_NEXT7:%.*]], [[FOR_COND1_PREHEADER_US]] ], [ 0, [[FOR_COND1_PREHEADER_LR_PH_SPLIT_US]] ]
-; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDVAR6]]
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX_US]], align 4
+; CHECK-NEXT: [[ARRAYIDX_US:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[INDVAR6]]
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX_US]], align 4
; CHECK-NEXT: tail call void @_Z1fi(i32 [[TMP2]])
; CHECK-NEXT: [[INDVAR_NEXT7]] = add nuw nsw i64 [[INDVAR6]], 1
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVAR_NEXT7]], [[FLATTEN_TRIPCOUNT]]
@@ -54,8 +54,8 @@ for.body4:
%mul = mul nsw i32 %i.0, %M
%add = add nsw i32 %mul, %j.0
%idxprom = sext i32 %add to i64
- %arrayidx = getelementptr inbounds i32, i32* %A, i64 %idxprom
- %0 = load i32, i32* %arrayidx, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %A, i64 %idxprom
+ %0 = load i32, ptr %arrayidx, align 4
call void @_Z1fi(i32 %0)
%inc = add nsw i32 %j.0, 1
br label %for.cond1
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
index f56c4e29f1421..c99a806bbd2f8 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/matrix-extract-insert.ll
@@ -3,7 +3,7 @@
target triple = "arm64-apple-ios"
-define void @matrix_extract_insert_scalar(i32 %i, i32 %k, i32 %j, [225 x double]* nonnull align 8 dereferenceable(1800) %A, [225 x double]* nonnull align 8 dereferenceable(1800) %B) #0 {
+define void @matrix_extract_insert_scalar(i32 %i, i32 %k, i32 %j, ptr nonnull align 8 dereferenceable(1800) %A, ptr nonnull align 8 dereferenceable(1800) %B) #0 {
; CHECK-LABEL: @matrix_extract_insert_scalar(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CONV:%.*]] = zext i32 [[K:%.*]] to i64
@@ -12,105 +12,98 @@ define void @matrix_extract_insert_scalar(i32 %i, i32 %k, i32 %j, [225 x double]
; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[TMP0]], [[CONV]]
; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i64 [[TMP1]], 225
; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP2]])
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast [225 x double]* [[A:%.*]] to <225 x double>*
-; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP3]], i64 0, i64 [[TMP1]]
-; CHECK-NEXT: [[MATRIXEXT:%.*]] = load double, double* [[TMP4]], align 8
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds <225 x double>, ptr [[A:%.*]], i64 0, i64 [[TMP1]]
+; CHECK-NEXT: [[MATRIXEXT:%.*]] = load double, ptr [[TMP4]], align 8
; CHECK-NEXT: [[CONV2:%.*]] = zext i32 [[I:%.*]] to i64
; CHECK-NEXT: [[TMP5:%.*]] = add nuw nsw i64 [[TMP0]], [[CONV2]]
; CHECK-NEXT: [[TMP6:%.*]] = icmp ult i64 [[TMP5]], 225
; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP6]])
-; CHECK-NEXT: [[TMP7:%.*]] = bitcast [225 x double]* [[B:%.*]] to <225 x double>*
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP7]], i64 0, i64 [[TMP5]]
-; CHECK-NEXT: [[MATRIXEXT4:%.*]] = load double, double* [[TMP8]], align 8
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds <225 x double>, ptr [[B:%.*]], i64 0, i64 [[TMP5]]
+; CHECK-NEXT: [[MATRIXEXT4:%.*]] = load double, ptr [[TMP8]], align 8
; CHECK-NEXT: [[MUL:%.*]] = fmul double [[MATRIXEXT]], [[MATRIXEXT4]]
-; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP7]], i64 0, i64 [[TMP1]]
-; CHECK-NEXT: [[MATRIXEXT7:%.*]] = load double, double* [[TMP9]], align 8
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds <225 x double>, ptr [[B]], i64 0, i64 [[TMP1]]
+; CHECK-NEXT: [[MATRIXEXT7:%.*]] = load double, ptr [[TMP9]], align 8
; CHECK-NEXT: [[SUB:%.*]] = fsub double [[MATRIXEXT7]], [[MUL]]
-; CHECK-NEXT: store double [[SUB]], double* [[TMP9]], align 8
+; CHECK-NEXT: store double [[SUB]], ptr [[TMP9]], align 8
; CHECK-NEXT: ret void
;
entry:
%i.addr = alloca i32, align 4
%k.addr = alloca i32, align 4
%j.addr = alloca i32, align 4
- %A.addr = alloca [225 x double]*, align 8
- %B.addr = alloca [225 x double]*, align 8
- store i32 %i, i32* %i.addr, align 4
- store i32 %k, i32* %k.addr, align 4
- store i32 %j, i32* %j.addr, align 4
- store [225 x double]* %A, [225 x double]** %A.addr, align 8
- store [225 x double]* %B, [225 x double]** %B.addr, align 8
- %0 = load i32, i32* %k.addr, align 4
+ %A.addr = alloca ptr, align 8
+ %B.addr = alloca ptr, align 8
+ store i32 %i, ptr %i.addr, align 4
+ store i32 %k, ptr %k.addr, align 4
+ store i32 %j, ptr %j.addr, align 4
+ store ptr %A, ptr %A.addr, align 8
+ store ptr %B, ptr %B.addr, align 8
+ %0 = load i32, ptr %k.addr, align 4
%conv = zext i32 %0 to i64
- %1 = load i32, i32* %j.addr, align 4
+ %1 = load i32, ptr %j.addr, align 4
%conv1 = zext i32 %1 to i64
%2 = mul i64 %conv1, 15
%3 = add i64 %2, %conv
%4 = icmp ult i64 %3, 225
call void @llvm.assume(i1 %4)
- %5 = load [225 x double]*, [225 x double]** %A.addr, align 8
- %6 = bitcast [225 x double]* %5 to <225 x double>*
- %7 = load <225 x double>, <225 x double>* %6, align 8
- %matrixext = extractelement <225 x double> %7, i64 %3
- %8 = load i32, i32* %i.addr, align 4
- %conv2 = zext i32 %8 to i64
- %9 = load i32, i32* %j.addr, align 4
- %conv3 = zext i32 %9 to i64
- %10 = mul i64 %conv3, 15
- %11 = add i64 %10, %conv2
- %12 = icmp ult i64 %11, 225
- call void @llvm.assume(i1 %12)
- %13 = load [225 x double]*, [225 x double]** %B.addr, align 8
- %14 = bitcast [225 x double]* %13 to <225 x double>*
- %15 = load <225 x double>, <225 x double>* %14, align 8
- %matrixext4 = extractelement <225 x double> %15, i64 %11
+ %5 = load ptr, ptr %A.addr, align 8
+ %6 = load <225 x double>, ptr %5, align 8
+ %matrixext = extractelement <225 x double> %6, i64 %3
+ %7 = load i32, ptr %i.addr, align 4
+ %conv2 = zext i32 %7 to i64
+ %8 = load i32, ptr %j.addr, align 4
+ %conv3 = zext i32 %8 to i64
+ %9 = mul i64 %conv3, 15
+ %10 = add i64 %9, %conv2
+ %11 = icmp ult i64 %10, 225
+ call void @llvm.assume(i1 %11)
+ %12 = load ptr, ptr %B.addr, align 8
+ %13 = load <225 x double>, ptr %12, align 8
+ %matrixext4 = extractelement <225 x double> %13, i64 %10
%mul = fmul double %matrixext, %matrixext4
- %16 = load [225 x double]*, [225 x double]** %B.addr, align 8
- %17 = load i32, i32* %k.addr, align 4
- %conv5 = zext i32 %17 to i64
- %18 = load i32, i32* %j.addr, align 4
- %conv6 = zext i32 %18 to i64
- %19 = mul i64 %conv6, 15
- %20 = add i64 %19, %conv5
- %21 = bitcast [225 x double]* %16 to <225 x double>*
- %22 = icmp ult i64 %20, 225
- call void @llvm.assume(i1 %22)
- %23 = load <225 x double>, <225 x double>* %21, align 8
- %matrixext7 = extractelement <225 x double> %23, i64 %20
+ %14 = load ptr, ptr %B.addr, align 8
+ %15 = load i32, ptr %k.addr, align 4
+ %conv5 = zext i32 %15 to i64
+ %16 = load i32, ptr %j.addr, align 4
+ %conv6 = zext i32 %16 to i64
+ %17 = mul i64 %conv6, 15
+ %18 = add i64 %17, %conv5
+ %19 = icmp ult i64 %18, 225
+ call void @llvm.assume(i1 %19)
+ %20 = load <225 x double>, ptr %14, align 8
+ %matrixext7 = extractelement <225 x double> %20, i64 %18
%sub = fsub double %matrixext7, %mul
- %24 = icmp ult i64 %20, 225
- call void @llvm.assume(i1 %24)
- %25 = load <225 x double>, <225 x double>* %21, align 8
- %matins = insertelement <225 x double> %25, double %sub, i64 %20
- store <225 x double> %matins, <225 x double>* %21, align 8
+ %21 = icmp ult i64 %18, 225
+ call void @llvm.assume(i1 %21)
+ %22 = load <225 x double>, ptr %14, align 8
+ %matins = insertelement <225 x double> %22, double %sub, i64 %18
+ store <225 x double> %matins, ptr %14, align 8
ret void
}
-define void @matrix_extract_insert_loop(i32 %i, [225 x double]* nonnull align 8 dereferenceable(1800) %A, [225 x double]* nonnull align 8 dereferenceable(1800) %B) {
+define void @matrix_extract_insert_loop(i32 %i, ptr nonnull align 8 dereferenceable(1800) %A, ptr nonnull align 8 dereferenceable(1800) %B) {
; CHECK-LABEL: @matrix_extract_insert_loop(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP212_NOT:%.*]] = icmp eq i32 [[I:%.*]], 0
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast [225 x double]* [[A:%.*]] to <225 x double>*
; CHECK-NEXT: [[CONV6:%.*]] = zext i32 [[I]] to i64
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast [225 x double]* [[B:%.*]] to <225 x double>*
; CHECK-NEXT: br i1 [[CMP212_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER_US:%.*]]
; CHECK: for.cond1.preheader.us:
; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[I]], 225
; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP2]])
-; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP1]], i64 0, i64 [[CONV6]]
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds <225 x double>, ptr [[B:%.*]], i64 0, i64 [[CONV6]]
; CHECK-NEXT: br label [[FOR_BODY4_US:%.*]]
; CHECK: for.body4.us:
; CHECK-NEXT: [[K_013_US:%.*]] = phi i32 [ 0, [[FOR_COND1_PREHEADER_US]] ], [ [[INC_US:%.*]], [[FOR_BODY4_US]] ]
; CHECK-NEXT: [[CONV_US:%.*]] = zext i32 [[K_013_US]] to i64
; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[K_013_US]], 225
; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP4]])
-; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP0]], i64 0, i64 [[CONV_US]]
-; CHECK-NEXT: [[MATRIXEXT_US:%.*]] = load double, double* [[TMP5]], align 8
-; CHECK-NEXT: [[MATRIXEXT8_US:%.*]] = load double, double* [[TMP3]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds <225 x double>, ptr [[A:%.*]], i64 0, i64 [[CONV_US]]
+; CHECK-NEXT: [[MATRIXEXT_US:%.*]] = load double, ptr [[TMP5]], align 8
+; CHECK-NEXT: [[MATRIXEXT8_US:%.*]] = load double, ptr [[TMP3]], align 8
; CHECK-NEXT: [[MUL_US:%.*]] = fmul double [[MATRIXEXT_US]], [[MATRIXEXT8_US]]
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP1]], i64 0, i64 [[CONV_US]]
-; CHECK-NEXT: [[MATRIXEXT11_US:%.*]] = load double, double* [[TMP6]], align 8
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds <225 x double>, ptr [[B]], i64 0, i64 [[CONV_US]]
+; CHECK-NEXT: [[MATRIXEXT11_US:%.*]] = load double, ptr [[TMP6]], align 8
; CHECK-NEXT: [[SUB_US:%.*]] = fsub double [[MATRIXEXT11_US]], [[MUL_US]]
-; CHECK-NEXT: store double [[SUB_US]], double* [[TMP6]], align 8
+; CHECK-NEXT: store double [[SUB_US]], ptr [[TMP6]], align 8
; CHECK-NEXT: [[INC_US]] = add nuw nsw i32 [[K_013_US]], 1
; CHECK-NEXT: [[CMP2_US:%.*]] = icmp ult i32 [[INC_US]], [[I]]
; CHECK-NEXT: br i1 [[CMP2_US]], label [[FOR_BODY4_US]], label [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US:%.*]]
@@ -118,7 +111,7 @@ define void @matrix_extract_insert_loop(i32 %i, [225 x double]* nonnull align 8
; CHECK-NEXT: [[TMP7:%.*]] = add nuw nsw i64 [[CONV6]], 15
; CHECK-NEXT: [[TMP8:%.*]] = icmp ult i32 [[I]], 210
; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP8]])
-; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP1]], i64 0, i64 [[TMP7]]
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds <225 x double>, ptr [[B]], i64 0, i64 [[TMP7]]
; CHECK-NEXT: br label [[FOR_BODY4_US_1:%.*]]
; CHECK: for.body4.us.1:
; CHECK-NEXT: [[K_013_US_1:%.*]] = phi i32 [ 0, [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US]] ], [ [[INC_US_1:%.*]], [[FOR_BODY4_US_1]] ]
@@ -126,14 +119,14 @@ define void @matrix_extract_insert_loop(i32 %i, [225 x double]* nonnull align 8
; CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[NARROW]] to i64
; CHECK-NEXT: [[TMP11:%.*]] = icmp ult i32 [[K_013_US_1]], 210
; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP11]])
-; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP0]], i64 0, i64 [[TMP10]]
-; CHECK-NEXT: [[MATRIXEXT_US_1:%.*]] = load double, double* [[TMP12]], align 8
-; CHECK-NEXT: [[MATRIXEXT8_US_1:%.*]] = load double, double* [[TMP9]], align 8
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds <225 x double>, ptr [[A]], i64 0, i64 [[TMP10]]
+; CHECK-NEXT: [[MATRIXEXT_US_1:%.*]] = load double, ptr [[TMP12]], align 8
+; CHECK-NEXT: [[MATRIXEXT8_US_1:%.*]] = load double, ptr [[TMP9]], align 8
; CHECK-NEXT: [[MUL_US_1:%.*]] = fmul double [[MATRIXEXT_US_1]], [[MATRIXEXT8_US_1]]
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP1]], i64 0, i64 [[TMP10]]
-; CHECK-NEXT: [[MATRIXEXT11_US_1:%.*]] = load double, double* [[TMP13]], align 8
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds <225 x double>, ptr [[B]], i64 0, i64 [[TMP10]]
+; CHECK-NEXT: [[MATRIXEXT11_US_1:%.*]] = load double, ptr [[TMP13]], align 8
; CHECK-NEXT: [[SUB_US_1:%.*]] = fsub double [[MATRIXEXT11_US_1]], [[MUL_US_1]]
-; CHECK-NEXT: store double [[SUB_US_1]], double* [[TMP13]], align 8
+; CHECK-NEXT: store double [[SUB_US_1]], ptr [[TMP13]], align 8
; CHECK-NEXT: [[INC_US_1]] = add nuw nsw i32 [[K_013_US_1]], 1
; CHECK-NEXT: [[CMP2_US_1:%.*]] = icmp ult i32 [[INC_US_1]], [[I]]
; CHECK-NEXT: br i1 [[CMP2_US_1]], label [[FOR_BODY4_US_1]], label [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US_1:%.*]]
@@ -141,7 +134,7 @@ define void @matrix_extract_insert_loop(i32 %i, [225 x double]* nonnull align 8
; CHECK-NEXT: [[TMP14:%.*]] = add nuw nsw i64 [[CONV6]], 30
; CHECK-NEXT: [[TMP15:%.*]] = icmp ult i32 [[I]], 195
; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP15]])
-; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP1]], i64 0, i64 [[TMP14]]
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds <225 x double>, ptr [[B]], i64 0, i64 [[TMP14]]
; CHECK-NEXT: br label [[FOR_BODY4_US_2:%.*]]
; CHECK: for.body4.us.2:
; CHECK-NEXT: [[K_013_US_2:%.*]] = phi i32 [ 0, [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US_1]] ], [ [[INC_US_2:%.*]], [[FOR_BODY4_US_2]] ]
@@ -149,14 +142,14 @@ define void @matrix_extract_insert_loop(i32 %i, [225 x double]* nonnull align 8
; CHECK-NEXT: [[TMP17:%.*]] = zext i32 [[NARROW17]] to i64
; CHECK-NEXT: [[TMP18:%.*]] = icmp ult i32 [[K_013_US_2]], 195
; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP18]])
-; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP0]], i64 0, i64 [[TMP17]]
-; CHECK-NEXT: [[MATRIXEXT_US_2:%.*]] = load double, double* [[TMP19]], align 8
-; CHECK-NEXT: [[MATRIXEXT8_US_2:%.*]] = load double, double* [[TMP16]], align 8
+; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds <225 x double>, ptr [[A]], i64 0, i64 [[TMP17]]
+; CHECK-NEXT: [[MATRIXEXT_US_2:%.*]] = load double, ptr [[TMP19]], align 8
+; CHECK-NEXT: [[MATRIXEXT8_US_2:%.*]] = load double, ptr [[TMP16]], align 8
; CHECK-NEXT: [[MUL_US_2:%.*]] = fmul double [[MATRIXEXT_US_2]], [[MATRIXEXT8_US_2]]
-; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP1]], i64 0, i64 [[TMP17]]
-; CHECK-NEXT: [[MATRIXEXT11_US_2:%.*]] = load double, double* [[TMP20]], align 8
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds <225 x double>, ptr [[B]], i64 0, i64 [[TMP17]]
+; CHECK-NEXT: [[MATRIXEXT11_US_2:%.*]] = load double, ptr [[TMP20]], align 8
; CHECK-NEXT: [[SUB_US_2:%.*]] = fsub double [[MATRIXEXT11_US_2]], [[MUL_US_2]]
-; CHECK-NEXT: store double [[SUB_US_2]], double* [[TMP20]], align 8
+; CHECK-NEXT: store double [[SUB_US_2]], ptr [[TMP20]], align 8
; CHECK-NEXT: [[INC_US_2]] = add nuw nsw i32 [[K_013_US_2]], 1
; CHECK-NEXT: [[CMP2_US_2:%.*]] = icmp ult i32 [[INC_US_2]], [[I]]
; CHECK-NEXT: br i1 [[CMP2_US_2]], label [[FOR_BODY4_US_2]], label [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US_2:%.*]]
@@ -164,7 +157,7 @@ define void @matrix_extract_insert_loop(i32 %i, [225 x double]* nonnull align 8
; CHECK-NEXT: [[TMP21:%.*]] = add nuw nsw i64 [[CONV6]], 45
; CHECK-NEXT: [[TMP22:%.*]] = icmp ult i32 [[I]], 180
; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP22]])
-; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP1]], i64 0, i64 [[TMP21]]
+; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds <225 x double>, ptr [[B]], i64 0, i64 [[TMP21]]
; CHECK-NEXT: br label [[FOR_BODY4_US_3:%.*]]
; CHECK: for.body4.us.3:
; CHECK-NEXT: [[K_013_US_3:%.*]] = phi i32 [ 0, [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US_2]] ], [ [[INC_US_3:%.*]], [[FOR_BODY4_US_3]] ]
@@ -172,14 +165,14 @@ define void @matrix_extract_insert_loop(i32 %i, [225 x double]* nonnull align 8
; CHECK-NEXT: [[TMP24:%.*]] = zext i32 [[NARROW18]] to i64
; CHECK-NEXT: [[TMP25:%.*]] = icmp ult i32 [[K_013_US_3]], 180
; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP25]])
-; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP0]], i64 0, i64 [[TMP24]]
-; CHECK-NEXT: [[MATRIXEXT_US_3:%.*]] = load double, double* [[TMP26]], align 8
-; CHECK-NEXT: [[MATRIXEXT8_US_3:%.*]] = load double, double* [[TMP23]], align 8
+; CHECK-NEXT: [[TMP26:%.*]] = getelementptr inbounds <225 x double>, ptr [[A]], i64 0, i64 [[TMP24]]
+; CHECK-NEXT: [[MATRIXEXT_US_3:%.*]] = load double, ptr [[TMP26]], align 8
+; CHECK-NEXT: [[MATRIXEXT8_US_3:%.*]] = load double, ptr [[TMP23]], align 8
; CHECK-NEXT: [[MUL_US_3:%.*]] = fmul double [[MATRIXEXT_US_3]], [[MATRIXEXT8_US_3]]
-; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds <225 x double>, <225 x double>* [[TMP1]], i64 0, i64 [[TMP24]]
-; CHECK-NEXT: [[MATRIXEXT11_US_3:%.*]] = load double, double* [[TMP27]], align 8
+; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds <225 x double>, ptr [[B]], i64 0, i64 [[TMP24]]
+; CHECK-NEXT: [[MATRIXEXT11_US_3:%.*]] = load double, ptr [[TMP27]], align 8
; CHECK-NEXT: [[SUB_US_3:%.*]] = fsub double [[MATRIXEXT11_US_3]], [[MUL_US_3]]
-; CHECK-NEXT: store double [[SUB_US_3]], double* [[TMP27]], align 8
+; CHECK-NEXT: store double [[SUB_US_3]], ptr [[TMP27]], align 8
; CHECK-NEXT: [[INC_US_3]] = add nuw nsw i32 [[K_013_US_3]], 1
; CHECK-NEXT: [[CMP2_US_3:%.*]] = icmp ult i32 [[INC_US_3]], [[I]]
; CHECK-NEXT: br i1 [[CMP2_US_3]], label [[FOR_BODY4_US_3]], label [[FOR_COND_CLEANUP]]
@@ -188,107 +181,100 @@ define void @matrix_extract_insert_loop(i32 %i, [225 x double]* nonnull align 8
;
entry:
%i.addr = alloca i32, align 4
- %A.addr = alloca [225 x double]*, align 8
- %B.addr = alloca [225 x double]*, align 8
+ %A.addr = alloca ptr, align 8
+ %B.addr = alloca ptr, align 8
%j = alloca i32, align 4
%cleanup.dest.slot = alloca i32, align 4
%k = alloca i32, align 4
- store i32 %i, i32* %i.addr, align 4
- store [225 x double]* %A, [225 x double]** %A.addr, align 8
- store [225 x double]* %B, [225 x double]** %B.addr, align 8
- %0 = bitcast i32* %j to i8*
- call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #3
- store i32 0, i32* %j, align 4
+ store i32 %i, ptr %i.addr, align 4
+ store ptr %A, ptr %A.addr, align 8
+ store ptr %B, ptr %B.addr, align 8
+ call void @llvm.lifetime.start.p0(i64 4, ptr %j) #3
+ store i32 0, ptr %j, align 4
br label %for.cond
for.cond: ; preds = %for.inc12, %entry
- %1 = load i32, i32* %j, align 4
- %cmp = icmp ult i32 %1, 4
+ %0 = load i32, ptr %j, align 4
+ %cmp = icmp ult i32 %0, 4
br i1 %cmp, label %for.body, label %for.cond.cleanup
for.cond.cleanup: ; preds = %for.cond
- store i32 2, i32* %cleanup.dest.slot, align 4
- %2 = bitcast i32* %j to i8*
- call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #3
+ store i32 2, ptr %cleanup.dest.slot, align 4
+ call void @llvm.lifetime.end.p0(i64 4, ptr %j) #3
br label %for.end14
for.body: ; preds = %for.cond
- %3 = bitcast i32* %k to i8*
- call void @llvm.lifetime.start.p0i8(i64 4, i8* %3) #3
- store i32 0, i32* %k, align 4
+ call void @llvm.lifetime.start.p0(i64 4, ptr %k) #3
+ store i32 0, ptr %k, align 4
br label %for.cond1
for.cond1: ; preds = %for.inc, %for.body
- %4 = load i32, i32* %k, align 4
- %5 = load i32, i32* %i.addr, align 4
- %cmp2 = icmp ult i32 %4, %5
+ %1 = load i32, ptr %k, align 4
+ %2 = load i32, ptr %i.addr, align 4
+ %cmp2 = icmp ult i32 %1, %2
br i1 %cmp2, label %for.body4, label %for.cond.cleanup3
for.cond.cleanup3: ; preds = %for.cond1
- store i32 5, i32* %cleanup.dest.slot, align 4
- %6 = bitcast i32* %k to i8*
- call void @llvm.lifetime.end.p0i8(i64 4, i8* %6) #3
+ store i32 5, ptr %cleanup.dest.slot, align 4
+ call void @llvm.lifetime.end.p0(i64 4, ptr %k) #3
br label %for.end
for.body4: ; preds = %for.cond1
- %7 = load i32, i32* %k, align 4
- %conv = zext i32 %7 to i64
- %8 = load i32, i32* %j, align 4
- %conv5 = zext i32 %8 to i64
- %9 = mul i64 %conv5, 15
- %10 = add i64 %9, %conv
- %11 = icmp ult i64 %10, 225
- call void @llvm.assume(i1 %11)
- %12 = load [225 x double]*, [225 x double]** %A.addr, align 8
- %13 = bitcast [225 x double]* %12 to <225 x double>*
- %14 = load <225 x double>, <225 x double>* %13, align 8
- %matrixext = extractelement <225 x double> %14, i64 %10
- %15 = load i32, i32* %i.addr, align 4
- %conv6 = zext i32 %15 to i64
- %16 = load i32, i32* %j, align 4
- %conv7 = zext i32 %16 to i64
- %17 = mul i64 %conv7, 15
- %18 = add i64 %17, %conv6
- %19 = icmp ult i64 %18, 225
- call void @llvm.assume(i1 %19)
- %20 = load [225 x double]*, [225 x double]** %B.addr, align 8
- %21 = bitcast [225 x double]* %20 to <225 x double>*
- %22 = load <225 x double>, <225 x double>* %21, align 8
- %matrixext8 = extractelement <225 x double> %22, i64 %18
+ %3 = load i32, ptr %k, align 4
+ %conv = zext i32 %3 to i64
+ %4 = load i32, ptr %j, align 4
+ %conv5 = zext i32 %4 to i64
+ %5 = mul i64 %conv5, 15
+ %6 = add i64 %5, %conv
+ %7 = icmp ult i64 %6, 225
+ call void @llvm.assume(i1 %7)
+ %8 = load ptr, ptr %A.addr, align 8
+ %9 = load <225 x double>, ptr %8, align 8
+ %matrixext = extractelement <225 x double> %9, i64 %6
+ %10 = load i32, ptr %i.addr, align 4
+ %conv6 = zext i32 %10 to i64
+ %11 = load i32, ptr %j, align 4
+ %conv7 = zext i32 %11 to i64
+ %12 = mul i64 %conv7, 15
+ %13 = add i64 %12, %conv6
+ %14 = icmp ult i64 %13, 225
+ call void @llvm.assume(i1 %14)
+ %15 = load ptr, ptr %B.addr, align 8
+ %16 = load <225 x double>, ptr %15, align 8
+ %matrixext8 = extractelement <225 x double> %16, i64 %13
%mul = fmul double %matrixext, %matrixext8
- %23 = load [225 x double]*, [225 x double]** %B.addr, align 8
- %24 = load i32, i32* %k, align 4
- %conv9 = zext i32 %24 to i64
- %25 = load i32, i32* %j, align 4
- %conv10 = zext i32 %25 to i64
- %26 = mul i64 %conv10, 15
- %27 = add i64 %26, %conv9
- %28 = bitcast [225 x double]* %23 to <225 x double>*
- %29 = icmp ult i64 %27, 225
- call void @llvm.assume(i1 %29)
- %30 = load <225 x double>, <225 x double>* %28, align 8
- %matrixext11 = extractelement <225 x double> %30, i64 %27
+ %17 = load ptr, ptr %B.addr, align 8
+ %18 = load i32, ptr %k, align 4
+ %conv9 = zext i32 %18 to i64
+ %19 = load i32, ptr %j, align 4
+ %conv10 = zext i32 %19 to i64
+ %20 = mul i64 %conv10, 15
+ %21 = add i64 %20, %conv9
+ %22 = icmp ult i64 %21, 225
+ call void @llvm.assume(i1 %22)
+ %23 = load <225 x double>, ptr %17, align 8
+ %matrixext11 = extractelement <225 x double> %23, i64 %21
%sub = fsub double %matrixext11, %mul
- %31 = icmp ult i64 %27, 225
- call void @llvm.assume(i1 %31)
- %32 = load <225 x double>, <225 x double>* %28, align 8
- %matins = insertelement <225 x double> %32, double %sub, i64 %27
- store <225 x double> %matins, <225 x double>* %28, align 8
+ %24 = icmp ult i64 %21, 225
+ call void @llvm.assume(i1 %24)
+ %25 = load <225 x double>, ptr %17, align 8
+ %matins = insertelement <225 x double> %25, double %sub, i64 %21
+ store <225 x double> %matins, ptr %17, align 8
br label %for.inc
for.inc: ; preds = %for.body4
- %33 = load i32, i32* %k, align 4
- %inc = add i32 %33, 1
- store i32 %inc, i32* %k, align 4
+ %26 = load i32, ptr %k, align 4
+ %inc = add i32 %26, 1
+ store i32 %inc, ptr %k, align 4
br label %for.cond1
for.end: ; preds = %for.cond.cleanup3
br label %for.inc12
for.inc12: ; preds = %for.end
- %34 = load i32, i32* %j, align 4
- %inc13 = add i32 %34, 1
- store i32 %inc13, i32* %j, align 4
+ %27 = load i32, ptr %j, align 4
+ %inc13 = add i32 %27, 1
+ store i32 %inc13, ptr %j, align 4
br label %for.cond
for.end14: ; preds = %for.cond.cleanup
@@ -296,13 +282,13 @@ for.end14: ; preds = %for.cond.cleanup
}
; Function Attrs: argmemonly nofree nosync nounwind willreturn
-declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1
; Function Attrs: inaccessiblememonly nofree nosync nounwind willreturn
declare void @llvm.assume(i1 noundef) #2
; Function Attrs: argmemonly nofree nosync nounwind willreturn
-declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1
; Function Attrs: nounwind ssp uwtable mustprogress
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/mul-ov.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/mul-ov.ll
index c348a5b0acdce..3f88ed5eaf3cd 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/mul-ov.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/mul-ov.ll
@@ -4,11 +4,11 @@
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-unknown"
-define i128 @__muloti4(i128 %0, i128 %1, i32* nonnull align 4 %2) {
+define i128 @__muloti4(i128 %0, i128 %1, ptr nonnull align 4 %2) {
; CHECK-LABEL: @__muloti4(
; CHECK-NEXT: Entry:
; CHECK-NEXT: [[DOTFR:%.*]] = freeze i128 [[TMP1:%.*]]
-; CHECK-NEXT: store i32 0, i32* [[TMP2:%.*]], align 4
+; CHECK-NEXT: store i32 0, ptr [[TMP2:%.*]], align 4
; CHECK-NEXT: [[MUL:%.*]] = tail call { i128, i1 } @llvm.smul.with.overflow.i128(i128 [[TMP0:%.*]], i128 [[DOTFR]])
; CHECK-NEXT: [[TMP3:%.*]] = icmp slt i128 [[TMP0]], 0
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i128 [[DOTFR]], -170141183460469231731687303715884105728
@@ -18,7 +18,7 @@ define i128 @__muloti4(i128 %0, i128 %1, i32* nonnull align 4 %2) {
; CHECK-NEXT: [[MUL_OV:%.*]] = extractvalue { i128, i1 } [[MUL]], 1
; CHECK-NEXT: br i1 [[MUL_OV]], label [[THEN7]], label [[BLOCK9:%.*]]
; CHECK: Then7:
-; CHECK-NEXT: store i32 1, i32* [[TMP2]], align 4
+; CHECK-NEXT: store i32 1, ptr [[TMP2]], align 4
; CHECK-NEXT: br label [[BLOCK9]]
; CHECK: Block9:
; CHECK-NEXT: [[MUL_VAL:%.*]] = extractvalue { i128, i1 } [[MUL]], 0
@@ -27,9 +27,9 @@ define i128 @__muloti4(i128 %0, i128 %1, i32* nonnull align 4 %2) {
Entry:
%3 = alloca i128, align 16
%4 = alloca i128, align 16
- store i32 0, i32* %2, align 4
+ store i32 0, ptr %2, align 4
%5 = mul i128 %0, %1
- store i128 %5, i128* %3, align 16
+ store i128 %5, ptr %3, align 16
%6 = icmp slt i128 %0, 0
br i1 %6, label %Then, label %Else
@@ -52,7 +52,7 @@ Else2:
br i1 %9, label %Then3, label %Else4
Then3:
- %10 = load i128, i128* %3, align 16
+ %10 = load i128, ptr %3, align 16
%11 = sdiv i128 %10, %0
%12 = icmp ne i128 %11, %1
br label %Block5
@@ -69,15 +69,15 @@ Block6:
br i1 %14, label %Then7, label %Else8
Then7:
- store i32 1, i32* %2, align 4
+ store i32 1, ptr %2, align 4
br label %Block9
Else8:
br label %Block9
Block9: ; preds = %Else8, %Then7
- %15 = load i128, i128* %3, align 16
- store i128 %15, i128* %4, align 16
- %16 = load i128, i128* %4, align 16
+ %15 = load i128, ptr %3, align 16
+ store i128 %15, ptr %4, align 16
+ %16 = load i128, ptr %4, align 16
ret i128 %16
}
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/peel-multiple-unreachable-exits-for-vectorization.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/peel-multiple-unreachable-exits-for-vectorization.ll
index 6c4ef763268d5..b3884368ef04e 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/peel-multiple-unreachable-exits-for-vectorization.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/peel-multiple-unreachable-exits-for-vectorization.ll
@@ -1,42 +1,40 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -O2 -mtriple=arm64-apple-ios -S %s | FileCheck %s
-%vec = type { i64*, i64* }
+%vec = type { ptr, ptr }
; Test to ensure a loop with multiple loads guarded by runtime-checks (like
; from multiple calls to C++'s std::vector::at) can be vectorized after
; hoisting the runtime checks out of the loop.
-define i64 @sum_2_at_with_int_conversion(%vec* %A, %vec* %B, i64 %N) {
+define i64 @sum_2_at_with_int_conversion(ptr %A, ptr %B, i64 %N) {
; CHECK-LABEL: @sum_2_at_with_int_conversion(
-; CHECK-NEXT: at_with_int_conversion.exit12.peel:
-; CHECK-NEXT: [[GEP_START_I:%.*]] = getelementptr [[VEC:%.*]], %vec* [[A:%.*]], i64 0, i32 0
-; CHECK-NEXT: [[START_I:%.*]] = load i64*, i64** [[GEP_START_I]], align 8
-; CHECK-NEXT: [[GEP_END_I:%.*]] = getelementptr [[VEC]], %vec* [[A]], i64 0, i32 1
-; CHECK-NEXT: [[END_I:%.*]] = load i64*, i64** [[GEP_END_I]], align 8
-; CHECK-NEXT: [[START_INT_I:%.*]] = ptrtoint i64* [[START_I]] to i64
-; CHECK-NEXT: [[END_INT_I:%.*]] = ptrtoint i64* [[END_I]] to i64
+; CHECK-NEXT: at_with_int_conversion.exit11.peel:
+; CHECK-NEXT: [[START_I:%.*]] = load ptr, ptr [[A:%.*]], align 8
+; CHECK-NEXT: [[GEP_END_I:%.*]] = getelementptr [[VEC:%.*]], ptr [[A]], i64 0, i32 1
+; CHECK-NEXT: [[END_I:%.*]] = load ptr, ptr [[GEP_END_I]], align 8
+; CHECK-NEXT: [[START_INT_I:%.*]] = ptrtoint ptr [[START_I]] to i64
+; CHECK-NEXT: [[END_INT_I:%.*]] = ptrtoint ptr [[END_I]] to i64
; CHECK-NEXT: [[SUB_I:%.*]] = sub i64 [[END_INT_I]], [[START_INT_I]]
-; CHECK-NEXT: [[GEP_END_I3:%.*]] = getelementptr [[VEC]], %vec* [[B:%.*]], i64 0, i32 1
-; CHECK-NEXT: [[GEP_START_I1:%.*]] = getelementptr [[VEC]], %vec* [[B]], i64 0, i32 0
-; CHECK-NEXT: [[START_I2_PEEL:%.*]] = load i64*, i64** [[GEP_START_I1]], align 8
-; CHECK-NEXT: [[END_I4_PEEL:%.*]] = load i64*, i64** [[GEP_END_I3]], align 8
-; CHECK-NEXT: [[START_INT_I5_PEEL:%.*]] = ptrtoint i64* [[START_I2_PEEL]] to i64
-; CHECK-NEXT: [[END_INT_I6_PEEL:%.*]] = ptrtoint i64* [[END_I4_PEEL]] to i64
-; CHECK-NEXT: [[SUB_I7_PEEL:%.*]] = sub i64 [[END_INT_I6_PEEL]], [[START_INT_I5_PEEL]]
-; CHECK-NEXT: [[LV_I_PEEL:%.*]] = load i64, i64* [[START_I]], align 4
-; CHECK-NEXT: [[LV_I10_PEEL:%.*]] = load i64, i64* [[START_I2_PEEL]], align 4
-; CHECK-NEXT: [[SUM_NEXT_PEEL:%.*]] = add i64 [[LV_I_PEEL]], [[LV_I10_PEEL]]
+; CHECK-NEXT: [[GEP_END_I2:%.*]] = getelementptr [[VEC]], ptr [[B:%.*]], i64 0, i32 1
+; CHECK-NEXT: [[START_I1_PEEL:%.*]] = load ptr, ptr [[B]], align 8
+; CHECK-NEXT: [[END_I3_PEEL:%.*]] = load ptr, ptr [[GEP_END_I2]], align 8
+; CHECK-NEXT: [[START_INT_I4_PEEL:%.*]] = ptrtoint ptr [[START_I1_PEEL]] to i64
+; CHECK-NEXT: [[END_INT_I5_PEEL:%.*]] = ptrtoint ptr [[END_I3_PEEL]] to i64
+; CHECK-NEXT: [[SUB_I6_PEEL:%.*]] = sub i64 [[END_INT_I5_PEEL]], [[START_INT_I4_PEEL]]
+; CHECK-NEXT: [[LV_I_PEEL:%.*]] = load i64, ptr [[START_I]], align 4
+; CHECK-NEXT: [[LV_I9_PEEL:%.*]] = load i64, ptr [[START_I1_PEEL]], align 4
+; CHECK-NEXT: [[SUM_NEXT_PEEL:%.*]] = add i64 [[LV_I_PEEL]], [[LV_I9_PEEL]]
; CHECK-NEXT: [[C_PEEL:%.*]] = icmp sgt i64 [[N:%.*]], 0
; CHECK-NEXT: br i1 [[C_PEEL]], label [[LOOP_PREHEADER:%.*]], label [[EXIT:%.*]]
; CHECK: loop.preheader:
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], -1
-; CHECK-NEXT: [[UMIN:%.*]] = tail call i64 @llvm.umin.i64(i64 [[SUB_I7_PEEL]], i64 [[TMP0]])
+; CHECK-NEXT: [[UMIN:%.*]] = tail call i64 @llvm.umin.i64(i64 [[SUB_I6_PEEL]], i64 [[TMP0]])
; CHECK-NEXT: [[TMP1:%.*]] = freeze i64 [[UMIN]]
-; CHECK-NEXT: [[UMIN16:%.*]] = tail call i64 @llvm.umin.i64(i64 [[TMP1]], i64 [[SUB_I]])
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[UMIN16]], 1
+; CHECK-NEXT: [[UMIN15:%.*]] = tail call i64 @llvm.umin.i64(i64 [[TMP1]], i64 [[SUB_I]])
+; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[UMIN15]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 5
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[LOOP_PREHEADER21:%.*]], label [[VECTOR_PH:%.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[LOOP_PREHEADER20:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[N_MOD_VF]], 0
@@ -47,62 +45,58 @@ define i64 @sum_2_at_with_int_conversion(%vec* %A, %vec* %B, i64 %N) {
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i64> [ [[TMP5]], [[VECTOR_PH]] ], [ [[TMP16:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI17:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP17:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i64> [ [[TMP5]], [[VECTOR_PH]] ], [ [[TMP12:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI16:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP13:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = or i64 [[INDEX]], 1
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i64, i64* [[START_I]], i64 [[OFFSET_IDX]]
-; CHECK-NEXT: [[TMP7:%.*]] = bitcast i64* [[TMP6]] to <2 x i64>*
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, <2 x i64>* [[TMP7]], align 4
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i64, i64* [[TMP6]], i64 2
-; CHECK-NEXT: [[TMP9:%.*]] = bitcast i64* [[TMP8]] to <2 x i64>*
-; CHECK-NEXT: [[WIDE_LOAD18:%.*]] = load <2 x i64>, <2 x i64>* [[TMP9]], align 4
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i64, i64* [[START_I2_PEEL]], i64 [[OFFSET_IDX]]
-; CHECK-NEXT: [[TMP11:%.*]] = bitcast i64* [[TMP10]] to <2 x i64>*
-; CHECK-NEXT: [[WIDE_LOAD19:%.*]] = load <2 x i64>, <2 x i64>* [[TMP11]], align 4
-; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i64, i64* [[TMP10]], i64 2
-; CHECK-NEXT: [[TMP13:%.*]] = bitcast i64* [[TMP12]] to <2 x i64>*
-; CHECK-NEXT: [[WIDE_LOAD20:%.*]] = load <2 x i64>, <2 x i64>* [[TMP13]], align 4
-; CHECK-NEXT: [[TMP14:%.*]] = add <2 x i64> [[WIDE_LOAD]], [[VEC_PHI]]
-; CHECK-NEXT: [[TMP15:%.*]] = add <2 x i64> [[WIDE_LOAD18]], [[VEC_PHI17]]
-; CHECK-NEXT: [[TMP16]] = add <2 x i64> [[TMP14]], [[WIDE_LOAD19]]
-; CHECK-NEXT: [[TMP17]] = add <2 x i64> [[TMP15]], [[WIDE_LOAD20]]
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i64, ptr [[START_I]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 4
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i64, ptr [[TMP6]], i64 2
+; CHECK-NEXT: [[WIDE_LOAD17:%.*]] = load <2 x i64>, ptr [[TMP7]], align 4
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[START_I1_PEEL]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT: [[WIDE_LOAD18:%.*]] = load <2 x i64>, ptr [[TMP8]], align 4
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP8]], i64 2
+; CHECK-NEXT: [[WIDE_LOAD19:%.*]] = load <2 x i64>, ptr [[TMP9]], align 4
+; CHECK-NEXT: [[TMP10:%.*]] = add <2 x i64> [[WIDE_LOAD]], [[VEC_PHI]]
+; CHECK-NEXT: [[TMP11:%.*]] = add <2 x i64> [[WIDE_LOAD17]], [[VEC_PHI16]]
+; CHECK-NEXT: [[TMP12]] = add <2 x i64> [[TMP10]], [[WIDE_LOAD18]]
+; CHECK-NEXT: [[TMP13]] = add <2 x i64> [[TMP11]], [[WIDE_LOAD19]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
-; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: middle.block:
-; CHECK-NEXT: [[BIN_RDX:%.*]] = add <2 x i64> [[TMP17]], [[TMP16]]
-; CHECK-NEXT: [[TMP19:%.*]] = tail call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> [[BIN_RDX]])
-; CHECK-NEXT: br label [[LOOP_PREHEADER21]]
-; CHECK: loop.preheader21:
+; CHECK-NEXT: [[BIN_RDX:%.*]] = add <2 x i64> [[TMP13]], [[TMP12]]
+; CHECK-NEXT: [[TMP15:%.*]] = tail call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> [[BIN_RDX]])
+; CHECK-NEXT: br label [[LOOP_PREHEADER20]]
+; CHECK: loop.preheader20:
; CHECK-NEXT: [[IV_PH:%.*]] = phi i64 [ 1, [[LOOP_PREHEADER]] ], [ [[IND_END]], [[MIDDLE_BLOCK]] ]
-; CHECK-NEXT: [[SUM_PH:%.*]] = phi i64 [ [[SUM_NEXT_PEEL]], [[LOOP_PREHEADER]] ], [ [[TMP19]], [[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[SUM_PH:%.*]] = phi i64 [ [[SUM_NEXT_PEEL]], [[LOOP_PREHEADER]] ], [ [[TMP15]], [[MIDDLE_BLOCK]] ]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[AT_WITH_INT_CONVERSION_EXIT12:%.*]] ], [ [[IV_PH]], [[LOOP_PREHEADER21]] ]
-; CHECK-NEXT: [[SUM:%.*]] = phi i64 [ [[SUM_NEXT:%.*]], [[AT_WITH_INT_CONVERSION_EXIT12]] ], [ [[SUM_PH]], [[LOOP_PREHEADER21]] ]
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[AT_WITH_INT_CONVERSION_EXIT11:%.*]] ], [ [[IV_PH]], [[LOOP_PREHEADER20]] ]
+; CHECK-NEXT: [[SUM:%.*]] = phi i64 [ [[SUM_NEXT:%.*]], [[AT_WITH_INT_CONVERSION_EXIT11]] ], [ [[SUM_PH]], [[LOOP_PREHEADER20]] ]
; CHECK-NEXT: [[INRANGE_I:%.*]] = icmp ult i64 [[SUB_I]], [[IV]]
; CHECK-NEXT: br i1 [[INRANGE_I]], label [[ERROR_I:%.*]], label [[AT_WITH_INT_CONVERSION_EXIT:%.*]]
; CHECK: error.i:
; CHECK-NEXT: tail call void @error()
; CHECK-NEXT: unreachable
; CHECK: at_with_int_conversion.exit:
-; CHECK-NEXT: [[INRANGE_I8:%.*]] = icmp ult i64 [[SUB_I7_PEEL]], [[IV]]
-; CHECK-NEXT: br i1 [[INRANGE_I8]], label [[ERROR_I11:%.*]], label [[AT_WITH_INT_CONVERSION_EXIT12]]
-; CHECK: error.i11:
+; CHECK-NEXT: [[INRANGE_I7:%.*]] = icmp ult i64 [[SUB_I6_PEEL]], [[IV]]
+; CHECK-NEXT: br i1 [[INRANGE_I7]], label [[ERROR_I10:%.*]], label [[AT_WITH_INT_CONVERSION_EXIT11]]
+; CHECK: error.i10:
; CHECK-NEXT: tail call void @error()
; CHECK-NEXT: unreachable
-; CHECK: at_with_int_conversion.exit12:
-; CHECK-NEXT: [[GEP_IDX_I:%.*]] = getelementptr i64, i64* [[START_I]], i64 [[IV]]
-; CHECK-NEXT: [[LV_I:%.*]] = load i64, i64* [[GEP_IDX_I]], align 4
-; CHECK-NEXT: [[GEP_IDX_I9:%.*]] = getelementptr i64, i64* [[START_I2_PEEL]], i64 [[IV]]
-; CHECK-NEXT: [[LV_I10:%.*]] = load i64, i64* [[GEP_IDX_I9]], align 4
+; CHECK: at_with_int_conversion.exit11:
+; CHECK-NEXT: [[GEP_IDX_I:%.*]] = getelementptr i64, ptr [[START_I]], i64 [[IV]]
+; CHECK-NEXT: [[LV_I:%.*]] = load i64, ptr [[GEP_IDX_I]], align 4
+; CHECK-NEXT: [[GEP_IDX_I8:%.*]] = getelementptr i64, ptr [[START_I1_PEEL]], i64 [[IV]]
+; CHECK-NEXT: [[LV_I9:%.*]] = load i64, ptr [[GEP_IDX_I8]], align 4
; CHECK-NEXT: [[ADD:%.*]] = add i64 [[LV_I]], [[SUM]]
-; CHECK-NEXT: [[SUM_NEXT]] = add i64 [[ADD]], [[LV_I10]]
+; CHECK-NEXT: [[SUM_NEXT]] = add i64 [[ADD]], [[LV_I9]]
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[C:%.*]] = icmp slt i64 [[IV]], [[N]]
; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: exit:
-; CHECK-NEXT: [[SUM_NEXT_LCSSA:%.*]] = phi i64 [ [[SUM_NEXT_PEEL]], [[AT_WITH_INT_CONVERSION_EXIT12_PEEL:%.*]] ], [ [[SUM_NEXT]], [[AT_WITH_INT_CONVERSION_EXIT12]] ]
+; CHECK-NEXT: [[SUM_NEXT_LCSSA:%.*]] = phi i64 [ [[SUM_NEXT_PEEL]], [[AT_WITH_INT_CONVERSION_EXIT11_PEEL:%.*]] ], [ [[SUM_NEXT]], [[AT_WITH_INT_CONVERSION_EXIT11]] ]
; CHECK-NEXT: ret i64 [[SUM_NEXT_LCSSA]]
;
entry:
@@ -111,8 +105,8 @@ entry:
loop:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
%sum = phi i64 [ 0, %entry ], [ %sum.next, %loop ]
- %a = call i64 @at_with_int_conversion(%vec* %A, i64 %iv)
- %b = call i64 @at_with_int_conversion(%vec* %B, i64 %iv)
+ %a = call i64 @at_with_int_conversion(ptr %A, i64 %iv)
+ %b = call i64 @at_with_int_conversion(ptr %B, i64 %iv)
%add = add i64 %a, %b
%sum.next = add i64 %sum, %add
%iv.next = add nuw nsw i64 %iv, 1
@@ -123,47 +117,44 @@ exit:
ret i64 %sum.next
}
-define i64 @sum_3_at_with_int_conversion(%vec* %A, %vec* %B, %vec* %C, i64 %N) {
+define i64 @sum_3_at_with_int_conversion(ptr %A, ptr %B, ptr %C, i64 %N) {
; CHECK-LABEL: @sum_3_at_with_int_conversion(
-; CHECK-NEXT: at_with_int_conversion.exit24.peel:
-; CHECK-NEXT: [[GEP_START_I:%.*]] = getelementptr [[VEC:%.*]], %vec* [[A:%.*]], i64 0, i32 0
-; CHECK-NEXT: [[START_I:%.*]] = load i64*, i64** [[GEP_START_I]], align 8
-; CHECK-NEXT: [[GEP_END_I:%.*]] = getelementptr [[VEC]], %vec* [[A]], i64 0, i32 1
-; CHECK-NEXT: [[END_I:%.*]] = load i64*, i64** [[GEP_END_I]], align 8
-; CHECK-NEXT: [[START_INT_I:%.*]] = ptrtoint i64* [[START_I]] to i64
-; CHECK-NEXT: [[END_INT_I:%.*]] = ptrtoint i64* [[END_I]] to i64
+; CHECK-NEXT: at_with_int_conversion.exit22.peel:
+; CHECK-NEXT: [[START_I:%.*]] = load ptr, ptr [[A:%.*]], align 8
+; CHECK-NEXT: [[GEP_END_I:%.*]] = getelementptr [[VEC:%.*]], ptr [[A]], i64 0, i32 1
+; CHECK-NEXT: [[END_I:%.*]] = load ptr, ptr [[GEP_END_I]], align 8
+; CHECK-NEXT: [[START_INT_I:%.*]] = ptrtoint ptr [[START_I]] to i64
+; CHECK-NEXT: [[END_INT_I:%.*]] = ptrtoint ptr [[END_I]] to i64
; CHECK-NEXT: [[SUB_I:%.*]] = sub i64 [[END_INT_I]], [[START_INT_I]]
-; CHECK-NEXT: [[GEP_START_I13:%.*]] = getelementptr [[VEC]], %vec* [[C:%.*]], i64 0, i32 0
-; CHECK-NEXT: [[GEP_END_I15:%.*]] = getelementptr [[VEC]], %vec* [[C]], i64 0, i32 1
-; CHECK-NEXT: [[GEP_END_I3:%.*]] = getelementptr [[VEC]], %vec* [[B:%.*]], i64 0, i32 1
-; CHECK-NEXT: [[GEP_START_I1:%.*]] = getelementptr [[VEC]], %vec* [[B]], i64 0, i32 0
-; CHECK-NEXT: [[LV_I_PEEL:%.*]] = load i64, i64* [[START_I]], align 4
-; CHECK-NEXT: [[START_I2_PEEL:%.*]] = load i64*, i64** [[GEP_START_I1]], align 8
-; CHECK-NEXT: [[END_I4_PEEL:%.*]] = load i64*, i64** [[GEP_END_I3]], align 8
-; CHECK-NEXT: [[START_INT_I5_PEEL:%.*]] = ptrtoint i64* [[START_I2_PEEL]] to i64
-; CHECK-NEXT: [[END_I4_PEEL_FR:%.*]] = freeze i64* [[END_I4_PEEL]]
-; CHECK-NEXT: [[END_INT_I6_PEEL:%.*]] = ptrtoint i64* [[END_I4_PEEL_FR]] to i64
-; CHECK-NEXT: [[SUB_I7_PEEL:%.*]] = sub i64 [[END_INT_I6_PEEL]], [[START_INT_I5_PEEL]]
-; CHECK-NEXT: [[START_I14_PEEL:%.*]] = load i64*, i64** [[GEP_START_I13]], align 8
-; CHECK-NEXT: [[END_I16_PEEL:%.*]] = load i64*, i64** [[GEP_END_I15]], align 8
-; CHECK-NEXT: [[START_INT_I17_PEEL:%.*]] = ptrtoint i64* [[START_I14_PEEL]] to i64
-; CHECK-NEXT: [[END_INT_I18_PEEL:%.*]] = ptrtoint i64* [[END_I16_PEEL]] to i64
-; CHECK-NEXT: [[SUB_I19_PEEL:%.*]] = sub i64 [[END_INT_I18_PEEL]], [[START_INT_I17_PEEL]]
-; CHECK-NEXT: [[LV_I10_PEEL:%.*]] = load i64, i64* [[START_I2_PEEL]], align 4
-; CHECK-NEXT: [[LV_I22_PEEL:%.*]] = load i64, i64* [[START_I14_PEEL]], align 4
-; CHECK-NEXT: [[ADD_2_PEEL:%.*]] = add i64 [[LV_I_PEEL]], [[LV_I10_PEEL]]
-; CHECK-NEXT: [[SUM_NEXT_PEEL:%.*]] = add i64 [[ADD_2_PEEL]], [[LV_I22_PEEL]]
+; CHECK-NEXT: [[GEP_END_I13:%.*]] = getelementptr [[VEC]], ptr [[C:%.*]], i64 0, i32 1
+; CHECK-NEXT: [[GEP_END_I2:%.*]] = getelementptr [[VEC]], ptr [[B:%.*]], i64 0, i32 1
+; CHECK-NEXT: [[LV_I_PEEL:%.*]] = load i64, ptr [[START_I]], align 4
+; CHECK-NEXT: [[START_I1_PEEL:%.*]] = load ptr, ptr [[B]], align 8
+; CHECK-NEXT: [[END_I3_PEEL:%.*]] = load ptr, ptr [[GEP_END_I2]], align 8
+; CHECK-NEXT: [[START_INT_I4_PEEL:%.*]] = ptrtoint ptr [[START_I1_PEEL]] to i64
+; CHECK-NEXT: [[END_I3_PEEL_FR:%.*]] = freeze ptr [[END_I3_PEEL]]
+; CHECK-NEXT: [[END_INT_I5_PEEL:%.*]] = ptrtoint ptr [[END_I3_PEEL_FR]] to i64
+; CHECK-NEXT: [[SUB_I6_PEEL:%.*]] = sub i64 [[END_INT_I5_PEEL]], [[START_INT_I4_PEEL]]
+; CHECK-NEXT: [[START_I12_PEEL:%.*]] = load ptr, ptr [[C]], align 8
+; CHECK-NEXT: [[END_I14_PEEL:%.*]] = load ptr, ptr [[GEP_END_I13]], align 8
+; CHECK-NEXT: [[START_INT_I15_PEEL:%.*]] = ptrtoint ptr [[START_I12_PEEL]] to i64
+; CHECK-NEXT: [[END_INT_I16_PEEL:%.*]] = ptrtoint ptr [[END_I14_PEEL]] to i64
+; CHECK-NEXT: [[SUB_I17_PEEL:%.*]] = sub i64 [[END_INT_I16_PEEL]], [[START_INT_I15_PEEL]]
+; CHECK-NEXT: [[LV_I9_PEEL:%.*]] = load i64, ptr [[START_I1_PEEL]], align 4
+; CHECK-NEXT: [[LV_I20_PEEL:%.*]] = load i64, ptr [[START_I12_PEEL]], align 4
+; CHECK-NEXT: [[ADD_2_PEEL:%.*]] = add i64 [[LV_I_PEEL]], [[LV_I9_PEEL]]
+; CHECK-NEXT: [[SUM_NEXT_PEEL:%.*]] = add i64 [[ADD_2_PEEL]], [[LV_I20_PEEL]]
; CHECK-NEXT: [[COND_PEEL:%.*]] = icmp sgt i64 [[N:%.*]], 0
; CHECK-NEXT: br i1 [[COND_PEEL]], label [[LOOP_PREHEADER:%.*]], label [[EXIT:%.*]]
; CHECK: loop.preheader:
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], -1
-; CHECK-NEXT: [[UMIN:%.*]] = tail call i64 @llvm.umin.i64(i64 [[SUB_I19_PEEL]], i64 [[TMP0]])
+; CHECK-NEXT: [[UMIN:%.*]] = tail call i64 @llvm.umin.i64(i64 [[SUB_I17_PEEL]], i64 [[TMP0]])
; CHECK-NEXT: [[TMP1:%.*]] = freeze i64 [[UMIN]]
-; CHECK-NEXT: [[UMIN28:%.*]] = tail call i64 @llvm.umin.i64(i64 [[TMP1]], i64 [[SUB_I7_PEEL]])
-; CHECK-NEXT: [[UMIN29:%.*]] = tail call i64 @llvm.umin.i64(i64 [[UMIN28]], i64 [[SUB_I]])
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[UMIN29]], 1
+; CHECK-NEXT: [[UMIN26:%.*]] = tail call i64 @llvm.umin.i64(i64 [[TMP1]], i64 [[SUB_I6_PEEL]])
+; CHECK-NEXT: [[UMIN27:%.*]] = tail call i64 @llvm.umin.i64(i64 [[UMIN26]], i64 [[SUB_I]])
+; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[UMIN27]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 5
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[LOOP_PREHEADER36:%.*]], label [[VECTOR_PH:%.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[LOOP_PREHEADER34:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[N_MOD_VF]], 0
@@ -174,79 +165,73 @@ define i64 @sum_3_at_with_int_conversion(%vec* %A, %vec* %B, %vec* %C, i64 %N) {
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i64> [ [[TMP5]], [[VECTOR_PH]] ], [ [[TMP22:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_PHI30:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP23:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i64> [ [[TMP5]], [[VECTOR_PH]] ], [ [[TMP16:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_PHI28:%.*]] = phi <2 x i64> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP17:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = or i64 [[INDEX]], 1
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i64, i64* [[START_I]], i64 [[OFFSET_IDX]]
-; CHECK-NEXT: [[TMP7:%.*]] = bitcast i64* [[TMP6]] to <2 x i64>*
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, <2 x i64>* [[TMP7]], align 4
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i64, i64* [[TMP6]], i64 2
-; CHECK-NEXT: [[TMP9:%.*]] = bitcast i64* [[TMP8]] to <2 x i64>*
-; CHECK-NEXT: [[WIDE_LOAD31:%.*]] = load <2 x i64>, <2 x i64>* [[TMP9]], align 4
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i64, i64* [[START_I2_PEEL]], i64 [[OFFSET_IDX]]
-; CHECK-NEXT: [[TMP11:%.*]] = bitcast i64* [[TMP10]] to <2 x i64>*
-; CHECK-NEXT: [[WIDE_LOAD32:%.*]] = load <2 x i64>, <2 x i64>* [[TMP11]], align 4
-; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i64, i64* [[TMP10]], i64 2
-; CHECK-NEXT: [[TMP13:%.*]] = bitcast i64* [[TMP12]] to <2 x i64>*
-; CHECK-NEXT: [[WIDE_LOAD33:%.*]] = load <2 x i64>, <2 x i64>* [[TMP13]], align 4
-; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i64, i64* [[START_I14_PEEL]], i64 [[OFFSET_IDX]]
-; CHECK-NEXT: [[TMP15:%.*]] = bitcast i64* [[TMP14]] to <2 x i64>*
-; CHECK-NEXT: [[WIDE_LOAD34:%.*]] = load <2 x i64>, <2 x i64>* [[TMP15]], align 4
-; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i64, i64* [[TMP14]], i64 2
-; CHECK-NEXT: [[TMP17:%.*]] = bitcast i64* [[TMP16]] to <2 x i64>*
-; CHECK-NEXT: [[WIDE_LOAD35:%.*]] = load <2 x i64>, <2 x i64>* [[TMP17]], align 4
-; CHECK-NEXT: [[TMP18:%.*]] = add <2 x i64> [[WIDE_LOAD]], [[VEC_PHI]]
-; CHECK-NEXT: [[TMP19:%.*]] = add <2 x i64> [[WIDE_LOAD31]], [[VEC_PHI30]]
-; CHECK-NEXT: [[TMP20:%.*]] = add <2 x i64> [[TMP18]], [[WIDE_LOAD32]]
-; CHECK-NEXT: [[TMP21:%.*]] = add <2 x i64> [[TMP19]], [[WIDE_LOAD33]]
-; CHECK-NEXT: [[TMP22]] = add <2 x i64> [[TMP20]], [[WIDE_LOAD34]]
-; CHECK-NEXT: [[TMP23]] = add <2 x i64> [[TMP21]], [[WIDE_LOAD35]]
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i64, ptr [[START_I]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 4
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i64, ptr [[TMP6]], i64 2
+; CHECK-NEXT: [[WIDE_LOAD29:%.*]] = load <2 x i64>, ptr [[TMP7]], align 4
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[START_I1_PEEL]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT: [[WIDE_LOAD30:%.*]] = load <2 x i64>, ptr [[TMP8]], align 4
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP8]], i64 2
+; CHECK-NEXT: [[WIDE_LOAD31:%.*]] = load <2 x i64>, ptr [[TMP9]], align 4
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i64, ptr [[START_I12_PEEL]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT: [[WIDE_LOAD32:%.*]] = load <2 x i64>, ptr [[TMP10]], align 4
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i64, ptr [[TMP10]], i64 2
+; CHECK-NEXT: [[WIDE_LOAD33:%.*]] = load <2 x i64>, ptr [[TMP11]], align 4
+; CHECK-NEXT: [[TMP12:%.*]] = add <2 x i64> [[WIDE_LOAD]], [[VEC_PHI]]
+; CHECK-NEXT: [[TMP13:%.*]] = add <2 x i64> [[WIDE_LOAD29]], [[VEC_PHI28]]
+; CHECK-NEXT: [[TMP14:%.*]] = add <2 x i64> [[TMP12]], [[WIDE_LOAD30]]
+; CHECK-NEXT: [[TMP15:%.*]] = add <2 x i64> [[TMP13]], [[WIDE_LOAD31]]
+; CHECK-NEXT: [[TMP16]] = add <2 x i64> [[TMP14]], [[WIDE_LOAD32]]
+; CHECK-NEXT: [[TMP17]] = add <2 x i64> [[TMP15]], [[WIDE_LOAD33]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
-; CHECK-NEXT: [[TMP24:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP24]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: middle.block:
-; CHECK-NEXT: [[BIN_RDX:%.*]] = add <2 x i64> [[TMP23]], [[TMP22]]
-; CHECK-NEXT: [[TMP25:%.*]] = tail call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> [[BIN_RDX]])
-; CHECK-NEXT: br label [[LOOP_PREHEADER36]]
-; CHECK: loop.preheader36:
+; CHECK-NEXT: [[BIN_RDX:%.*]] = add <2 x i64> [[TMP17]], [[TMP16]]
+; CHECK-NEXT: [[TMP19:%.*]] = tail call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> [[BIN_RDX]])
+; CHECK-NEXT: br label [[LOOP_PREHEADER34]]
+; CHECK: loop.preheader34:
; CHECK-NEXT: [[IV_PH:%.*]] = phi i64 [ 1, [[LOOP_PREHEADER]] ], [ [[IND_END]], [[MIDDLE_BLOCK]] ]
-; CHECK-NEXT: [[SUM_PH:%.*]] = phi i64 [ [[SUM_NEXT_PEEL]], [[LOOP_PREHEADER]] ], [ [[TMP25]], [[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[SUM_PH:%.*]] = phi i64 [ [[SUM_NEXT_PEEL]], [[LOOP_PREHEADER]] ], [ [[TMP19]], [[MIDDLE_BLOCK]] ]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[AT_WITH_INT_CONVERSION_EXIT24:%.*]] ], [ [[IV_PH]], [[LOOP_PREHEADER36]] ]
-; CHECK-NEXT: [[SUM:%.*]] = phi i64 [ [[SUM_NEXT:%.*]], [[AT_WITH_INT_CONVERSION_EXIT24]] ], [ [[SUM_PH]], [[LOOP_PREHEADER36]] ]
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[AT_WITH_INT_CONVERSION_EXIT22:%.*]] ], [ [[IV_PH]], [[LOOP_PREHEADER34]] ]
+; CHECK-NEXT: [[SUM:%.*]] = phi i64 [ [[SUM_NEXT:%.*]], [[AT_WITH_INT_CONVERSION_EXIT22]] ], [ [[SUM_PH]], [[LOOP_PREHEADER34]] ]
; CHECK-NEXT: [[INRANGE_I:%.*]] = icmp ult i64 [[SUB_I]], [[IV]]
; CHECK-NEXT: br i1 [[INRANGE_I]], label [[ERROR_I:%.*]], label [[AT_WITH_INT_CONVERSION_EXIT:%.*]]
; CHECK: error.i:
; CHECK-NEXT: tail call void @error()
; CHECK-NEXT: unreachable
; CHECK: at_with_int_conversion.exit:
-; CHECK-NEXT: [[GEP_IDX_I:%.*]] = getelementptr i64, i64* [[START_I]], i64 [[IV]]
-; CHECK-NEXT: [[LV_I:%.*]] = load i64, i64* [[GEP_IDX_I]], align 4
-; CHECK-NEXT: [[INRANGE_I8:%.*]] = icmp ult i64 [[SUB_I7_PEEL]], [[IV]]
-; CHECK-NEXT: br i1 [[INRANGE_I8]], label [[ERROR_I11:%.*]], label [[AT_WITH_INT_CONVERSION_EXIT12:%.*]]
-; CHECK: error.i11:
+; CHECK-NEXT: [[GEP_IDX_I:%.*]] = getelementptr i64, ptr [[START_I]], i64 [[IV]]
+; CHECK-NEXT: [[LV_I:%.*]] = load i64, ptr [[GEP_IDX_I]], align 4
+; CHECK-NEXT: [[INRANGE_I7:%.*]] = icmp ult i64 [[SUB_I6_PEEL]], [[IV]]
+; CHECK-NEXT: br i1 [[INRANGE_I7]], label [[ERROR_I10:%.*]], label [[AT_WITH_INT_CONVERSION_EXIT11:%.*]]
+; CHECK: error.i10:
; CHECK-NEXT: tail call void @error()
; CHECK-NEXT: unreachable
-; CHECK: at_with_int_conversion.exit12:
-; CHECK-NEXT: [[INRANGE_I20:%.*]] = icmp ult i64 [[SUB_I19_PEEL]], [[IV]]
-; CHECK-NEXT: br i1 [[INRANGE_I20]], label [[ERROR_I23:%.*]], label [[AT_WITH_INT_CONVERSION_EXIT24]]
-; CHECK: error.i23:
+; CHECK: at_with_int_conversion.exit11:
+; CHECK-NEXT: [[INRANGE_I18:%.*]] = icmp ult i64 [[SUB_I17_PEEL]], [[IV]]
+; CHECK-NEXT: br i1 [[INRANGE_I18]], label [[ERROR_I21:%.*]], label [[AT_WITH_INT_CONVERSION_EXIT22]]
+; CHECK: error.i21:
; CHECK-NEXT: tail call void @error()
; CHECK-NEXT: unreachable
-; CHECK: at_with_int_conversion.exit24:
-; CHECK-NEXT: [[GEP_IDX_I9:%.*]] = getelementptr i64, i64* [[START_I2_PEEL]], i64 [[IV]]
-; CHECK-NEXT: [[LV_I10:%.*]] = load i64, i64* [[GEP_IDX_I9]], align 4
-; CHECK-NEXT: [[GEP_IDX_I21:%.*]] = getelementptr i64, i64* [[START_I14_PEEL]], i64 [[IV]]
-; CHECK-NEXT: [[LV_I22:%.*]] = load i64, i64* [[GEP_IDX_I21]], align 4
+; CHECK: at_with_int_conversion.exit22:
+; CHECK-NEXT: [[GEP_IDX_I8:%.*]] = getelementptr i64, ptr [[START_I1_PEEL]], i64 [[IV]]
+; CHECK-NEXT: [[LV_I9:%.*]] = load i64, ptr [[GEP_IDX_I8]], align 4
+; CHECK-NEXT: [[GEP_IDX_I19:%.*]] = getelementptr i64, ptr [[START_I12_PEEL]], i64 [[IV]]
+; CHECK-NEXT: [[LV_I20:%.*]] = load i64, ptr [[GEP_IDX_I19]], align 4
; CHECK-NEXT: [[ADD_1:%.*]] = add i64 [[LV_I]], [[SUM]]
-; CHECK-NEXT: [[ADD_2:%.*]] = add i64 [[ADD_1]], [[LV_I10]]
-; CHECK-NEXT: [[SUM_NEXT]] = add i64 [[ADD_2]], [[LV_I22]]
+; CHECK-NEXT: [[ADD_2:%.*]] = add i64 [[ADD_1]], [[LV_I9]]
+; CHECK-NEXT: [[SUM_NEXT]] = add i64 [[ADD_2]], [[LV_I20]]
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp slt i64 [[IV]], [[N]]
; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK: exit:
-; CHECK-NEXT: [[SUM_NEXT_LCSSA:%.*]] = phi i64 [ [[SUM_NEXT_PEEL]], [[AT_WITH_INT_CONVERSION_EXIT24_PEEL:%.*]] ], [ [[SUM_NEXT]], [[AT_WITH_INT_CONVERSION_EXIT24]] ]
+; CHECK-NEXT: [[SUM_NEXT_LCSSA:%.*]] = phi i64 [ [[SUM_NEXT_PEEL]], [[AT_WITH_INT_CONVERSION_EXIT22_PEEL:%.*]] ], [ [[SUM_NEXT]], [[AT_WITH_INT_CONVERSION_EXIT22]] ]
; CHECK-NEXT: ret i64 [[SUM_NEXT_LCSSA]]
;
entry:
@@ -255,9 +240,9 @@ entry:
loop:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
%sum = phi i64 [ 0, %entry ], [ %sum.next, %loop ]
- %a = call i64 @at_with_int_conversion(%vec* %A, i64 %iv)
- %b = call i64 @at_with_int_conversion(%vec* %B, i64 %iv)
- %c = call i64 @at_with_int_conversion(%vec* %C, i64 %iv)
+ %a = call i64 @at_with_int_conversion(ptr %A, i64 %iv)
+ %b = call i64 @at_with_int_conversion(ptr %B, i64 %iv)
+ %c = call i64 @at_with_int_conversion(ptr %C, i64 %iv)
%add.1 = add i64 %a, %b
%add.2 = add i64 %add.1, %c
%sum.next = add i64 %sum, %add.2
@@ -270,38 +255,36 @@ exit:
}
-define i64 @at_with_int_conversion(%vec* %ptr, i64 %idx) {
+define i64 @at_with_int_conversion(ptr %ptr, i64 %idx) {
; CHECK-LABEL: @at_with_int_conversion(
-; CHECK-NEXT: [[GEP_START:%.*]] = getelementptr [[VEC:%.*]], %vec* [[PTR:%.*]], i64 0, i32 0
-; CHECK-NEXT: [[START:%.*]] = load i64*, i64** [[GEP_START]], align 8
-; CHECK-NEXT: [[GEP_END:%.*]] = getelementptr [[VEC]], %vec* [[PTR]], i64 0, i32 1
-; CHECK-NEXT: [[END:%.*]] = load i64*, i64** [[GEP_END]], align 8
-; CHECK-NEXT: [[START_INT:%.*]] = ptrtoint i64* [[START]] to i64
-; CHECK-NEXT: [[END_INT:%.*]] = ptrtoint i64* [[END]] to i64
+; CHECK-NEXT: [[START:%.*]] = load ptr, ptr [[PTR:%.*]], align 8
+; CHECK-NEXT: [[GEP_END:%.*]] = getelementptr [[VEC:%.*]], ptr [[PTR]], i64 0, i32 1
+; CHECK-NEXT: [[END:%.*]] = load ptr, ptr [[GEP_END]], align 8
+; CHECK-NEXT: [[START_INT:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[END_INT:%.*]] = ptrtoint ptr [[END]] to i64
; CHECK-NEXT: [[SUB:%.*]] = sub i64 [[END_INT]], [[START_INT]]
; CHECK-NEXT: [[INRANGE:%.*]] = icmp ult i64 [[SUB]], [[IDX:%.*]]
; CHECK-NEXT: br i1 [[INRANGE]], label [[ERROR:%.*]], label [[EXIT:%.*]]
; CHECK: exit:
-; CHECK-NEXT: [[GEP_IDX:%.*]] = getelementptr i64, i64* [[START]], i64 [[IDX]]
-; CHECK-NEXT: [[LV:%.*]] = load i64, i64* [[GEP_IDX]], align 4
+; CHECK-NEXT: [[GEP_IDX:%.*]] = getelementptr i64, ptr [[START]], i64 [[IDX]]
+; CHECK-NEXT: [[LV:%.*]] = load i64, ptr [[GEP_IDX]], align 4
; CHECK-NEXT: ret i64 [[LV]]
; CHECK: error:
; CHECK-NEXT: tail call void @error()
; CHECK-NEXT: unreachable
;
- %gep.start = getelementptr %vec, %vec* %ptr, i64 0, i32 0
- %start = load i64*, i64** %gep.start
- %gep.end = getelementptr %vec, %vec* %ptr, i64 0, i32 1
- %end = load i64*, i64** %gep.end
- %start.int = ptrtoint i64* %start to i64
- %end.int = ptrtoint i64* %end to i64
+ %start = load ptr, ptr %ptr
+ %gep.end = getelementptr %vec, ptr %ptr, i64 0, i32 1
+ %end = load ptr, ptr %gep.end
+ %start.int = ptrtoint ptr %start to i64
+ %end.int = ptrtoint ptr %end to i64
%sub = sub i64 %end.int, %start.int
%inrange = icmp ugt i64 %idx, %sub
br i1 %inrange, label %error, label %exit
exit:
- %gep.idx = getelementptr i64, i64* %start, i64 %idx
- %lv = load i64, i64* %gep.idx
+ %gep.idx = getelementptr i64, ptr %start, i64 %idx
+ %lv = load i64, ptr %gep.idx
ret i64 %lv
error:
diff --git a/llvm/test/Transforms/PhaseOrdering/ARM/arm_add_q7.ll b/llvm/test/Transforms/PhaseOrdering/ARM/arm_add_q7.ll
index 1c3474f82bafa..b1d0c70abc558 100644
--- a/llvm/test/Transforms/PhaseOrdering/ARM/arm_add_q7.ll
+++ b/llvm/test/Transforms/PhaseOrdering/ARM/arm_add_q7.ll
@@ -8,7 +8,7 @@ target triple = "thumbv8.1m.main-arm-none-eabi"
; 16x vector loop handling llvm.sadd.sat. __SSAT is inlined and so is DCE'd.
; Function Attrs: nounwind
-define dso_local void @arm_add_q7(i8* %pSrcA, i8* %pSrcB, i8* noalias %pDst, i32 %blockSize) #0 {
+define dso_local void @arm_add_q7(ptr %pSrcA, ptr %pSrcB, ptr noalias %pDst, i32 %blockSize) #0 {
; CHECK-LABEL: @arm_add_q7(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP_NOT3:%.*]] = icmp eq i32 [[BLOCKSIZE:%.*]], 0
@@ -19,17 +19,14 @@ define dso_local void @arm_add_q7(i8* %pSrcA, i8* %pSrcB, i8* noalias %pDst, i32
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, i8* [[PSRCA:%.*]], i32 [[INDEX]]
-; CHECK-NEXT: [[NEXT_GEP14:%.*]] = getelementptr i8, i8* [[PDST:%.*]], i32 [[INDEX]]
-; CHECK-NEXT: [[NEXT_GEP15:%.*]] = getelementptr i8, i8* [[PSRCB:%.*]], i32 [[INDEX]]
+; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PSRCA:%.*]], i32 [[INDEX]]
+; CHECK-NEXT: [[NEXT_GEP14:%.*]] = getelementptr i8, ptr [[PDST:%.*]], i32 [[INDEX]]
+; CHECK-NEXT: [[NEXT_GEP15:%.*]] = getelementptr i8, ptr [[PSRCB:%.*]], i32 [[INDEX]]
; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = tail call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 [[INDEX]], i32 [[BLOCKSIZE]])
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[NEXT_GEP]] to <16 x i8>*
-; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = tail call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* [[TMP0]], i32 1, <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i8> poison)
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[NEXT_GEP15]] to <16 x i8>*
-; CHECK-NEXT: [[WIDE_MASKED_LOAD16:%.*]] = tail call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* [[TMP1]], i32 1, <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i8> poison)
+; CHECK-NEXT: [[WIDE_MASKED_LOAD:%.*]] = tail call <16 x i8> @llvm.masked.load.v16i8.p0(ptr [[NEXT_GEP]], i32 1, <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i8> poison)
+; CHECK-NEXT: [[WIDE_MASKED_LOAD16:%.*]] = tail call <16 x i8> @llvm.masked.load.v16i8.p0(ptr [[NEXT_GEP15]], i32 1, <16 x i1> [[ACTIVE_LANE_MASK]], <16 x i8> poison)
; CHECK-NEXT: [[TMP2:%.*]] = tail call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> [[WIDE_MASKED_LOAD]], <16 x i8> [[WIDE_MASKED_LOAD16]])
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[NEXT_GEP14]] to <16 x i8>*
-; CHECK-NEXT: tail call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> [[TMP2]], <16 x i8>* [[TMP3]], i32 1, <16 x i1> [[ACTIVE_LANE_MASK]])
+; CHECK-NEXT: tail call void @llvm.masked.store.v16i8.p0(<16 x i8> [[TMP2]], ptr [[NEXT_GEP14]], i32 1, <16 x i1> [[ACTIVE_LANE_MASK]])
; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 16
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP4]], label [[WHILE_END]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
@@ -37,53 +34,51 @@ define dso_local void @arm_add_q7(i8* %pSrcA, i8* %pSrcB, i8* noalias %pDst, i32
; CHECK-NEXT: ret void
;
entry:
- %pSrcA.addr = alloca i8*, align 4
- %pSrcB.addr = alloca i8*, align 4
- %pDst.addr = alloca i8*, align 4
+ %pSrcA.addr = alloca ptr, align 4
+ %pSrcB.addr = alloca ptr, align 4
+ %pDst.addr = alloca ptr, align 4
%blockSize.addr = alloca i32, align 4
%blkCnt = alloca i32, align 4
- store i8* %pSrcA, i8** %pSrcA.addr, align 4
- store i8* %pSrcB, i8** %pSrcB.addr, align 4
- store i8* %pDst, i8** %pDst.addr, align 4
- store i32 %blockSize, i32* %blockSize.addr, align 4
- %0 = bitcast i32* %blkCnt to i8*
- call void @llvm.lifetime.start.p0i8(i64 4, i8* %0)
- %1 = load i32, i32* %blockSize.addr, align 4
- store i32 %1, i32* %blkCnt, align 4
+ store ptr %pSrcA, ptr %pSrcA.addr, align 4
+ store ptr %pSrcB, ptr %pSrcB.addr, align 4
+ store ptr %pDst, ptr %pDst.addr, align 4
+ store i32 %blockSize, ptr %blockSize.addr, align 4
+ call void @llvm.lifetime.start.p0(i64 4, ptr %blkCnt)
+ %0 = load i32, ptr %blockSize.addr, align 4
+ store i32 %0, ptr %blkCnt, align 4
br label %while.cond
while.cond: ; preds = %while.body, %entry
- %2 = load i32, i32* %blkCnt, align 4
- %cmp = icmp ugt i32 %2, 0
+ %1 = load i32, ptr %blkCnt, align 4
+ %cmp = icmp ugt i32 %1, 0
br i1 %cmp, label %while.body, label %while.end
while.body: ; preds = %while.cond
- %3 = load i8*, i8** %pSrcA.addr, align 4
- %incdec.ptr = getelementptr inbounds i8, i8* %3, i32 1
- store i8* %incdec.ptr, i8** %pSrcA.addr, align 4
- %4 = load i8, i8* %3, align 1
- %conv = sext i8 %4 to i16
+ %2 = load ptr, ptr %pSrcA.addr, align 4
+ %incdec.ptr = getelementptr inbounds i8, ptr %2, i32 1
+ store ptr %incdec.ptr, ptr %pSrcA.addr, align 4
+ %3 = load i8, ptr %2, align 1
+ %conv = sext i8 %3 to i16
%conv1 = sext i16 %conv to i32
- %5 = load i8*, i8** %pSrcB.addr, align 4
- %incdec.ptr2 = getelementptr inbounds i8, i8* %5, i32 1
- store i8* %incdec.ptr2, i8** %pSrcB.addr, align 4
- %6 = load i8, i8* %5, align 1
- %conv3 = sext i8 %6 to i32
+ %4 = load ptr, ptr %pSrcB.addr, align 4
+ %incdec.ptr2 = getelementptr inbounds i8, ptr %4, i32 1
+ store ptr %incdec.ptr2, ptr %pSrcB.addr, align 4
+ %5 = load i8, ptr %4, align 1
+ %conv3 = sext i8 %5 to i32
%add = add nsw i32 %conv1, %conv3
%call = call i32 @__SSAT(i32 %add, i32 8)
%conv4 = trunc i32 %call to i8
- %7 = load i8*, i8** %pDst.addr, align 4
- %incdec.ptr5 = getelementptr inbounds i8, i8* %7, i32 1
- store i8* %incdec.ptr5, i8** %pDst.addr, align 4
- store i8 %conv4, i8* %7, align 1
- %8 = load i32, i32* %blkCnt, align 4
- %dec = add i32 %8, -1
- store i32 %dec, i32* %blkCnt, align 4
+ %6 = load ptr, ptr %pDst.addr, align 4
+ %incdec.ptr5 = getelementptr inbounds i8, ptr %6, i32 1
+ store ptr %incdec.ptr5, ptr %pDst.addr, align 4
+ store i8 %conv4, ptr %6, align 1
+ %7 = load i32, ptr %blkCnt, align 4
+ %dec = add i32 %7, -1
+ store i32 %dec, ptr %blkCnt, align 4
br label %while.cond
while.end: ; preds = %while.cond
- %9 = bitcast i32* %blkCnt to i8*
- call void @llvm.lifetime.end.p0i8(i64 4, i8* %9)
+ call void @llvm.lifetime.end.p0(i64 4, ptr %blkCnt)
ret void
}
@@ -95,66 +90,62 @@ entry:
%max = alloca i32, align 4
%min = alloca i32, align 4
%cleanup.dest.slot = alloca i32, align 4
- store i32 %val, i32* %val.addr, align 4
- store i32 %sat, i32* %sat.addr, align 4
- %0 = load i32, i32* %sat.addr, align 4
+ store i32 %val, ptr %val.addr, align 4
+ store i32 %sat, ptr %sat.addr, align 4
+ %0 = load i32, ptr %sat.addr, align 4
%cmp = icmp uge i32 %0, 1
br i1 %cmp, label %land.lhs.true, label %if.end10
land.lhs.true: ; preds = %entry
- %1 = load i32, i32* %sat.addr, align 4
+ %1 = load i32, ptr %sat.addr, align 4
%cmp1 = icmp ule i32 %1, 32
br i1 %cmp1, label %if.then, label %if.end10
if.then: ; preds = %land.lhs.true
- %2 = bitcast i32* %max to i8*
- call void @llvm.lifetime.start.p0i8(i64 4, i8* %2)
- %3 = load i32, i32* %sat.addr, align 4
- %sub = sub i32 %3, 1
+ call void @llvm.lifetime.start.p0(i64 4, ptr %max)
+ %2 = load i32, ptr %sat.addr, align 4
+ %sub = sub i32 %2, 1
%shl = shl i32 1, %sub
%sub2 = sub i32 %shl, 1
- store i32 %sub2, i32* %max, align 4
- %4 = bitcast i32* %min to i8*
- call void @llvm.lifetime.start.p0i8(i64 4, i8* %4)
- %5 = load i32, i32* %max, align 4
- %sub3 = sub nsw i32 -1, %5
- store i32 %sub3, i32* %min, align 4
- %6 = load i32, i32* %val.addr, align 4
- %7 = load i32, i32* %max, align 4
- %cmp4 = icmp sgt i32 %6, %7
+ store i32 %sub2, ptr %max, align 4
+ call void @llvm.lifetime.start.p0(i64 4, ptr %min)
+ %3 = load i32, ptr %max, align 4
+ %sub3 = sub nsw i32 -1, %3
+ store i32 %sub3, ptr %min, align 4
+ %4 = load i32, ptr %val.addr, align 4
+ %5 = load i32, ptr %max, align 4
+ %cmp4 = icmp sgt i32 %4, %5
br i1 %cmp4, label %if.then5, label %if.else
if.then5: ; preds = %if.then
- %8 = load i32, i32* %max, align 4
- store i32 %8, i32* %retval, align 4
- store i32 1, i32* %cleanup.dest.slot, align 4
+ %6 = load i32, ptr %max, align 4
+ store i32 %6, ptr %retval, align 4
+ store i32 1, ptr %cleanup.dest.slot, align 4
br label %cleanup
if.else: ; preds = %if.then
- %9 = load i32, i32* %val.addr, align 4
- %10 = load i32, i32* %min, align 4
- %cmp6 = icmp slt i32 %9, %10
+ %7 = load i32, ptr %val.addr, align 4
+ %8 = load i32, ptr %min, align 4
+ %cmp6 = icmp slt i32 %7, %8
br i1 %cmp6, label %if.then7, label %if.end
if.then7: ; preds = %if.else
- %11 = load i32, i32* %min, align 4
- store i32 %11, i32* %retval, align 4
- store i32 1, i32* %cleanup.dest.slot, align 4
+ %9 = load i32, ptr %min, align 4
+ store i32 %9, ptr %retval, align 4
+ store i32 1, ptr %cleanup.dest.slot, align 4
br label %cleanup
if.end: ; preds = %if.else
br label %if.end8
if.end8: ; preds = %if.end
- store i32 0, i32* %cleanup.dest.slot, align 4
+ store i32 0, ptr %cleanup.dest.slot, align 4
br label %cleanup
cleanup: ; preds = %if.end8, %if.then7, %if.then5
- %12 = bitcast i32* %min to i8*
- call void @llvm.lifetime.end.p0i8(i64 4, i8* %12)
- %13 = bitcast i32* %max to i8*
- call void @llvm.lifetime.end.p0i8(i64 4, i8* %13)
- %cleanup.dest = load i32, i32* %cleanup.dest.slot, align 4
+ call void @llvm.lifetime.end.p0(i64 4, ptr %min)
+ call void @llvm.lifetime.end.p0(i64 4, ptr %max)
+ %cleanup.dest = load i32, ptr %cleanup.dest.slot, align 4
switch i32 %cleanup.dest, label %unreachable [
i32 0, label %cleanup.cont
i32 1, label %return
@@ -164,20 +155,20 @@ cleanup.cont: ; preds = %cleanup
br label %if.end10
if.end10: ; preds = %cleanup.cont, %land.lhs.true, %entry
- %14 = load i32, i32* %val.addr, align 4
- store i32 %14, i32* %retval, align 4
+ %10 = load i32, ptr %val.addr, align 4
+ store i32 %10, ptr %retval, align 4
br label %return
return: ; preds = %if.end10, %cleanup
- %15 = load i32, i32* %retval, align 4
- ret i32 %15
+ %11 = load i32, ptr %retval, align 4
+ ret i32 %11
unreachable: ; preds = %cleanup
unreachable
}
-declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
-declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)
attributes #0 = { nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8sp,-fp16fml,-hwdiv-arm,-i8mm,-neon,-sb,-sha2,-vfp3,-vfp3sp,-vfp4,-vfp4sp" "unsafe-fp-math"="true" }
attributes #1 = { alwaysinline nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8sp,-fp16fml,-hwdiv-arm,-i8mm,-neon,-sb,-sha2,-vfp3,-vfp3sp,-vfp4,-vfp4sp" "unsafe-fp-math"="true" }
diff --git a/llvm/test/Transforms/PhaseOrdering/ARM/arm_fill_q7.ll b/llvm/test/Transforms/PhaseOrdering/ARM/arm_fill_q7.ll
index 42b74635c6476..5b7622bca6b5c 100644
--- a/llvm/test/Transforms/PhaseOrdering/ARM/arm_fill_q7.ll
+++ b/llvm/test/Transforms/PhaseOrdering/ARM/arm_fill_q7.ll
@@ -9,23 +9,23 @@ target triple = "thumbv6m-none-none-eabi"
; should be deleted, too.
; Function Attrs: nounwind
-define dso_local void @arm_fill_q7(i8 signext %value, i8* %pDst, i32 %blockSize) #0 {
+define dso_local void @arm_fill_q7(i8 signext %value, ptr %pDst, i32 %blockSize) #0 {
; OLDPM-LABEL: @arm_fill_q7(
; OLDPM-NEXT: entry:
; OLDPM-NEXT: [[CMP_NOT20:%.*]] = icmp ult i32 [[BLOCKSIZE:%.*]], 4
; OLDPM-NEXT: br i1 [[CMP_NOT20]], label [[WHILE_END:%.*]], label [[WHILE_BODY_PREHEADER:%.*]]
; OLDPM: while.body.preheader:
; OLDPM-NEXT: [[TMP0:%.*]] = and i32 [[BLOCKSIZE]], -4
-; OLDPM-NEXT: call void @llvm.memset.p0i8.i32(i8* align 1 [[PDST:%.*]], i8 [[VALUE:%.*]], i32 [[TMP0]], i1 false)
-; OLDPM-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, i8* [[PDST]], i32 [[TMP0]]
+; OLDPM-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[PDST:%.*]], i8 [[VALUE:%.*]], i32 [[TMP0]], i1 false)
+; OLDPM-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[PDST]], i32 [[TMP0]]
; OLDPM-NEXT: br label [[WHILE_END]]
; OLDPM: while.end:
-; OLDPM-NEXT: [[PDST_ADDR_0_LCSSA:%.*]] = phi i8* [ [[PDST]], [[ENTRY:%.*]] ], [ [[SCEVGEP]], [[WHILE_BODY_PREHEADER]] ]
+; OLDPM-NEXT: [[PDST_ADDR_0_LCSSA:%.*]] = phi ptr [ [[PDST]], [[ENTRY:%.*]] ], [ [[SCEVGEP]], [[WHILE_BODY_PREHEADER]] ]
; OLDPM-NEXT: [[REM:%.*]] = and i32 [[BLOCKSIZE]], 3
; OLDPM-NEXT: [[CMP14_NOT17:%.*]] = icmp eq i32 [[REM]], 0
; OLDPM-NEXT: br i1 [[CMP14_NOT17]], label [[WHILE_END18:%.*]], label [[WHILE_BODY16_PREHEADER:%.*]]
; OLDPM: while.body16.preheader:
-; OLDPM-NEXT: call void @llvm.memset.p0i8.i32(i8* align 1 [[PDST_ADDR_0_LCSSA]], i8 [[VALUE]], i32 [[REM]], i1 false)
+; OLDPM-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[PDST_ADDR_0_LCSSA]], i8 [[VALUE]], i32 [[REM]], i1 false)
; OLDPM-NEXT: br label [[WHILE_END18]]
; OLDPM: while.end18:
; OLDPM-NEXT: ret void
@@ -36,158 +36,151 @@ define dso_local void @arm_fill_q7(i8 signext %value, i8* %pDst, i32 %blockSize)
; NEWPM-NEXT: br i1 [[CMP_NOT17]], label [[WHILE_END:%.*]], label [[WHILE_BODY_PREHEADER:%.*]]
; NEWPM: while.body.preheader:
; NEWPM-NEXT: [[TMP0:%.*]] = and i32 [[BLOCKSIZE]], -4
-; NEWPM-NEXT: call void @llvm.memset.p0i8.i32(i8* align 1 [[PDST:%.*]], i8 [[VALUE:%.*]], i32 [[TMP0]], i1 false)
-; NEWPM-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, i8* [[PDST]], i32 [[TMP0]]
+; NEWPM-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[PDST:%.*]], i8 [[VALUE:%.*]], i32 [[TMP0]], i1 false)
+; NEWPM-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[PDST]], i32 [[TMP0]]
; NEWPM-NEXT: br label [[WHILE_END]]
; NEWPM: while.end:
-; NEWPM-NEXT: [[PDST_ADDR_0_LCSSA:%.*]] = phi i8* [ [[PDST]], [[ENTRY:%.*]] ], [ [[SCEVGEP]], [[WHILE_BODY_PREHEADER]] ]
+; NEWPM-NEXT: [[PDST_ADDR_0_LCSSA:%.*]] = phi ptr [ [[PDST]], [[ENTRY:%.*]] ], [ [[SCEVGEP]], [[WHILE_BODY_PREHEADER]] ]
; NEWPM-NEXT: [[REM:%.*]] = and i32 [[BLOCKSIZE]], 3
; NEWPM-NEXT: [[CMP14_NOT20:%.*]] = icmp eq i32 [[REM]], 0
; NEWPM-NEXT: br i1 [[CMP14_NOT20]], label [[WHILE_END18:%.*]], label [[WHILE_BODY16_PREHEADER:%.*]]
; NEWPM: while.body16.preheader:
-; NEWPM-NEXT: call void @llvm.memset.p0i8.i32(i8* align 1 [[PDST_ADDR_0_LCSSA]], i8 [[VALUE]], i32 [[REM]], i1 false)
+; NEWPM-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[PDST_ADDR_0_LCSSA]], i8 [[VALUE]], i32 [[REM]], i1 false)
; NEWPM-NEXT: br label [[WHILE_END18]]
; NEWPM: while.end18:
; NEWPM-NEXT: ret void
;
entry:
%value.addr = alloca i8, align 1
- %pDst.addr = alloca i8*, align 4
+ %pDst.addr = alloca ptr, align 4
%blockSize.addr = alloca i32, align 4
%blkCnt = alloca i32, align 4
%packedValue = alloca i32, align 4
- store i8 %value, i8* %value.addr, align 1, !tbaa !3
- store i8* %pDst, i8** %pDst.addr, align 4, !tbaa !6
- store i32 %blockSize, i32* %blockSize.addr, align 4, !tbaa !8
- %0 = bitcast i32* %blkCnt to i8*
- call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #3
- %1 = bitcast i32* %packedValue to i8*
- call void @llvm.lifetime.start.p0i8(i64 4, i8* %1) #3
- %2 = load i8, i8* %value.addr, align 1, !tbaa !3
- %conv = sext i8 %2 to i32
+ store i8 %value, ptr %value.addr, align 1, !tbaa !3
+ store ptr %pDst, ptr %pDst.addr, align 4, !tbaa !6
+ store i32 %blockSize, ptr %blockSize.addr, align 4, !tbaa !8
+ call void @llvm.lifetime.start.p0(i64 4, ptr %blkCnt) #3
+ call void @llvm.lifetime.start.p0(i64 4, ptr %packedValue) #3
+ %0 = load i8, ptr %value.addr, align 1, !tbaa !3
+ %conv = sext i8 %0 to i32
%shl = shl i32 %conv, 0
%and = and i32 %shl, 255
- %3 = load i8, i8* %value.addr, align 1, !tbaa !3
- %conv1 = sext i8 %3 to i32
+ %1 = load i8, ptr %value.addr, align 1, !tbaa !3
+ %conv1 = sext i8 %1 to i32
%shl2 = shl i32 %conv1, 8
%and3 = and i32 %shl2, 65280
%or = or i32 %and, %and3
- %4 = load i8, i8* %value.addr, align 1, !tbaa !3
- %conv4 = sext i8 %4 to i32
+ %2 = load i8, ptr %value.addr, align 1, !tbaa !3
+ %conv4 = sext i8 %2 to i32
%shl5 = shl i32 %conv4, 16
%and6 = and i32 %shl5, 16711680
%or7 = or i32 %or, %and6
- %5 = load i8, i8* %value.addr, align 1, !tbaa !3
- %conv8 = sext i8 %5 to i32
+ %3 = load i8, ptr %value.addr, align 1, !tbaa !3
+ %conv8 = sext i8 %3 to i32
%shl9 = shl i32 %conv8, 24
%and10 = and i32 %shl9, -16777216
%or11 = or i32 %or7, %and10
- store i32 %or11, i32* %packedValue, align 4, !tbaa !8
- %6 = load i32, i32* %blockSize.addr, align 4, !tbaa !8
- %shr = lshr i32 %6, 2
- store i32 %shr, i32* %blkCnt, align 4, !tbaa !8
+ store i32 %or11, ptr %packedValue, align 4, !tbaa !8
+ %4 = load i32, ptr %blockSize.addr, align 4, !tbaa !8
+ %shr = lshr i32 %4, 2
+ store i32 %shr, ptr %blkCnt, align 4, !tbaa !8
br label %while.cond
while.cond: ; preds = %while.body, %entry
- %7 = load i32, i32* %blkCnt, align 4, !tbaa !8
- %cmp = icmp ugt i32 %7, 0
+ %5 = load i32, ptr %blkCnt, align 4, !tbaa !8
+ %cmp = icmp ugt i32 %5, 0
br i1 %cmp, label %while.body, label %while.end
while.body: ; preds = %while.cond
- %8 = load i32, i32* %packedValue, align 4, !tbaa !8
- call void @write_q7x4_ia(i8** %pDst.addr, i32 %8)
- %9 = load i32, i32* %blkCnt, align 4, !tbaa !8
- %dec = add i32 %9, -1
- store i32 %dec, i32* %blkCnt, align 4, !tbaa !8
+ %6 = load i32, ptr %packedValue, align 4, !tbaa !8
+ call void @write_q7x4_ia(ptr %pDst.addr, i32 %6)
+ %7 = load i32, ptr %blkCnt, align 4, !tbaa !8
+ %dec = add i32 %7, -1
+ store i32 %dec, ptr %blkCnt, align 4, !tbaa !8
br label %while.cond, !llvm.loop !10
while.end: ; preds = %while.cond
- %10 = load i32, i32* %blockSize.addr, align 4, !tbaa !8
- %rem = urem i32 %10, 4
- store i32 %rem, i32* %blkCnt, align 4, !tbaa !8
+ %8 = load i32, ptr %blockSize.addr, align 4, !tbaa !8
+ %rem = urem i32 %8, 4
+ store i32 %rem, ptr %blkCnt, align 4, !tbaa !8
br label %while.cond13
while.cond13: ; preds = %while.body16, %while.end
- %11 = load i32, i32* %blkCnt, align 4, !tbaa !8
- %cmp14 = icmp ugt i32 %11, 0
+ %9 = load i32, ptr %blkCnt, align 4, !tbaa !8
+ %cmp14 = icmp ugt i32 %9, 0
br i1 %cmp14, label %while.body16, label %while.end18
while.body16: ; preds = %while.cond13
- %12 = load i8, i8* %value.addr, align 1, !tbaa !3
- %13 = load i8*, i8** %pDst.addr, align 4, !tbaa !6
- %incdec.ptr = getelementptr inbounds i8, i8* %13, i32 1
- store i8* %incdec.ptr, i8** %pDst.addr, align 4, !tbaa !6
- store i8 %12, i8* %13, align 1, !tbaa !3
- %14 = load i32, i32* %blkCnt, align 4, !tbaa !8
- %dec17 = add i32 %14, -1
- store i32 %dec17, i32* %blkCnt, align 4, !tbaa !8
+ %10 = load i8, ptr %value.addr, align 1, !tbaa !3
+ %11 = load ptr, ptr %pDst.addr, align 4, !tbaa !6
+ %incdec.ptr = getelementptr inbounds i8, ptr %11, i32 1
+ store ptr %incdec.ptr, ptr %pDst.addr, align 4, !tbaa !6
+ store i8 %10, ptr %11, align 1, !tbaa !3
+ %12 = load i32, ptr %blkCnt, align 4, !tbaa !8
+ %dec17 = add i32 %12, -1
+ store i32 %dec17, ptr %blkCnt, align 4, !tbaa !8
br label %while.cond13, !llvm.loop !12
while.end18: ; preds = %while.cond13
- %15 = bitcast i32* %packedValue to i8*
- call void @llvm.lifetime.end.p0i8(i64 4, i8* %15) #3
- %16 = bitcast i32* %blkCnt to i8*
- call void @llvm.lifetime.end.p0i8(i64 4, i8* %16) #3
+ call void @llvm.lifetime.end.p0(i64 4, ptr %packedValue) #3
+ call void @llvm.lifetime.end.p0(i64 4, ptr %blkCnt) #3
ret void
}
; Function Attrs: argmemonly nofree nosync nounwind willreturn
-declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1
; Function Attrs: alwaysinline nounwind
-define internal void @write_q7x4_ia(i8** %pQ7, i32 %value) #2 {
+define internal void @write_q7x4_ia(ptr %pQ7, i32 %value) #2 {
entry:
- %pQ7.addr = alloca i8**, align 4
+ %pQ7.addr = alloca ptr, align 4
%value.addr = alloca i32, align 4
%val = alloca i32, align 4
- store i8** %pQ7, i8*** %pQ7.addr, align 4, !tbaa !6
- store i32 %value, i32* %value.addr, align 4, !tbaa !8
- %0 = bitcast i32* %val to i8*
- call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #3
- %1 = load i32, i32* %value.addr, align 4, !tbaa !8
- store i32 %1, i32* %val, align 4, !tbaa !8
- %2 = load i32, i32* %val, align 4, !tbaa !8
- %and = and i32 %2, 255
+ store ptr %pQ7, ptr %pQ7.addr, align 4, !tbaa !6
+ store i32 %value, ptr %value.addr, align 4, !tbaa !8
+ call void @llvm.lifetime.start.p0(i64 4, ptr %val) #3
+ %0 = load i32, ptr %value.addr, align 4, !tbaa !8
+ store i32 %0, ptr %val, align 4, !tbaa !8
+ %1 = load i32, ptr %val, align 4, !tbaa !8
+ %and = and i32 %1, 255
%conv = trunc i32 %and to i8
- %3 = load i8**, i8*** %pQ7.addr, align 4, !tbaa !6
- %4 = load i8*, i8** %3, align 4, !tbaa !6
- %arrayidx = getelementptr inbounds i8, i8* %4, i32 0
- store i8 %conv, i8* %arrayidx, align 1, !tbaa !3
- %5 = load i32, i32* %val, align 4, !tbaa !8
- %shr = ashr i32 %5, 8
+ %2 = load ptr, ptr %pQ7.addr, align 4, !tbaa !6
+ %3 = load ptr, ptr %2, align 4, !tbaa !6
+ store i8 %conv, ptr %3, align 1, !tbaa !3
+ %4 = load i32, ptr %val, align 4, !tbaa !8
+ %shr = ashr i32 %4, 8
%and1 = and i32 %shr, 255
%conv2 = trunc i32 %and1 to i8
- %6 = load i8**, i8*** %pQ7.addr, align 4, !tbaa !6
- %7 = load i8*, i8** %6, align 4, !tbaa !6
- %arrayidx3 = getelementptr inbounds i8, i8* %7, i32 1
- store i8 %conv2, i8* %arrayidx3, align 1, !tbaa !3
- %8 = load i32, i32* %val, align 4, !tbaa !8
- %shr4 = ashr i32 %8, 16
+ %5 = load ptr, ptr %pQ7.addr, align 4, !tbaa !6
+ %6 = load ptr, ptr %5, align 4, !tbaa !6
+ %arrayidx3 = getelementptr inbounds i8, ptr %6, i32 1
+ store i8 %conv2, ptr %arrayidx3, align 1, !tbaa !3
+ %7 = load i32, ptr %val, align 4, !tbaa !8
+ %shr4 = ashr i32 %7, 16
%and5 = and i32 %shr4, 255
%conv6 = trunc i32 %and5 to i8
- %9 = load i8**, i8*** %pQ7.addr, align 4, !tbaa !6
- %10 = load i8*, i8** %9, align 4, !tbaa !6
- %arrayidx7 = getelementptr inbounds i8, i8* %10, i32 2
- store i8 %conv6, i8* %arrayidx7, align 1, !tbaa !3
- %11 = load i32, i32* %val, align 4, !tbaa !8
- %shr8 = ashr i32 %11, 24
+ %8 = load ptr, ptr %pQ7.addr, align 4, !tbaa !6
+ %9 = load ptr, ptr %8, align 4, !tbaa !6
+ %arrayidx7 = getelementptr inbounds i8, ptr %9, i32 2
+ store i8 %conv6, ptr %arrayidx7, align 1, !tbaa !3
+ %10 = load i32, ptr %val, align 4, !tbaa !8
+ %shr8 = ashr i32 %10, 24
%and9 = and i32 %shr8, 255
%conv10 = trunc i32 %and9 to i8
- %12 = load i8**, i8*** %pQ7.addr, align 4, !tbaa !6
- %13 = load i8*, i8** %12, align 4, !tbaa !6
- %arrayidx11 = getelementptr inbounds i8, i8* %13, i32 3
- store i8 %conv10, i8* %arrayidx11, align 1, !tbaa !3
- %14 = load i8**, i8*** %pQ7.addr, align 4, !tbaa !6
- %15 = load i8*, i8** %14, align 4, !tbaa !6
- %add.ptr = getelementptr inbounds i8, i8* %15, i32 4
- store i8* %add.ptr, i8** %14, align 4, !tbaa !6
- %16 = bitcast i32* %val to i8*
- call void @llvm.lifetime.end.p0i8(i64 4, i8* %16) #3
+ %11 = load ptr, ptr %pQ7.addr, align 4, !tbaa !6
+ %12 = load ptr, ptr %11, align 4, !tbaa !6
+ %arrayidx11 = getelementptr inbounds i8, ptr %12, i32 3
+ store i8 %conv10, ptr %arrayidx11, align 1, !tbaa !3
+ %13 = load ptr, ptr %pQ7.addr, align 4, !tbaa !6
+ %14 = load ptr, ptr %13, align 4, !tbaa !6
+ %add.ptr = getelementptr inbounds i8, ptr %14, i32 4
+ store ptr %add.ptr, ptr %13, align 4, !tbaa !6
+ call void @llvm.lifetime.end.p0(i64 4, ptr %val) #3
ret void
}
; Function Attrs: argmemonly nofree nosync nounwind willreturn
-declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1
attributes #0 = { nounwind "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m0plus" "target-features"="+armv6-m,+strict-align,+thumb-mode,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-dotprod,-dsp,-fp16fml,-fullfp16,-hwdiv,-hwdiv-arm,-i8mm,-lob,-mve,-mve.fp,-ras,-sb,-sha2" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { argmemonly nofree nosync nounwind willreturn }
diff --git a/llvm/test/Transforms/PhaseOrdering/ARM/arm_mult_q15.ll b/llvm/test/Transforms/PhaseOrdering/ARM/arm_mult_q15.ll
index ff18722af99fe..7cbce461a4924 100644
--- a/llvm/test/Transforms/PhaseOrdering/ARM/arm_mult_q15.ll
+++ b/llvm/test/Transforms/PhaseOrdering/ARM/arm_mult_q15.ll
@@ -8,125 +8,126 @@
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi"
-define void @arm_mult_q15(i16* %pSrcA, i16* %pSrcB, i16 * noalias %pDst, i32 %blockSize) #0 {
+define void @arm_mult_q15(ptr %pSrcA, ptr %pSrcB, ptr noalias %pDst, i32 %blockSize) #0 {
; CHECK-LABEL: @arm_mult_q15(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CMP_NOT3:%.*]] = icmp eq i32 [[BLOCKSIZE:%.*]], 0
-; CHECK-NEXT: br i1 [[CMP_NOT3]], label [[WHILE_END:%.*]], label [[WHILE_BODY_PREHEADER:%.*]]
+; CHECK-NEXT: [[CMP_NOT2:%.*]] = icmp eq i32 [[BLOCKSIZE:%.*]], 0
+; CHECK-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_END:%.*]], label [[WHILE_BODY_PREHEADER:%.*]]
; CHECK: while.body.preheader:
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[BLOCKSIZE]], 8
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[WHILE_BODY_PREHEADER17:%.*]], label [[VECTOR_PH:%.*]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[WHILE_BODY_PREHEADER16:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[BLOCKSIZE]], -8
; CHECK-NEXT: [[IND_END:%.*]] = and i32 [[BLOCKSIZE]], 7
-; CHECK-NEXT: [[IND_END8:%.*]] = getelementptr i16, i16* [[PSRCA:%.*]], i32 [[N_VEC]]
-; CHECK-NEXT: [[IND_END10:%.*]] = getelementptr i16, i16* [[PDST:%.*]], i32 [[N_VEC]]
-; CHECK-NEXT: [[IND_END12:%.*]] = getelementptr i16, i16* [[PSRCB:%.*]], i32 [[N_VEC]]
+; CHECK-NEXT: [[TMP0:%.*]] = shl i32 [[N_VEC]], 1
+; CHECK-NEXT: [[IND_END7:%.*]] = getelementptr i8, ptr [[PSRCA:%.*]], i32 [[TMP0]]
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[N_VEC]], 1
+; CHECK-NEXT: [[IND_END9:%.*]] = getelementptr i8, ptr [[PDST:%.*]], i32 [[TMP1]]
+; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[N_VEC]], 1
+; CHECK-NEXT: [[IND_END11:%.*]] = getelementptr i8, ptr [[PSRCB:%.*]], i32 [[TMP2]]
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i16, i16* [[PSRCA]], i32 [[INDEX]]
-; CHECK-NEXT: [[NEXT_GEP14:%.*]] = getelementptr i16, i16* [[PDST]], i32 [[INDEX]]
-; CHECK-NEXT: [[NEXT_GEP15:%.*]] = getelementptr i16, i16* [[PSRCB]], i32 [[INDEX]]
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast i16* [[NEXT_GEP]] to <8 x i16>*
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i16>, <8 x i16>* [[TMP0]], align 2
-; CHECK-NEXT: [[TMP1:%.*]] = sext <8 x i16> [[WIDE_LOAD]] to <8 x i32>
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast i16* [[NEXT_GEP15]] to <8 x i16>*
-; CHECK-NEXT: [[WIDE_LOAD16:%.*]] = load <8 x i16>, <8 x i16>* [[TMP2]], align 2
-; CHECK-NEXT: [[TMP3:%.*]] = sext <8 x i16> [[WIDE_LOAD16]] to <8 x i32>
-; CHECK-NEXT: [[TMP4:%.*]] = mul nsw <8 x i32> [[TMP3]], [[TMP1]]
-; CHECK-NEXT: [[TMP5:%.*]] = ashr <8 x i32> [[TMP4]], <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
-; CHECK-NEXT: [[TMP6:%.*]] = tail call <8 x i32> @llvm.smin.v8i32(<8 x i32> [[TMP5]], <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>)
-; CHECK-NEXT: [[TMP7:%.*]] = trunc <8 x i32> [[TMP6]] to <8 x i16>
-; CHECK-NEXT: [[TMP8:%.*]] = bitcast i16* [[NEXT_GEP14]] to <8 x i16>*
-; CHECK-NEXT: store <8 x i16> [[TMP7]], <8 x i16>* [[TMP8]], align 2
+; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[INDEX]], 1
+; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PSRCA]], i32 [[TMP3]]
+; CHECK-NEXT: [[TMP4:%.*]] = shl i32 [[INDEX]], 1
+; CHECK-NEXT: [[NEXT_GEP13:%.*]] = getelementptr i8, ptr [[PDST]], i32 [[TMP4]]
+; CHECK-NEXT: [[TMP5:%.*]] = shl i32 [[INDEX]], 1
+; CHECK-NEXT: [[NEXT_GEP14:%.*]] = getelementptr i8, ptr [[PSRCB]], i32 [[TMP5]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i16>, ptr [[NEXT_GEP]], align 2
+; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i16> [[WIDE_LOAD]] to <8 x i32>
+; CHECK-NEXT: [[WIDE_LOAD15:%.*]] = load <8 x i16>, ptr [[NEXT_GEP14]], align 2
+; CHECK-NEXT: [[TMP7:%.*]] = sext <8 x i16> [[WIDE_LOAD15]] to <8 x i32>
+; CHECK-NEXT: [[TMP8:%.*]] = mul nsw <8 x i32> [[TMP7]], [[TMP6]]
+; CHECK-NEXT: [[TMP9:%.*]] = ashr <8 x i32> [[TMP8]], <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT: [[TMP10:%.*]] = tail call <8 x i32> @llvm.smin.v8i32(<8 x i32> [[TMP9]], <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>)
+; CHECK-NEXT: [[TMP11:%.*]] = trunc <8 x i32> [[TMP10]] to <8 x i16>
+; CHECK-NEXT: store <8 x i16> [[TMP11]], ptr [[NEXT_GEP13]], align 2
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
-; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: middle.block:
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N_VEC]], [[BLOCKSIZE]]
-; CHECK-NEXT: br i1 [[CMP_N]], label [[WHILE_END]], label [[WHILE_BODY_PREHEADER17]]
-; CHECK: while.body.preheader17:
-; CHECK-NEXT: [[BLKCNT_07_PH:%.*]] = phi i32 [ [[BLOCKSIZE]], [[WHILE_BODY_PREHEADER]] ], [ [[IND_END]], [[MIDDLE_BLOCK]] ]
-; CHECK-NEXT: [[PSRCA_ADDR_06_PH:%.*]] = phi i16* [ [[PSRCA]], [[WHILE_BODY_PREHEADER]] ], [ [[IND_END8]], [[MIDDLE_BLOCK]] ]
-; CHECK-NEXT: [[PDST_ADDR_05_PH:%.*]] = phi i16* [ [[PDST]], [[WHILE_BODY_PREHEADER]] ], [ [[IND_END10]], [[MIDDLE_BLOCK]] ]
-; CHECK-NEXT: [[PSRCB_ADDR_04_PH:%.*]] = phi i16* [ [[PSRCB]], [[WHILE_BODY_PREHEADER]] ], [ [[IND_END12]], [[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: br i1 [[CMP_N]], label [[WHILE_END]], label [[WHILE_BODY_PREHEADER16]]
+; CHECK: while.body.preheader16:
+; CHECK-NEXT: [[BLKCNT_06_PH:%.*]] = phi i32 [ [[BLOCKSIZE]], [[WHILE_BODY_PREHEADER]] ], [ [[IND_END]], [[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[PSRCA_ADDR_05_PH:%.*]] = phi ptr [ [[PSRCA]], [[WHILE_BODY_PREHEADER]] ], [ [[IND_END7]], [[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[PDST_ADDR_04_PH:%.*]] = phi ptr [ [[PDST]], [[WHILE_BODY_PREHEADER]] ], [ [[IND_END9]], [[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: [[PSRCB_ADDR_03_PH:%.*]] = phi ptr [ [[PSRCB]], [[WHILE_BODY_PREHEADER]] ], [ [[IND_END11]], [[MIDDLE_BLOCK]] ]
; CHECK-NEXT: br label [[WHILE_BODY:%.*]]
; CHECK: while.body:
-; CHECK-NEXT: [[BLKCNT_07:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], [ [[BLKCNT_07_PH]], [[WHILE_BODY_PREHEADER17]] ]
-; CHECK-NEXT: [[PSRCA_ADDR_06:%.*]] = phi i16* [ [[INCDEC_PTR:%.*]], [[WHILE_BODY]] ], [ [[PSRCA_ADDR_06_PH]], [[WHILE_BODY_PREHEADER17]] ]
-; CHECK-NEXT: [[PDST_ADDR_05:%.*]] = phi i16* [ [[INCDEC_PTR4:%.*]], [[WHILE_BODY]] ], [ [[PDST_ADDR_05_PH]], [[WHILE_BODY_PREHEADER17]] ]
-; CHECK-NEXT: [[PSRCB_ADDR_04:%.*]] = phi i16* [ [[INCDEC_PTR1:%.*]], [[WHILE_BODY]] ], [ [[PSRCB_ADDR_04_PH]], [[WHILE_BODY_PREHEADER17]] ]
-; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i16, i16* [[PSRCA_ADDR_06]], i32 1
-; CHECK-NEXT: [[TMP10:%.*]] = load i16, i16* [[PSRCA_ADDR_06]], align 2
-; CHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32
-; CHECK-NEXT: [[INCDEC_PTR1]] = getelementptr inbounds i16, i16* [[PSRCB_ADDR_04]], i32 1
-; CHECK-NEXT: [[TMP11:%.*]] = load i16, i16* [[PSRCB_ADDR_04]], align 2
-; CHECK-NEXT: [[CONV2:%.*]] = sext i16 [[TMP11]] to i32
+; CHECK-NEXT: [[BLKCNT_06:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], [ [[BLKCNT_06_PH]], [[WHILE_BODY_PREHEADER16]] ]
+; CHECK-NEXT: [[PSRCA_ADDR_05:%.*]] = phi ptr [ [[INCDEC_PTR:%.*]], [[WHILE_BODY]] ], [ [[PSRCA_ADDR_05_PH]], [[WHILE_BODY_PREHEADER16]] ]
+; CHECK-NEXT: [[PDST_ADDR_04:%.*]] = phi ptr [ [[INCDEC_PTR4:%.*]], [[WHILE_BODY]] ], [ [[PDST_ADDR_04_PH]], [[WHILE_BODY_PREHEADER16]] ]
+; CHECK-NEXT: [[PSRCB_ADDR_03:%.*]] = phi ptr [ [[INCDEC_PTR1:%.*]], [[WHILE_BODY]] ], [ [[PSRCB_ADDR_03_PH]], [[WHILE_BODY_PREHEADER16]] ]
+; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i16, ptr [[PSRCA_ADDR_05]], i32 1
+; CHECK-NEXT: [[TMP13:%.*]] = load i16, ptr [[PSRCA_ADDR_05]], align 2
+; CHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i32
+; CHECK-NEXT: [[INCDEC_PTR1]] = getelementptr inbounds i16, ptr [[PSRCB_ADDR_03]], i32 1
+; CHECK-NEXT: [[TMP14:%.*]] = load i16, ptr [[PSRCB_ADDR_03]], align 2
+; CHECK-NEXT: [[CONV2:%.*]] = sext i16 [[TMP14]] to i32
; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[CONV2]], [[CONV]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[MUL]], 15
-; CHECK-NEXT: [[TMP12:%.*]] = tail call i32 @llvm.smin.i32(i32 [[SHR]], i32 32767)
-; CHECK-NEXT: [[CONV3:%.*]] = trunc i32 [[TMP12]] to i16
-; CHECK-NEXT: [[INCDEC_PTR4]] = getelementptr inbounds i16, i16* [[PDST_ADDR_05]], i32 1
-; CHECK-NEXT: store i16 [[CONV3]], i16* [[PDST_ADDR_05]], align 2
-; CHECK-NEXT: [[DEC]] = add i32 [[BLKCNT_07]], -1
+; CHECK-NEXT: [[TMP15:%.*]] = tail call i32 @llvm.smin.i32(i32 [[SHR]], i32 32767)
+; CHECK-NEXT: [[CONV3:%.*]] = trunc i32 [[TMP15]] to i16
+; CHECK-NEXT: [[INCDEC_PTR4]] = getelementptr inbounds i16, ptr [[PDST_ADDR_04]], i32 1
+; CHECK-NEXT: store i16 [[CONV3]], ptr [[PDST_ADDR_04]], align 2
+; CHECK-NEXT: [[DEC]] = add i32 [[BLKCNT_06]], -1
; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[DEC]], 0
; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END]], label [[WHILE_BODY]], !llvm.loop [[LOOP2:![0-9]+]]
; CHECK: while.end:
; CHECK-NEXT: ret void
;
entry:
- %pSrcA.addr = alloca i16*, align 4
- %pSrcB.addr = alloca i16*, align 4
- %pDst.addr = alloca i16*, align 4
+ %pSrcA.addr = alloca ptr, align 4
+ %pSrcB.addr = alloca ptr, align 4
+ %pDst.addr = alloca ptr, align 4
%blockSize.addr = alloca i32, align 4
%blkCnt = alloca i32, align 4
- store i16* %pSrcA, i16** %pSrcA.addr, align 4
- store i16* %pSrcB, i16** %pSrcB.addr, align 4
- store i16* %pDst, i16** %pDst.addr, align 4
- store i32 %blockSize, i32* %blockSize.addr, align 4
- %0 = bitcast i32* %blkCnt to i8*
- call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #3
- %1 = load i32, i32* %blockSize.addr, align 4
- store i32 %1, i32* %blkCnt, align 4
+ store ptr %pSrcA, ptr %pSrcA.addr, align 4
+ store ptr %pSrcB, ptr %pSrcB.addr, align 4
+ store ptr %pDst, ptr %pDst.addr, align 4
+ store i32 %blockSize, ptr %blockSize.addr, align 4
+ call void @llvm.lifetime.start.p0(i64 4, ptr %blkCnt) #3
+ %0 = load i32, ptr %blockSize.addr, align 4
+ store i32 %0, ptr %blkCnt, align 4
br label %while.cond
while.cond: ; preds = %while.body, %entry
- %2 = load i32, i32* %blkCnt, align 4
- %cmp = icmp ugt i32 %2, 0
+ %1 = load i32, ptr %blkCnt, align 4
+ %cmp = icmp ugt i32 %1, 0
br i1 %cmp, label %while.body, label %while.end
while.body: ; preds = %while.cond
- %3 = load i16*, i16** %pSrcA.addr, align 4
- %incdec.ptr = getelementptr inbounds i16, i16* %3, i32 1
- store i16* %incdec.ptr, i16** %pSrcA.addr, align 4
- %4 = load i16, i16* %3, align 2
- %conv = sext i16 %4 to i32
- %5 = load i16*, i16** %pSrcB.addr, align 4
- %incdec.ptr1 = getelementptr inbounds i16, i16* %5, i32 1
- store i16* %incdec.ptr1, i16** %pSrcB.addr, align 4
- %6 = load i16, i16* %5, align 2
- %conv2 = sext i16 %6 to i32
+ %2 = load ptr, ptr %pSrcA.addr, align 4
+ %incdec.ptr = getelementptr inbounds i16, ptr %2, i32 1
+ store ptr %incdec.ptr, ptr %pSrcA.addr, align 4
+ %3 = load i16, ptr %2, align 2
+ %conv = sext i16 %3 to i32
+ %4 = load ptr, ptr %pSrcB.addr, align 4
+ %incdec.ptr1 = getelementptr inbounds i16, ptr %4, i32 1
+ store ptr %incdec.ptr1, ptr %pSrcB.addr, align 4
+ %5 = load i16, ptr %4, align 2
+ %conv2 = sext i16 %5 to i32
%mul = mul nsw i32 %conv, %conv2
%shr = ashr i32 %mul, 15
%call = call i32 @__SSAT(i32 %shr, i32 16)
%conv3 = trunc i32 %call to i16
- %7 = load i16*, i16** %pDst.addr, align 4
- %incdec.ptr4 = getelementptr inbounds i16, i16* %7, i32 1
- store i16* %incdec.ptr4, i16** %pDst.addr, align 4
- store i16 %conv3, i16* %7, align 2
- %8 = load i32, i32* %blkCnt, align 4
- %dec = add i32 %8, -1
- store i32 %dec, i32* %blkCnt, align 4
+ %6 = load ptr, ptr %pDst.addr, align 4
+ %incdec.ptr4 = getelementptr inbounds i16, ptr %6, i32 1
+ store ptr %incdec.ptr4, ptr %pDst.addr, align 4
+ store i16 %conv3, ptr %6, align 2
+ %7 = load i32, ptr %blkCnt, align 4
+ %dec = add i32 %7, -1
+ store i32 %dec, ptr %blkCnt, align 4
br label %while.cond
while.end: ; preds = %while.cond
- %9 = bitcast i32* %blkCnt to i8*
- call void @llvm.lifetime.end.p0i8(i64 4, i8* %9) #3
+ call void @llvm.lifetime.end.p0(i64 4, ptr %blkCnt) #3
ret void
}
-declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1
define internal i32 @__SSAT(i32 %val, i32 %sat) #2 {
entry:
@@ -136,66 +137,62 @@ entry:
%max = alloca i32, align 4
%min = alloca i32, align 4
%cleanup.dest.slot = alloca i32, align 4
- store i32 %val, i32* %val.addr, align 4
- store i32 %sat, i32* %sat.addr, align 4
- %0 = load i32, i32* %sat.addr, align 4
+ store i32 %val, ptr %val.addr, align 4
+ store i32 %sat, ptr %sat.addr, align 4
+ %0 = load i32, ptr %sat.addr, align 4
%cmp = icmp uge i32 %0, 1
br i1 %cmp, label %land.lhs.true, label %if.end10
land.lhs.true: ; preds = %entry
- %1 = load i32, i32* %sat.addr, align 4
+ %1 = load i32, ptr %sat.addr, align 4
%cmp1 = icmp ule i32 %1, 32
br i1 %cmp1, label %if.then, label %if.end10
if.then: ; preds = %land.lhs.true
- %2 = bitcast i32* %max to i8*
- call void @llvm.lifetime.start.p0i8(i64 4, i8* %2) #3
- %3 = load i32, i32* %sat.addr, align 4
- %sub = sub i32 %3, 1
+ call void @llvm.lifetime.start.p0(i64 4, ptr %max) #3
+ %2 = load i32, ptr %sat.addr, align 4
+ %sub = sub i32 %2, 1
%shl = shl i32 1, %sub
%sub2 = sub i32 %shl, 1
- store i32 %sub2, i32* %max, align 4
- %4 = bitcast i32* %min to i8*
- call void @llvm.lifetime.start.p0i8(i64 4, i8* %4) #3
- %5 = load i32, i32* %max, align 4
- %sub3 = sub nsw i32 -1, %5
- store i32 %sub3, i32* %min, align 4
- %6 = load i32, i32* %val.addr, align 4
- %7 = load i32, i32* %max, align 4
- %cmp4 = icmp sgt i32 %6, %7
+ store i32 %sub2, ptr %max, align 4
+ call void @llvm.lifetime.start.p0(i64 4, ptr %min) #3
+ %3 = load i32, ptr %max, align 4
+ %sub3 = sub nsw i32 -1, %3
+ store i32 %sub3, ptr %min, align 4
+ %4 = load i32, ptr %val.addr, align 4
+ %5 = load i32, ptr %max, align 4
+ %cmp4 = icmp sgt i32 %4, %5
br i1 %cmp4, label %if.then5, label %if.else
if.then5: ; preds = %if.then
- %8 = load i32, i32* %max, align 4
- store i32 %8, i32* %retval, align 4
- store i32 1, i32* %cleanup.dest.slot, align 4
+ %6 = load i32, ptr %max, align 4
+ store i32 %6, ptr %retval, align 4
+ store i32 1, ptr %cleanup.dest.slot, align 4
br label %cleanup
if.else: ; preds = %if.then
- %9 = load i32, i32* %val.addr, align 4
- %10 = load i32, i32* %min, align 4
- %cmp6 = icmp slt i32 %9, %10
+ %7 = load i32, ptr %val.addr, align 4
+ %8 = load i32, ptr %min, align 4
+ %cmp6 = icmp slt i32 %7, %8
br i1 %cmp6, label %if.then7, label %if.end
if.then7: ; preds = %if.else
- %11 = load i32, i32* %min, align 4
- store i32 %11, i32* %retval, align 4
- store i32 1, i32* %cleanup.dest.slot, align 4
+ %9 = load i32, ptr %min, align 4
+ store i32 %9, ptr %retval, align 4
+ store i32 1, ptr %cleanup.dest.slot, align 4
br label %cleanup
if.end: ; preds = %if.else
br label %if.end8
if.end8: ; preds = %if.end
- store i32 0, i32* %cleanup.dest.slot, align 4
+ store i32 0, ptr %cleanup.dest.slot, align 4
br label %cleanup
cleanup: ; preds = %if.end8, %if.then7, %if.then5
- %12 = bitcast i32* %min to i8*
- call void @llvm.lifetime.end.p0i8(i64 4, i8* %12) #3
- %13 = bitcast i32* %max to i8*
- call void @llvm.lifetime.end.p0i8(i64 4, i8* %13) #3
- %cleanup.dest = load i32, i32* %cleanup.dest.slot, align 4
+ call void @llvm.lifetime.end.p0(i64 4, ptr %min) #3
+ call void @llvm.lifetime.end.p0(i64 4, ptr %max) #3
+ %cleanup.dest = load i32, ptr %cleanup.dest.slot, align 4
switch i32 %cleanup.dest, label %unreachable [
i32 0, label %cleanup.cont
i32 1, label %return
@@ -205,19 +202,19 @@ cleanup.cont: ; preds = %cleanup
br label %if.end10
if.end10: ; preds = %cleanup.cont, %land.lhs.true, %entry
- %14 = load i32, i32* %val.addr, align 4
- store i32 %14, i32* %retval, align 4
+ %10 = load i32, ptr %val.addr, align 4
+ store i32 %10, ptr %retval, align 4
br label %return
return: ; preds = %if.end10, %cleanup
- %15 = load i32, i32* %retval, align 4
- ret i32 %15
+ %11 = load i32, ptr %retval, align 4
+ ret i32 %11
unreachable: ; preds = %cleanup
unreachable
}
-declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1
attributes #0 = { nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8sp,-fp16fml,-hwdiv-arm,-i8mm,-neon,-sb,-sha2,-vfp3,-vfp3sp,-vfp4,-vfp4sp" "unsafe-fp-math"="true" }
attributes #1 = { argmemonly nofree nosync nounwind willreturn }
diff --git a/llvm/test/Transforms/PhaseOrdering/PR6627.ll b/llvm/test/Transforms/PhaseOrdering/PR6627.ll
index 2774d208352cc..ccf089863265c 100644
--- a/llvm/test/Transforms/PhaseOrdering/PR6627.ll
+++ b/llvm/test/Transforms/PhaseOrdering/PR6627.ll
@@ -5,32 +5,31 @@ declare i32 @doo(...)
; PR6627 - This whole nasty sequence should be flattened down to a single
; 32-bit comparison.
-define void @test2(i8* %arrayidx) nounwind ssp {
+define void @test2(ptr %arrayidx) nounwind ssp {
entry:
- %xx = bitcast i8* %arrayidx to i32*
- %x1 = load i32, i32* %xx, align 4
+ %x1 = load i32, ptr %arrayidx, align 4
%tmp = trunc i32 %x1 to i8
%conv = zext i8 %tmp to i32
%cmp = icmp eq i32 %conv, 127
br i1 %cmp, label %land.lhs.true, label %if.end
land.lhs.true: ; preds = %entry
- %arrayidx4 = getelementptr inbounds i8, i8* %arrayidx, i64 1
- %tmp5 = load i8, i8* %arrayidx4, align 1
+ %arrayidx4 = getelementptr inbounds i8, ptr %arrayidx, i64 1
+ %tmp5 = load i8, ptr %arrayidx4, align 1
%conv6 = zext i8 %tmp5 to i32
%cmp7 = icmp eq i32 %conv6, 69
br i1 %cmp7, label %land.lhs.true9, label %if.end
land.lhs.true9: ; preds = %land.lhs.true
- %arrayidx12 = getelementptr inbounds i8, i8* %arrayidx, i64 2
- %tmp13 = load i8, i8* %arrayidx12, align 1
+ %arrayidx12 = getelementptr inbounds i8, ptr %arrayidx, i64 2
+ %tmp13 = load i8, ptr %arrayidx12, align 1
%conv14 = zext i8 %tmp13 to i32
%cmp15 = icmp eq i32 %conv14, 76
br i1 %cmp15, label %land.lhs.true17, label %if.end
land.lhs.true17: ; preds = %land.lhs.true9
- %arrayidx20 = getelementptr inbounds i8, i8* %arrayidx, i64 3
- %tmp21 = load i8, i8* %arrayidx20, align 1
+ %arrayidx20 = getelementptr inbounds i8, ptr %arrayidx, i64 3
+ %tmp21 = load i8, ptr %arrayidx20, align 1
%conv22 = zext i8 %tmp21 to i32
%cmp23 = icmp eq i32 %conv22, 70
br i1 %cmp23, label %if.then, label %if.end
@@ -43,7 +42,7 @@ if.end:
ret void
; CHECK-LABEL: @test2(
-; CHECK: %x1 = load i32, i32* %xx, align 4
+; CHECK: %x1 = load i32, ptr %arrayidx, align 4
; CHECK-NEXT: icmp eq i32 %x1, 1179403647
; CHECK-NEXT: br i1 {{.*}}, label %if.then, label %if.end
}
@@ -51,30 +50,30 @@ if.end:
; PR6627 - This should all be flattened down to one compare. This is the same
; as test2, except that the initial load is done as an i8 instead of i32, thus
; requiring widening.
-define void @test2a(i8* %arrayidx) nounwind ssp {
+define void @test2a(ptr %arrayidx) nounwind ssp {
entry:
- %x1 = load i8, i8* %arrayidx, align 4
+ %x1 = load i8, ptr %arrayidx, align 4
%conv = zext i8 %x1 to i32
%cmp = icmp eq i32 %conv, 127
br i1 %cmp, label %land.lhs.true, label %if.end
land.lhs.true: ; preds = %entry
- %arrayidx4 = getelementptr inbounds i8, i8* %arrayidx, i64 1
- %tmp5 = load i8, i8* %arrayidx4, align 1
+ %arrayidx4 = getelementptr inbounds i8, ptr %arrayidx, i64 1
+ %tmp5 = load i8, ptr %arrayidx4, align 1
%conv6 = zext i8 %tmp5 to i32
%cmp7 = icmp eq i32 %conv6, 69
br i1 %cmp7, label %land.lhs.true9, label %if.end
land.lhs.true9: ; preds = %land.lhs.true
- %arrayidx12 = getelementptr inbounds i8, i8* %arrayidx, i64 2
- %tmp13 = load i8, i8* %arrayidx12, align 1
+ %arrayidx12 = getelementptr inbounds i8, ptr %arrayidx, i64 2
+ %tmp13 = load i8, ptr %arrayidx12, align 1
%conv14 = zext i8 %tmp13 to i32
%cmp15 = icmp eq i32 %conv14, 76
br i1 %cmp15, label %land.lhs.true17, label %if.end
land.lhs.true17: ; preds = %land.lhs.true9
- %arrayidx20 = getelementptr inbounds i8, i8* %arrayidx, i64 3
- %tmp21 = load i8, i8* %arrayidx20, align 1
+ %arrayidx20 = getelementptr inbounds i8, ptr %arrayidx, i64 3
+ %tmp21 = load i8, ptr %arrayidx20, align 1
%conv22 = zext i8 %tmp21 to i32
%cmp23 = icmp eq i32 %conv22, 70
br i1 %cmp23, label %if.then, label %if.end
@@ -87,7 +86,7 @@ if.end:
ret void
; CHECK-LABEL: @test2a(
-; CHECK: %x1 = load i32, i32* {{.*}}, align 4
+; CHECK: %x1 = load i32, ptr {{.*}}, align 4
; CHECK-NEXT: icmp eq i32 %x1, 1179403647
; CHECK-NEXT: br i1 {{.*}}, label %if.then, label %if.end
}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/SROA-after-final-loop-unrolling-2.ll b/llvm/test/Transforms/PhaseOrdering/X86/SROA-after-final-loop-unrolling-2.ll
index 818af8a596c58..5c229606a05a1 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/SROA-after-final-loop-unrolling-2.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/SROA-after-final-loop-unrolling-2.ll
@@ -120,9 +120,8 @@ bb:
store ptr %arg, ptr %i, align 8, !tbaa !9
store i64 %arg1, ptr %i2, align 8, !tbaa !15
%i3 = load ptr, ptr %i, align 8
- %i4 = getelementptr inbounds %t0, ptr %i3, i32 0, i32 0
%i5 = load i64, ptr %i2, align 8, !tbaa !15
- %i6 = call noundef nonnull align 4 dereferenceable(4) ptr @widget(ptr noundef nonnull align 4 dereferenceable(8) %i4, i64 noundef %i5) #3
+ %i6 = call noundef nonnull align 4 dereferenceable(4) ptr @widget(ptr noundef nonnull align 4 dereferenceable(8) %i3, i64 noundef %i5) #3
ret ptr %i6
}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/SROA-after-loop-unrolling.ll b/llvm/test/Transforms/PhaseOrdering/X86/SROA-after-loop-unrolling.ll
index 37994ea4d86ef..c6dc7b374b00f 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/SROA-after-loop-unrolling.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/SROA-after-loop-unrolling.ll
@@ -41,162 +41,142 @@ define dso_local void @_Z3fooi(i32 %cnt) {
entry:
%cnt.addr = alloca i32
%arr = alloca %"struct.std::array"
- %__range1 = alloca %"struct.std::array"*
- %__begin1 = alloca i32*
- %__end1 = alloca i32*
- %elt = alloca i32*
- %__range12 = alloca %"struct.std::array"*
- %__begin13 = alloca i32*
- %__end15 = alloca i32*
- %elt11 = alloca i32*
- store i32 %cnt, i32* %cnt.addr
- %0 = bitcast %"struct.std::array"* %arr to i8*
- call void @llvm.lifetime.start.p0i8(i64 24, i8* %0)
- %1 = bitcast %"struct.std::array"** %__range1 to i8*
- call void @llvm.lifetime.start.p0i8(i64 8, i8* %1)
- store %"struct.std::array"* %arr, %"struct.std::array"** %__range1
- %2 = bitcast i32** %__begin1 to i8*
- call void @llvm.lifetime.start.p0i8(i64 8, i8* %2)
- %3 = load %"struct.std::array"*, %"struct.std::array"** %__range1
- %call = call i32* @_ZNSt5arrayIiLm6EE5beginEv(%"struct.std::array"* %3)
- store i32* %call, i32** %__begin1
- %4 = bitcast i32** %__end1 to i8*
- call void @llvm.lifetime.start.p0i8(i64 8, i8* %4)
- %5 = load %"struct.std::array"*, %"struct.std::array"** %__range1
- %call1 = call i32* @_ZNSt5arrayIiLm6EE3endEv(%"struct.std::array"* %5)
- store i32* %call1, i32** %__end1
+ %__range1 = alloca ptr
+ %__begin1 = alloca ptr
+ %__end1 = alloca ptr
+ %elt = alloca ptr
+ %__range12 = alloca ptr
+ %__begin13 = alloca ptr
+ %__end15 = alloca ptr
+ %elt11 = alloca ptr
+ store i32 %cnt, ptr %cnt.addr
+ call void @llvm.lifetime.start.p0(i64 24, ptr %arr)
+ call void @llvm.lifetime.start.p0(i64 8, ptr %__range1)
+ store ptr %arr, ptr %__range1
+ call void @llvm.lifetime.start.p0(i64 8, ptr %__begin1)
+ %0 = load ptr, ptr %__range1
+ %call = call ptr @_ZNSt5arrayIiLm6EE5beginEv(ptr %0)
+ store ptr %call, ptr %__begin1
+ call void @llvm.lifetime.start.p0(i64 8, ptr %__end1)
+ %1 = load ptr, ptr %__range1
+ %call1 = call ptr @_ZNSt5arrayIiLm6EE3endEv(ptr %1)
+ store ptr %call1, ptr %__end1
br label %for.cond
for.cond:
- %6 = load i32*, i32** %__begin1
- %7 = load i32*, i32** %__end1
- %cmp = icmp ne i32* %6, %7
+ %2 = load ptr, ptr %__begin1
+ %3 = load ptr, ptr %__end1
+ %cmp = icmp ne ptr %2, %3
br i1 %cmp, label %for.body, label %for.cond.cleanup
for.cond.cleanup:
- %8 = bitcast i32** %__end1 to i8*
- call void @llvm.lifetime.end.p0i8(i64 8, i8* %8)
- %9 = bitcast i32** %__begin1 to i8*
- call void @llvm.lifetime.end.p0i8(i64 8, i8* %9)
- %10 = bitcast %"struct.std::array"** %__range1 to i8*
- call void @llvm.lifetime.end.p0i8(i64 8, i8* %10)
+ call void @llvm.lifetime.end.p0(i64 8, ptr %__end1)
+ call void @llvm.lifetime.end.p0(i64 8, ptr %__begin1)
+ call void @llvm.lifetime.end.p0(i64 8, ptr %__range1)
br label %for.end
for.body:
- %11 = bitcast i32** %elt to i8*
- call void @llvm.lifetime.start.p0i8(i64 8, i8* %11)
- %12 = load i32*, i32** %__begin1
- store i32* %12, i32** %elt
- %13 = load i32, i32* %cnt.addr
- %inc = add nsw i32 %13, 1
- store i32 %inc, i32* %cnt.addr
- %14 = load i32*, i32** %elt
- store i32 %inc, i32* %14
- %15 = bitcast i32** %elt to i8*
- call void @llvm.lifetime.end.p0i8(i64 8, i8* %15)
+ call void @llvm.lifetime.start.p0(i64 8, ptr %elt)
+ %4 = load ptr, ptr %__begin1
+ store ptr %4, ptr %elt
+ %5 = load i32, ptr %cnt.addr
+ %inc = add nsw i32 %5, 1
+ store i32 %inc, ptr %cnt.addr
+ %6 = load ptr, ptr %elt
+ store i32 %inc, ptr %6
+ call void @llvm.lifetime.end.p0(i64 8, ptr %elt)
br label %for.inc
for.inc:
- %16 = load i32*, i32** %__begin1
- %incdec.ptr = getelementptr inbounds i32, i32* %16, i32 1
- store i32* %incdec.ptr, i32** %__begin1
+ %7 = load ptr, ptr %__begin1
+ %incdec.ptr = getelementptr inbounds i32, ptr %7, i32 1
+ store ptr %incdec.ptr, ptr %__begin1
br label %for.cond
for.end:
- %17 = bitcast %"struct.std::array"** %__range12 to i8*
- call void @llvm.lifetime.start.p0i8(i64 8, i8* %17)
- store %"struct.std::array"* %arr, %"struct.std::array"** %__range12
- %18 = bitcast i32** %__begin13 to i8*
- call void @llvm.lifetime.start.p0i8(i64 8, i8* %18)
- %19 = load %"struct.std::array"*, %"struct.std::array"** %__range12
- %call4 = call i32* @_ZNSt5arrayIiLm6EE5beginEv(%"struct.std::array"* %19)
- store i32* %call4, i32** %__begin13
- %20 = bitcast i32** %__end15 to i8*
- call void @llvm.lifetime.start.p0i8(i64 8, i8* %20)
- %21 = load %"struct.std::array"*, %"struct.std::array"** %__range12
- %call6 = call i32* @_ZNSt5arrayIiLm6EE3endEv(%"struct.std::array"* %21)
- store i32* %call6, i32** %__end15
+ call void @llvm.lifetime.start.p0(i64 8, ptr %__range12)
+ store ptr %arr, ptr %__range12
+ call void @llvm.lifetime.start.p0(i64 8, ptr %__begin13)
+ %8 = load ptr, ptr %__range12
+ %call4 = call ptr @_ZNSt5arrayIiLm6EE5beginEv(ptr %8)
+ store ptr %call4, ptr %__begin13
+ call void @llvm.lifetime.start.p0(i64 8, ptr %__end15)
+ %9 = load ptr, ptr %__range12
+ %call6 = call ptr @_ZNSt5arrayIiLm6EE3endEv(ptr %9)
+ store ptr %call6, ptr %__end15
br label %for.cond7
for.cond7:
- %22 = load i32*, i32** %__begin13
- %23 = load i32*, i32** %__end15
- %cmp8 = icmp ne i32* %22, %23
+ %10 = load ptr, ptr %__begin13
+ %11 = load ptr, ptr %__end15
+ %cmp8 = icmp ne ptr %10, %11
br i1 %cmp8, label %for.body10, label %for.cond.cleanup9
for.cond.cleanup9:
- %24 = bitcast i32** %__end15 to i8*
- call void @llvm.lifetime.end.p0i8(i64 8, i8* %24)
- %25 = bitcast i32** %__begin13 to i8*
- call void @llvm.lifetime.end.p0i8(i64 8, i8* %25)
- %26 = bitcast %"struct.std::array"** %__range12 to i8*
- call void @llvm.lifetime.end.p0i8(i64 8, i8* %26)
+ call void @llvm.lifetime.end.p0(i64 8, ptr %__end15)
+ call void @llvm.lifetime.end.p0(i64 8, ptr %__begin13)
+ call void @llvm.lifetime.end.p0(i64 8, ptr %__range12)
br label %for.end14
for.body10:
- %27 = bitcast i32** %elt11 to i8*
- call void @llvm.lifetime.start.p0i8(i64 8, i8* %27)
- %28 = load i32*, i32** %__begin13
- store i32* %28, i32** %elt11
- %29 = load i32*, i32** %elt11
- %30 = load i32, i32* %29
- call void @_Z3usei(i32 %30)
- %31 = bitcast i32** %elt11 to i8*
- call void @llvm.lifetime.end.p0i8(i64 8, i8* %31)
+ call void @llvm.lifetime.start.p0(i64 8, ptr %elt11)
+ %12 = load ptr, ptr %__begin13
+ store ptr %12, ptr %elt11
+ %13 = load ptr, ptr %elt11
+ %14 = load i32, ptr %13
+ call void @_Z3usei(i32 %14)
+ call void @llvm.lifetime.end.p0(i64 8, ptr %elt11)
br label %for.inc12
for.inc12:
- %32 = load i32*, i32** %__begin13
- %incdec.ptr13 = getelementptr inbounds i32, i32* %32, i32 1
- store i32* %incdec.ptr13, i32** %__begin13
+ %15 = load ptr, ptr %__begin13
+ %incdec.ptr13 = getelementptr inbounds i32, ptr %15, i32 1
+ store ptr %incdec.ptr13, ptr %__begin13
br label %for.cond7
for.end14:
- %33 = bitcast %"struct.std::array"* %arr to i8*
- call void @llvm.lifetime.end.p0i8(i64 24, i8* %33)
+ call void @llvm.lifetime.end.p0(i64 24, ptr %arr)
ret void
}
-declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
-define linkonce_odr dso_local i32* @_ZNSt5arrayIiLm6EE5beginEv(%"struct.std::array"* %this) {
+define linkonce_odr dso_local ptr @_ZNSt5arrayIiLm6EE5beginEv(ptr %this) {
entry:
- %this.addr = alloca %"struct.std::array"*
- store %"struct.std::array"* %this, %"struct.std::array"** %this.addr
- %this1 = load %"struct.std::array"*, %"struct.std::array"** %this.addr
- %call = call i32* @_ZNSt5arrayIiLm6EE4dataEv(%"struct.std::array"* %this1)
- ret i32* %call
+ %this.addr = alloca ptr
+ store ptr %this, ptr %this.addr
+ %this1 = load ptr, ptr %this.addr
+ %call = call ptr @_ZNSt5arrayIiLm6EE4dataEv(ptr %this1)
+ ret ptr %call
}
-define linkonce_odr dso_local i32* @_ZNSt5arrayIiLm6EE3endEv(%"struct.std::array"* %this) {
+define linkonce_odr dso_local ptr @_ZNSt5arrayIiLm6EE3endEv(ptr %this) {
entry:
- %this.addr = alloca %"struct.std::array"*
- store %"struct.std::array"* %this, %"struct.std::array"** %this.addr
- %this1 = load %"struct.std::array"*, %"struct.std::array"** %this.addr
- %call = call i32* @_ZNSt5arrayIiLm6EE4dataEv(%"struct.std::array"* %this1)
- %add.ptr = getelementptr inbounds i32, i32* %call, i64 6
- ret i32* %add.ptr
+ %this.addr = alloca ptr
+ store ptr %this, ptr %this.addr
+ %this1 = load ptr, ptr %this.addr
+ %call = call ptr @_ZNSt5arrayIiLm6EE4dataEv(ptr %this1)
+ %add.ptr = getelementptr inbounds i32, ptr %call, i64 6
+ ret ptr %add.ptr
}
-declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)
declare dso_local void @_Z3usei(i32)
-define linkonce_odr dso_local i32* @_ZNSt5arrayIiLm6EE4dataEv(%"struct.std::array"* %this) {
+define linkonce_odr dso_local ptr @_ZNSt5arrayIiLm6EE4dataEv(ptr %this) {
entry:
- %this.addr = alloca %"struct.std::array"*
- store %"struct.std::array"* %this, %"struct.std::array"** %this.addr
- %this1 = load %"struct.std::array"*, %"struct.std::array"** %this.addr
- %_M_elems = getelementptr inbounds %"struct.std::array", %"struct.std::array"* %this1, i32 0, i32 0
- %call = call i32* @_ZNSt14__array_traitsIiLm6EE6_S_ptrERA6_Ki([6 x i32]* nonnull align 4 dereferenceable(24) %_M_elems)
- ret i32* %call
+ %this.addr = alloca ptr
+ store ptr %this, ptr %this.addr
+ %this1 = load ptr, ptr %this.addr
+ %call = call ptr @_ZNSt14__array_traitsIiLm6EE6_S_ptrERA6_Ki(ptr nonnull align 4 dereferenceable(24) %this1)
+ ret ptr %call
}
-define linkonce_odr dso_local i32* @_ZNSt14__array_traitsIiLm6EE6_S_ptrERA6_Ki([6 x i32]* nonnull align 4 dereferenceable(24) %__t) {
+define linkonce_odr dso_local ptr @_ZNSt14__array_traitsIiLm6EE6_S_ptrERA6_Ki(ptr nonnull align 4 dereferenceable(24) %__t) {
entry:
- %__t.addr = alloca [6 x i32]*
- store [6 x i32]* %__t, [6 x i32]** %__t.addr
- %0 = load [6 x i32]*, [6 x i32]** %__t.addr
- %arraydecay = getelementptr inbounds [6 x i32], [6 x i32]* %0, i64 0, i64 0
- ret i32* %arraydecay
+ %__t.addr = alloca ptr
+ store ptr %__t, ptr %__t.addr
+ %0 = load ptr, ptr %__t.addr
+ ret ptr %0
}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll b/llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
index 63b9223d508e4..84eba813b179d 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
@@ -68,34 +68,32 @@ define { <2 x float>, <2 x float> } @add_aggregate(<2 x float> %a0, <2 x float>
ret { <2 x float>, <2 x float> } %fca.1.insert
}
-define void @add_aggregate_store(<2 x float> %a0, <2 x float> %a1, <2 x float> %b0, <2 x float> %b1, %struct.Vector4* nocapture dereferenceable(16) %r) {
+define void @add_aggregate_store(<2 x float> %a0, <2 x float> %a1, <2 x float> %b0, <2 x float> %b1, ptr nocapture dereferenceable(16) %r) {
; CHECK-LABEL: @add_aggregate_store(
; CHECK-NEXT: [[TMP1:%.*]] = fadd <2 x float> [[A0:%.*]], [[B0:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = fadd <2 x float> [[A1:%.*]], [[B1:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast %struct.Vector4* [[R:%.*]] to <4 x float>*
-; CHECK-NEXT: store <4 x float> [[TMP3]], <4 x float>* [[TMP4]], align 4
+; CHECK-NEXT: store <4 x float> [[TMP3]], ptr [[R:%.*]], align 4
; CHECK-NEXT: ret void
;
%a00 = extractelement <2 x float> %a0, i32 0
%b00 = extractelement <2 x float> %b0, i32 0
%add = fadd float %a00, %b00
- %r0 = getelementptr inbounds %struct.Vector4, %struct.Vector4* %r, i64 0, i32 0
- store float %add, float* %r0, align 4
+ store float %add, ptr %r, align 4
%a01 = extractelement <2 x float> %a0, i32 1
%b01 = extractelement <2 x float> %b0, i32 1
%add4 = fadd float %a01, %b01
- %r1 = getelementptr inbounds %struct.Vector4, %struct.Vector4* %r, i64 0, i32 1
- store float %add4, float* %r1, align 4
+ %r1 = getelementptr inbounds %struct.Vector4, ptr %r, i64 0, i32 1
+ store float %add4, ptr %r1, align 4
%a10 = extractelement <2 x float> %a1, i32 0
%b10 = extractelement <2 x float> %b1, i32 0
%add7 = fadd float %a10, %b10
- %r2 = getelementptr inbounds %struct.Vector4, %struct.Vector4* %r, i64 0, i32 2
- store float %add7, float* %r2, align 4
+ %r2 = getelementptr inbounds %struct.Vector4, ptr %r, i64 0, i32 2
+ store float %add7, ptr %r2, align 4
%a11 = extractelement <2 x float> %a1, i32 1
%b11 = extractelement <2 x float> %b1, i32 1
%add10 = fadd float %a11, %b11
- %r3 = getelementptr inbounds %struct.Vector4, %struct.Vector4* %r, i64 0, i32 3
- store float %add10, float* %r3, align 4
+ %r3 = getelementptr inbounds %struct.Vector4, ptr %r, i64 0, i32 3
+ store float %add10, ptr %r3, align 4
ret void
}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/addsub.ll b/llvm/test/Transforms/PhaseOrdering/X86/addsub.ll
index 0c9a7633fc88f..870ae4ec20e4c 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/addsub.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/addsub.ll
@@ -68,34 +68,32 @@ define { <2 x float>, <2 x float> } @add_aggregate(<2 x float> %a0, <2 x float>
ret { <2 x float>, <2 x float> } %fca.1.insert
}
-define void @add_aggregate_store(<2 x float> %a0, <2 x float> %a1, <2 x float> %b0, <2 x float> %b1, %struct.Vector4* nocapture dereferenceable(16) %r) {
+define void @add_aggregate_store(<2 x float> %a0, <2 x float> %a1, <2 x float> %b0, <2 x float> %b1, ptr nocapture dereferenceable(16) %r) {
; CHECK-LABEL: @add_aggregate_store(
; CHECK-NEXT: [[TMP1:%.*]] = fadd <2 x float> [[A0:%.*]], [[B0:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = fadd <2 x float> [[A1:%.*]], [[B1:%.*]]
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast %struct.Vector4* [[R:%.*]] to <4 x float>*
-; CHECK-NEXT: store <4 x float> [[TMP3]], <4 x float>* [[TMP4]], align 4
+; CHECK-NEXT: store <4 x float> [[TMP3]], ptr [[R:%.*]], align 4
; CHECK-NEXT: ret void
;
%a00 = extractelement <2 x float> %a0, i32 0
%b00 = extractelement <2 x float> %b0, i32 0
%add = fadd float %a00, %b00
- %r0 = getelementptr inbounds %struct.Vector4, %struct.Vector4* %r, i64 0, i32 0
- store float %add, float* %r0, align 4
+ store float %add, ptr %r, align 4
%a01 = extractelement <2 x float> %a0, i32 1
%b01 = extractelement <2 x float> %b0, i32 1
%add4 = fadd float %a01, %b01
- %r1 = getelementptr inbounds %struct.Vector4, %struct.Vector4* %r, i64 0, i32 1
- store float %add4, float* %r1, align 4
+ %r1 = getelementptr inbounds %struct.Vector4, ptr %r, i64 0, i32 1
+ store float %add4, ptr %r1, align 4
%a10 = extractelement <2 x float> %a1, i32 0
%b10 = extractelement <2 x float> %b1, i32 0
%add7 = fadd float %a10, %b10
- %r2 = getelementptr inbounds %struct.Vector4, %struct.Vector4* %r, i64 0, i32 2
- store float %add7, float* %r2, align 4
+ %r2 = getelementptr inbounds %struct.Vector4, ptr %r, i64 0, i32 2
+ store float %add7, ptr %r2, align 4
%a11 = extractelement <2 x float> %a1, i32 1
%b11 = extractelement <2 x float> %b1, i32 1
%add10 = fadd float %a11, %b11
- %r3 = getelementptr inbounds %struct.Vector4, %struct.Vector4* %r, i64 0, i32 3
- store float %add10, float* %r3, align 4
+ %r3 = getelementptr inbounds %struct.Vector4, ptr %r, i64 0, i32 3
+ store float %add10, ptr %r3, align 4
ret void
}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/earlycse-after-simplifycfg-two-entry-phi-node-folding.ll b/llvm/test/Transforms/PhaseOrdering/X86/earlycse-after-simplifycfg-two-entry-phi-node-folding.ll
index f84ad93683b63..4c57ba74782e5 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/earlycse-after-simplifycfg-two-entry-phi-node-folding.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/earlycse-after-simplifycfg-two-entry-phi-node-folding.ll
@@ -6,46 +6,46 @@ target triple = "x86_64-unknown-linux-gnu"
; PR51092: SimplifyCFG might produce duplicate PHI's/select's.
; We need to deduplicate them so that further transformations are possible.
-define dso_local void @foo(i32* %in, i64 %lo, i64 %hi, i32 %ishi) #0 {
+define dso_local void @foo(ptr %in, i64 %lo, i64 %hi, i32 %ishi) #0 {
; CHECK-LABEL: @foo(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[ISHI:%.*]], 0
; CHECK-NEXT: [[LO_HI:%.*]] = select i1 [[TOBOOL_NOT]], i64 [[LO:%.*]], i64 [[HI:%.*]]
-; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[IN:%.*]], i64 [[LO_HI]]
-; CHECK-NEXT: [[ARRAYVAL2:%.*]] = load i32, i32* [[ARRAYIDX1]], align 4
+; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[IN:%.*]], i64 [[LO_HI]]
+; CHECK-NEXT: [[ARRAYVAL2:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4
; CHECK-NEXT: [[INC2:%.*]] = add nsw i32 [[ARRAYVAL2]], 1
-; CHECK-NEXT: store i32 [[INC2]], i32* [[ARRAYIDX1]], align 4
+; CHECK-NEXT: store i32 [[INC2]], ptr [[ARRAYIDX1]], align 4
; CHECK-NEXT: ret void
;
entry:
- %in.addr = alloca i32*, align 8
+ %in.addr = alloca ptr, align 8
%lo.addr = alloca i64, align 8
%hi.addr = alloca i64, align 8
%ishi.addr = alloca i32, align 4
- store i32* %in, i32** %in.addr, align 8
- store i64 %lo, i64* %lo.addr, align 8
- store i64 %hi, i64* %hi.addr, align 8
- store i32 %ishi, i32* %ishi.addr, align 4
- %ishi.reloaded = load i32, i32* %ishi.addr, align 4
+ store ptr %in, ptr %in.addr, align 8
+ store i64 %lo, ptr %lo.addr, align 8
+ store i64 %hi, ptr %hi.addr, align 8
+ store i32 %ishi, ptr %ishi.addr, align 4
+ %ishi.reloaded = load i32, ptr %ishi.addr, align 4
%tobool = icmp ne i32 %ishi.reloaded, 0
br i1 %tobool, label %if.then, label %if.else
if.then:
- %in.reloaded = load i32*, i32** %in.addr, align 8
- %hi.reloaded = load i64, i64* %hi.addr, align 8
- %arrayidx = getelementptr inbounds i32, i32* %in.reloaded, i64 %hi.reloaded
- %arrayval = load i32, i32* %arrayidx, align 4
+ %in.reloaded = load ptr, ptr %in.addr, align 8
+ %hi.reloaded = load i64, ptr %hi.addr, align 8
+ %arrayidx = getelementptr inbounds i32, ptr %in.reloaded, i64 %hi.reloaded
+ %arrayval = load i32, ptr %arrayidx, align 4
%inc = add nsw i32 %arrayval, 1
- store i32 %inc, i32* %arrayidx, align 4
+ store i32 %inc, ptr %arrayidx, align 4
br label %if.end
if.else:
- %in.reloaded2 = load i32*, i32** %in.addr, align 8
- %lo.reloaded = load i64, i64* %lo.addr, align 8
- %arrayidx1 = getelementptr inbounds i32, i32* %in.reloaded2, i64 %lo.reloaded
- %arrayval2 = load i32, i32* %arrayidx1, align 4
+ %in.reloaded2 = load ptr, ptr %in.addr, align 8
+ %lo.reloaded = load i64, ptr %lo.addr, align 8
+ %arrayidx1 = getelementptr inbounds i32, ptr %in.reloaded2, i64 %lo.reloaded
+ %arrayval2 = load i32, ptr %arrayidx1, align 4
%inc2 = add nsw i32 %arrayval2, 1
- store i32 %inc2, i32* %arrayidx1, align 4
+ store i32 %inc2, ptr %arrayidx1, align 4
br label %if.end
if.end:
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll b/llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll
index 74063ea5cfe4b..5dac5edf63651 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll
@@ -9,233 +9,215 @@ target triple = "x86_64-unknown-linux-gnu"
%"class.std::vector" = type { %"struct.std::_Vector_base" }
%"struct.std::_Vector_base" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" }
%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl" = type { %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" }
-%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { i32*, i32*, i32* }
+%"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data" = type { ptr, ptr, ptr }
$_ZNSt6vectorIiSaIiEEixEm = comdat any
-define dso_local void @_Z7computeRSt6vectorIiSaIiEEy(%"class.std::vector"* noundef nonnull align 8 dereferenceable(24) %data, i64 noundef %numElems) {
+define dso_local void @_Z7computeRSt6vectorIiSaIiEEy(ptr noundef nonnull align 8 dereferenceable(24) %data, i64 noundef %numElems) {
; O1-LABEL: define {{[^@]+}}@_Z7computeRSt6vectorIiSaIiEEy
-; O1-SAME: (%"class.std::vector"* nocapture noundef nonnull readonly align 8 dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+; O1-SAME: (ptr nocapture noundef nonnull readonly align 8 dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
; O1-NEXT: entry:
-; O1-NEXT: [[CMP26_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0
-; O1-NEXT: [[_M_START_I:%.*]] = getelementptr inbounds %"class.std::vector", %"class.std::vector"* [[DATA]], i64 0, i32 0, i32 0, i32 0, i32 0
-; O1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[_M_START_I]], align 8
+; O1-NEXT: [[CMP24_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0
+; O1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DATA]], align 8
; O1-NEXT: br label [[FOR_COND1_PREHEADER:%.*]]
; O1: for.cond1.preheader:
-; O1-NEXT: [[I_08:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INC7:%.*]], [[FOR_COND_CLEANUP3:%.*]] ]
-; O1-NEXT: br i1 [[CMP26_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4:%.*]]
+; O1-NEXT: [[I_06:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INC7:%.*]], [[FOR_COND_CLEANUP3:%.*]] ]
+; O1-NEXT: br i1 [[CMP24_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4:%.*]]
; O1: for.cond.cleanup:
; O1-NEXT: ret void
; O1: for.cond.cleanup3:
-; O1-NEXT: [[INC7]] = add nuw nsw i64 [[I_08]], 1
-; O1-NEXT: [[EXITCOND9_NOT:%.*]] = icmp eq i64 [[INC7]], 100
-; O1-NEXT: br i1 [[EXITCOND9_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER]], !llvm.loop [[LOOP0:![0-9]+]]
+; O1-NEXT: [[INC7]] = add nuw nsw i64 [[I_06]], 1
+; O1-NEXT: [[EXITCOND7_NOT:%.*]] = icmp eq i64 [[INC7]], 100
+; O1-NEXT: br i1 [[EXITCOND7_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER]], !llvm.loop [[LOOP0:![0-9]+]]
; O1: for.body4:
-; O1-NEXT: [[J_07:%.*]] = phi i64 [ [[INC5:%.*]], [[FOR_BODY4]] ], [ 0, [[FOR_COND1_PREHEADER]] ]
-; O1-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[J_07]]
-; O1-NEXT: [[TMP1:%.*]] = load i32, i32* [[ADD_PTR_I]], align 4, !tbaa [[TBAA2:![0-9]+]]
+; O1-NEXT: [[J_05:%.*]] = phi i64 [ [[INC5:%.*]], [[FOR_BODY4]] ], [ 0, [[FOR_COND1_PREHEADER]] ]
+; O1-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 [[J_05]]
+; O1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ADD_PTR_I]], align 4, !tbaa [[TBAA2:![0-9]+]]
; O1-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1
-; O1-NEXT: store i32 [[INC]], i32* [[ADD_PTR_I]], align 4, !tbaa [[TBAA2]]
-; O1-NEXT: [[INC5]] = add nuw i64 [[J_07]], 1
+; O1-NEXT: store i32 [[INC]], ptr [[ADD_PTR_I]], align 4, !tbaa [[TBAA2]]
+; O1-NEXT: [[INC5]] = add nuw i64 [[J_05]], 1
; O1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC5]], [[NUMELEMS]]
; O1-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4]], !llvm.loop [[LOOP6:![0-9]+]]
;
; O2-LABEL: define {{[^@]+}}@_Z7computeRSt6vectorIiSaIiEEy
-; O2-SAME: (%"class.std::vector"* nocapture noundef nonnull readonly align 8 dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+; O2-SAME: (ptr nocapture noundef nonnull readonly align 8 dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
; O2-NEXT: entry:
-; O2-NEXT: [[CMP26_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0
-; O2-NEXT: [[_M_START_I:%.*]] = getelementptr inbounds %"class.std::vector", %"class.std::vector"* [[DATA]], i64 0, i32 0, i32 0, i32 0, i32 0
-; O2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[_M_START_I]], align 8
+; O2-NEXT: [[CMP24_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0
+; O2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DATA]], align 8
; O2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEMS]], 8
; O2-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEMS]], -8
; O2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEMS]]
; O2-NEXT: br label [[FOR_COND1_PREHEADER:%.*]]
; O2: for.cond1.preheader:
-; O2-NEXT: [[I_08:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INC7:%.*]], [[FOR_COND_CLEANUP3:%.*]] ]
-; O2-NEXT: br i1 [[CMP26_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4_PREHEADER:%.*]]
+; O2-NEXT: [[I_06:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INC7:%.*]], [[FOR_COND_CLEANUP3:%.*]] ]
+; O2-NEXT: br i1 [[CMP24_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4_PREHEADER:%.*]]
; O2: for.body4.preheader:
-; O2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY4_PREHEADER11:%.*]], label [[VECTOR_BODY:%.*]]
+; O2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY4_PREHEADER9:%.*]], label [[VECTOR_BODY:%.*]]
; O2: vector.body:
; O2-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ], [ 0, [[FOR_BODY4_PREHEADER]] ]
-; O2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[INDEX]]
-; O2-NEXT: [[TMP2:%.*]] = bitcast i32* [[TMP1]] to <4 x i32>*
-; O2-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP2]], align 4, !tbaa [[TBAA0:![0-9]+]]
-; O2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 4
-; O2-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP3]] to <4 x i32>*
-; O2-NEXT: [[WIDE_LOAD10:%.*]] = load <4 x i32>, <4 x i32>* [[TMP4]], align 4, !tbaa [[TBAA0]]
-; O2-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], <i32 1, i32 1, i32 1, i32 1>
-; O2-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD10]], <i32 1, i32 1, i32 1, i32 1>
-; O2-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP1]] to <4 x i32>*
-; O2-NEXT: store <4 x i32> [[TMP5]], <4 x i32>* [[TMP7]], align 4, !tbaa [[TBAA0]]
-; O2-NEXT: [[TMP8:%.*]] = bitcast i32* [[TMP3]] to <4 x i32>*
-; O2-NEXT: store <4 x i32> [[TMP6]], <4 x i32>* [[TMP8]], align 4, !tbaa [[TBAA0]]
+; O2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 [[INDEX]]
+; O2-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4, !tbaa [[TBAA0:![0-9]+]]
+; O2-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 4
+; O2-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4, !tbaa [[TBAA0]]
+; O2-NEXT: [[TMP3:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], <i32 1, i32 1, i32 1, i32 1>
+; O2-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> [[WIDE_LOAD8]], <i32 1, i32 1, i32 1, i32 1>
+; O2-NEXT: store <4 x i32> [[TMP3]], ptr [[TMP1]], align 4, !tbaa [[TBAA0]]
+; O2-NEXT: store <4 x i32> [[TMP4]], ptr [[TMP2]], align 4, !tbaa [[TBAA0]]
; O2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
-; O2-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; O2-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; O2-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; O2-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
; O2: middle.block:
-; O2-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4_PREHEADER11]]
-; O2: for.body4.preheader11:
-; O2-NEXT: [[J_07_PH:%.*]] = phi i64 [ 0, [[FOR_BODY4_PREHEADER]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ]
+; O2-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4_PREHEADER9]]
+; O2: for.body4.preheader9:
+; O2-NEXT: [[J_05_PH:%.*]] = phi i64 [ 0, [[FOR_BODY4_PREHEADER]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ]
; O2-NEXT: br label [[FOR_BODY4:%.*]]
; O2: for.cond.cleanup:
; O2-NEXT: ret void
; O2: for.cond.cleanup3:
-; O2-NEXT: [[INC7]] = add nuw nsw i64 [[I_08]], 1
-; O2-NEXT: [[EXITCOND9_NOT:%.*]] = icmp eq i64 [[INC7]], 100
-; O2-NEXT: br i1 [[EXITCOND9_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER]], !llvm.loop [[LOOP7:![0-9]+]]
+; O2-NEXT: [[INC7]] = add nuw nsw i64 [[I_06]], 1
+; O2-NEXT: [[EXITCOND7_NOT:%.*]] = icmp eq i64 [[INC7]], 100
+; O2-NEXT: br i1 [[EXITCOND7_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER]], !llvm.loop [[LOOP7:![0-9]+]]
; O2: for.body4:
-; O2-NEXT: [[J_07:%.*]] = phi i64 [ [[INC5:%.*]], [[FOR_BODY4]] ], [ [[J_07_PH]], [[FOR_BODY4_PREHEADER11]] ]
-; O2-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[J_07]]
-; O2-NEXT: [[TMP10:%.*]] = load i32, i32* [[ADD_PTR_I]], align 4, !tbaa [[TBAA0]]
-; O2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP10]], 1
-; O2-NEXT: store i32 [[INC]], i32* [[ADD_PTR_I]], align 4, !tbaa [[TBAA0]]
-; O2-NEXT: [[INC5]] = add nuw i64 [[J_07]], 1
+; O2-NEXT: [[J_05:%.*]] = phi i64 [ [[INC5:%.*]], [[FOR_BODY4]] ], [ [[J_05_PH]], [[FOR_BODY4_PREHEADER9]] ]
+; O2-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 [[J_05]]
+; O2-NEXT: [[TMP6:%.*]] = load i32, ptr [[ADD_PTR_I]], align 4, !tbaa [[TBAA0]]
+; O2-NEXT: [[INC:%.*]] = add nsw i32 [[TMP6]], 1
+; O2-NEXT: store i32 [[INC]], ptr [[ADD_PTR_I]], align 4, !tbaa [[TBAA0]]
+; O2-NEXT: [[INC5]] = add nuw i64 [[J_05]], 1
; O2-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC5]], [[NUMELEMS]]
; O2-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4]], !llvm.loop [[LOOP8:![0-9]+]]
;
; O3-LABEL: define {{[^@]+}}@_Z7computeRSt6vectorIiSaIiEEy
-; O3-SAME: (%"class.std::vector"* nocapture noundef nonnull readonly align 8 dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+; O3-SAME: (ptr nocapture noundef nonnull readonly align 8 dereferenceable(24) [[DATA:%.*]], i64 noundef [[NUMELEMS:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
; O3-NEXT: entry:
-; O3-NEXT: [[CMP26_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0
-; O3-NEXT: [[_M_START_I:%.*]] = getelementptr inbounds %"class.std::vector", %"class.std::vector"* [[DATA]], i64 0, i32 0, i32 0, i32 0, i32 0
-; O3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[_M_START_I]], align 8
-; O3-NEXT: br i1 [[CMP26_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER_US_PREHEADER:%.*]]
+; O3-NEXT: [[CMP24_NOT:%.*]] = icmp eq i64 [[NUMELEMS]], 0
+; O3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DATA]], align 8
+; O3-NEXT: br i1 [[CMP24_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER_US_PREHEADER:%.*]]
; O3: for.cond1.preheader.us.preheader:
; O3-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEMS]], 8
; O3-NEXT: [[N_VEC:%.*]] = and i64 [[NUMELEMS]], -8
; O3-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[NUMELEMS]]
; O3-NEXT: br label [[FOR_COND1_PREHEADER_US:%.*]]
; O3: for.cond1.preheader.us:
-; O3-NEXT: [[I_08_US:%.*]] = phi i64 [ [[INC7_US:%.*]], [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND1_PREHEADER_US_PREHEADER]] ]
+; O3-NEXT: [[I_06_US:%.*]] = phi i64 [ [[INC7_US:%.*]], [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US:%.*]] ], [ 0, [[FOR_COND1_PREHEADER_US_PREHEADER]] ]
; O3-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY4_US_PREHEADER:%.*]], label [[VECTOR_BODY:%.*]]
; O3: vector.body:
; O3-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ], [ 0, [[FOR_COND1_PREHEADER_US]] ]
-; O3-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[INDEX]]
-; O3-NEXT: [[TMP2:%.*]] = bitcast i32* [[TMP1]] to <4 x i32>*
-; O3-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP2]], align 4, !tbaa [[TBAA0:![0-9]+]]
-; O3-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 4
-; O3-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP3]] to <4 x i32>*
-; O3-NEXT: [[WIDE_LOAD11:%.*]] = load <4 x i32>, <4 x i32>* [[TMP4]], align 4, !tbaa [[TBAA0]]
-; O3-NEXT: [[TMP5:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], <i32 1, i32 1, i32 1, i32 1>
-; O3-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[WIDE_LOAD11]], <i32 1, i32 1, i32 1, i32 1>
-; O3-NEXT: [[TMP7:%.*]] = bitcast i32* [[TMP1]] to <4 x i32>*
-; O3-NEXT: store <4 x i32> [[TMP5]], <4 x i32>* [[TMP7]], align 4, !tbaa [[TBAA0]]
-; O3-NEXT: [[TMP8:%.*]] = bitcast i32* [[TMP3]] to <4 x i32>*
-; O3-NEXT: store <4 x i32> [[TMP6]], <4 x i32>* [[TMP8]], align 4, !tbaa [[TBAA0]]
+; O3-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 [[INDEX]]
+; O3-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4, !tbaa [[TBAA0:![0-9]+]]
+; O3-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 4
+; O3-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4, !tbaa [[TBAA0]]
+; O3-NEXT: [[TMP3:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], <i32 1, i32 1, i32 1, i32 1>
+; O3-NEXT: [[TMP4:%.*]] = add nsw <4 x i32> [[WIDE_LOAD9]], <i32 1, i32 1, i32 1, i32 1>
+; O3-NEXT: store <4 x i32> [[TMP3]], ptr [[TMP1]], align 4, !tbaa [[TBAA0]]
+; O3-NEXT: store <4 x i32> [[TMP4]], ptr [[TMP2]], align 4, !tbaa [[TBAA0]]
; O3-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
-; O3-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; O3-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; O3-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; O3-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
; O3: middle.block:
; O3-NEXT: br i1 [[CMP_N]], label [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US]], label [[FOR_BODY4_US_PREHEADER]]
; O3: for.body4.us.preheader:
-; O3-NEXT: [[J_07_US_PH:%.*]] = phi i64 [ 0, [[FOR_COND1_PREHEADER_US]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ]
+; O3-NEXT: [[J_05_US_PH:%.*]] = phi i64 [ 0, [[FOR_COND1_PREHEADER_US]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ]
; O3-NEXT: br label [[FOR_BODY4_US:%.*]]
; O3: for.body4.us:
-; O3-NEXT: [[J_07_US:%.*]] = phi i64 [ [[INC5_US:%.*]], [[FOR_BODY4_US]] ], [ [[J_07_US_PH]], [[FOR_BODY4_US_PREHEADER]] ]
-; O3-NEXT: [[ADD_PTR_I_US:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[J_07_US]]
-; O3-NEXT: [[TMP10:%.*]] = load i32, i32* [[ADD_PTR_I_US]], align 4, !tbaa [[TBAA0]]
-; O3-NEXT: [[INC_US:%.*]] = add nsw i32 [[TMP10]], 1
-; O3-NEXT: store i32 [[INC_US]], i32* [[ADD_PTR_I_US]], align 4, !tbaa [[TBAA0]]
-; O3-NEXT: [[INC5_US]] = add nuw i64 [[J_07_US]], 1
+; O3-NEXT: [[J_05_US:%.*]] = phi i64 [ [[INC5_US:%.*]], [[FOR_BODY4_US]] ], [ [[J_05_US_PH]], [[FOR_BODY4_US_PREHEADER]] ]
+; O3-NEXT: [[ADD_PTR_I_US:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 [[J_05_US]]
+; O3-NEXT: [[TMP6:%.*]] = load i32, ptr [[ADD_PTR_I_US]], align 4, !tbaa [[TBAA0]]
+; O3-NEXT: [[INC_US:%.*]] = add nsw i32 [[TMP6]], 1
+; O3-NEXT: store i32 [[INC_US]], ptr [[ADD_PTR_I_US]], align 4, !tbaa [[TBAA0]]
+; O3-NEXT: [[INC5_US]] = add nuw i64 [[J_05_US]], 1
; O3-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC5_US]], [[NUMELEMS]]
; O3-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US]], label [[FOR_BODY4_US]], !llvm.loop [[LOOP7:![0-9]+]]
; O3: for.cond1.for.cond.cleanup3_crit_edge.us:
-; O3-NEXT: [[INC7_US]] = add nuw nsw i64 [[I_08_US]], 1
-; O3-NEXT: [[EXITCOND10_NOT:%.*]] = icmp eq i64 [[INC7_US]], 100
-; O3-NEXT: br i1 [[EXITCOND10_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_COND1_PREHEADER_US]], !llvm.loop [[LOOP9:![0-9]+]]
+; O3-NEXT: [[INC7_US]] = add nuw nsw i64 [[I_06_US]], 1
+; O3-NEXT: [[EXITCOND8_NOT:%.*]] = icmp eq i64 [[INC7_US]], 100
+; O3-NEXT: br i1 [[EXITCOND8_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_COND1_PREHEADER_US]], !llvm.loop [[LOOP9:![0-9]+]]
; O3: for.cond.cleanup:
; O3-NEXT: ret void
;
entry:
- %data.addr = alloca %"class.std::vector"*, align 8
+ %data.addr = alloca ptr, align 8
%numElems.addr = alloca i64, align 8
%i = alloca i64, align 8
%cleanup.dest.slot = alloca i32, align 4
%j = alloca i64, align 8
- store %"class.std::vector"* %data, %"class.std::vector"** %data.addr, align 8, !tbaa !3
- store i64 %numElems, i64* %numElems.addr, align 8, !tbaa !7
- %0 = bitcast i64* %i to i8*
- call void @llvm.lifetime.start.p0i8(i64 8, i8* %0)
- store i64 0, i64* %i, align 8, !tbaa !7
+ store ptr %data, ptr %data.addr, align 8, !tbaa !3
+ store i64 %numElems, ptr %numElems.addr, align 8, !tbaa !7
+ call void @llvm.lifetime.start.p0(i64 8, ptr %i)
+ store i64 0, ptr %i, align 8, !tbaa !7
br label %for.cond
for.cond:
- %1 = load i64, i64* %i, align 8, !tbaa !7
- %cmp = icmp ult i64 %1, 100
+ %0 = load i64, ptr %i, align 8, !tbaa !7
+ %cmp = icmp ult i64 %0, 100
br i1 %cmp, label %for.body, label %for.cond.cleanup
for.cond.cleanup:
- store i32 2, i32* %cleanup.dest.slot, align 4
- %2 = bitcast i64* %i to i8*
- call void @llvm.lifetime.end.p0i8(i64 8, i8* %2)
+ store i32 2, ptr %cleanup.dest.slot, align 4
+ call void @llvm.lifetime.end.p0(i64 8, ptr %i)
br label %for.end8
for.body:
- %3 = bitcast i64* %j to i8*
- call void @llvm.lifetime.start.p0i8(i64 8, i8* %3)
- store i64 0, i64* %j, align 8, !tbaa !7
+ call void @llvm.lifetime.start.p0(i64 8, ptr %j)
+ store i64 0, ptr %j, align 8, !tbaa !7
br label %for.cond1
for.cond1:
- %4 = load i64, i64* %j, align 8, !tbaa !7
- %5 = load i64, i64* %numElems.addr, align 8, !tbaa !7
- %cmp2 = icmp ult i64 %4, %5
+ %1 = load i64, ptr %j, align 8, !tbaa !7
+ %2 = load i64, ptr %numElems.addr, align 8, !tbaa !7
+ %cmp2 = icmp ult i64 %1, %2
br i1 %cmp2, label %for.body4, label %for.cond.cleanup3
for.cond.cleanup3:
- store i32 5, i32* %cleanup.dest.slot, align 4
- %6 = bitcast i64* %j to i8*
- call void @llvm.lifetime.end.p0i8(i64 8, i8* %6)
+ store i32 5, ptr %cleanup.dest.slot, align 4
+ call void @llvm.lifetime.end.p0(i64 8, ptr %j)
br label %for.end
for.body4:
- %7 = load %"class.std::vector"*, %"class.std::vector"** %data.addr, align 8, !tbaa !3
- %8 = load i64, i64* %j, align 8, !tbaa !7
- %call = call noundef nonnull align 4 dereferenceable(4) i32* @_ZNSt6vectorIiSaIiEEixEm(%"class.std::vector"* noundef nonnull align 8 dereferenceable(24) %7, i64 noundef %8)
- %9 = load i32, i32* %call, align 4, !tbaa !9
- %inc = add nsw i32 %9, 1
- store i32 %inc, i32* %call, align 4, !tbaa !9
+ %3 = load ptr, ptr %data.addr, align 8, !tbaa !3
+ %4 = load i64, ptr %j, align 8, !tbaa !7
+ %call = call noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %3, i64 noundef %4)
+ %5 = load i32, ptr %call, align 4, !tbaa !9
+ %inc = add nsw i32 %5, 1
+ store i32 %inc, ptr %call, align 4, !tbaa !9
br label %for.inc
for.inc:
- %10 = load i64, i64* %j, align 8, !tbaa !7
- %inc5 = add i64 %10, 1
- store i64 %inc5, i64* %j, align 8, !tbaa !7
+ %6 = load i64, ptr %j, align 8, !tbaa !7
+ %inc5 = add i64 %6, 1
+ store i64 %inc5, ptr %j, align 8, !tbaa !7
br label %for.cond1, !llvm.loop !11
for.end:
br label %for.inc6
for.inc6:
- %11 = load i64, i64* %i, align 8, !tbaa !7
- %inc7 = add i64 %11, 1
- store i64 %inc7, i64* %i, align 8, !tbaa !7
+ %7 = load i64, ptr %i, align 8, !tbaa !7
+ %inc7 = add i64 %7, 1
+ store i64 %inc7, ptr %i, align 8, !tbaa !7
br label %for.cond, !llvm.loop !13
for.end8:
ret void
}
-declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
-define linkonce_odr dso_local noundef nonnull align 4 dereferenceable(4) i32* @_ZNSt6vectorIiSaIiEEixEm(%"class.std::vector"* noundef nonnull align 8 dereferenceable(24) %this, i64 noundef %__n) comdat align 2 {
+define linkonce_odr dso_local noundef nonnull align 4 dereferenceable(4) ptr @_ZNSt6vectorIiSaIiEEixEm(ptr noundef nonnull align 8 dereferenceable(24) %this, i64 noundef %__n) comdat align 2 {
entry:
- %this.addr = alloca %"class.std::vector"*, align 8
+ %this.addr = alloca ptr, align 8
%__n.addr = alloca i64, align 8
- store %"class.std::vector"* %this, %"class.std::vector"** %this.addr, align 8, !tbaa !3
- store i64 %__n, i64* %__n.addr, align 8, !tbaa !14
- %this1 = load %"class.std::vector"*, %"class.std::vector"** %this.addr, align 8
- %0 = bitcast %"class.std::vector"* %this1 to %"struct.std::_Vector_base"*
- %_M_impl = getelementptr inbounds %"struct.std::_Vector_base", %"struct.std::_Vector_base"* %0, i32 0, i32 0
- %1 = bitcast %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl"* %_M_impl to %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data"*
- %_M_start = getelementptr inbounds %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data", %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data"* %1, i32 0, i32 0
- %2 = load i32*, i32** %_M_start, align 8, !tbaa !16
- %3 = load i64, i64* %__n.addr, align 8, !tbaa !14
- %add.ptr = getelementptr inbounds i32, i32* %2, i64 %3
- ret i32* %add.ptr
+ store ptr %this, ptr %this.addr, align 8, !tbaa !3
+ store i64 %__n, ptr %__n.addr, align 8, !tbaa !14
+ %this1 = load ptr, ptr %this.addr, align 8
+ %_M_start = getelementptr inbounds %"struct.std::_Vector_base<int, std::allocator<int>>::_Vector_impl_data", ptr %this1, i32 0, i32 0
+ %0 = load ptr, ptr %_M_start, align 8, !tbaa !16
+ %1 = load i64, ptr %__n.addr, align 8, !tbaa !14
+ %add.ptr = getelementptr inbounds i32, ptr %0, i64 %1
+ ret ptr %add.ptr
}
-declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)
!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 7, !"uwtable", i32 2}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll b/llvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll
index 17317ae78e934..4b5f3107466c8 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll
@@ -8,14 +8,14 @@
target triple = "x86_64--"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
-define i32 @cttz(i32 %n, i32* %p1) {
+define i32 @cttz(i32 %n, ptr %p1) {
; ALL-LABEL: @cttz(
; ALL-NEXT: entry:
; ALL-NEXT: [[TMP0:%.*]] = shl i32 [[N:%.*]], 1
; ALL-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false), !range [[RNG0:![0-9]+]]
; ALL-NEXT: [[TMP2:%.*]] = sub nuw nsw i32 32, [[TMP1]]
; ALL-NEXT: [[TMP3:%.*]] = sub nuw nsw i32 75, [[TMP1]]
-; ALL-NEXT: store i32 [[TMP3]], i32* [[P1:%.*]], align 4
+; ALL-NEXT: store i32 [[TMP3]], ptr [[P1:%.*]], align 4
; ALL-NEXT: ret i32 [[TMP2]]
;
entry:
@@ -32,6 +32,6 @@ while.cond: ; preds = %while.cond, %entry
br i1 %tobool, label %while.end, label %while.cond
while.end: ; preds = %while.cond
- store i32 %whatever.next, i32* %p1
+ store i32 %whatever.next, ptr %p1
ret i32 %i.0
}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/masked-memory-ops.ll b/llvm/test/Transforms/PhaseOrdering/X86/masked-memory-ops.ll
index a7c250b624ee2..eec8910fa69e2 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/masked-memory-ops.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/masked-memory-ops.ll
@@ -5,52 +5,49 @@
target triple = "x86_64--"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
-declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x i32>, <8 x float>) #0
-declare void @llvm.masked.store.v8f32.p0v8f32(<8 x float>, <8 x float>*, i32, <8 x i1>)
+declare void @llvm.x86.avx.maskstore.ps.256(ptr, <8 x i32>, <8 x float>) #0
+declare void @llvm.masked.store.v8f32.p0(<8 x float>, ptr, i32, <8 x i1>)
; PR11210: If we have been able to replace a AVX/AVX2 masked store with a
; generic masked store intrinsic, then we should be able to remove dead
; masked stores.
-define void @PR11210_v8f32_maskstore_maskstore(i8* %ptr, <8 x float> %x, <8 x float> %y, <8 x i32> %src) {
+define void @PR11210_v8f32_maskstore_maskstore(ptr %ptr, <8 x float> %x, <8 x float> %y, <8 x i32> %src) {
; CHECK-LABEL: @PR11210_v8f32_maskstore_maskstore(
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <8 x i32> [[SRC:%.*]], zeroinitializer
-; CHECK-NEXT: [[CASTVEC:%.*]] = bitcast i8* [[PTR:%.*]] to <8 x float>*
-; CHECK-NEXT: tail call void @llvm.masked.store.v8f32.p0v8f32(<8 x float> [[Y:%.*]], <8 x float>* [[CASTVEC]], i32 1, <8 x i1> [[CMP]])
+; CHECK-NEXT: tail call void @llvm.masked.store.v8f32.p0(<8 x float> [[Y:%.*]], ptr [[PTR:%.*]], i32 1, <8 x i1> [[CMP]])
; CHECK-NEXT: ret void
;
%cmp = icmp sgt <8 x i32> %src, zeroinitializer
%mask = sext <8 x i1> %cmp to <8 x i32>
- call void @llvm.x86.avx.maskstore.ps.256(i8* %ptr, <8 x i32> %mask, <8 x float> %x)
- call void @llvm.x86.avx.maskstore.ps.256(i8* %ptr, <8 x i32> %mask, <8 x float> %y)
+ call void @llvm.x86.avx.maskstore.ps.256(ptr %ptr, <8 x i32> %mask, <8 x float> %x)
+ call void @llvm.x86.avx.maskstore.ps.256(ptr %ptr, <8 x i32> %mask, <8 x float> %y)
ret void
}
; The contents of %mask are unknown so we don't replace this with a generic masked.store.
-define void @PR11210_v8f32_maskstore_maskstore_raw_mask(i8* %ptr, <8 x float> %x, <8 x float> %y, <8 x i32> %mask) {
+define void @PR11210_v8f32_maskstore_maskstore_raw_mask(ptr %ptr, <8 x float> %x, <8 x float> %y, <8 x i32> %mask) {
; CHECK-LABEL: @PR11210_v8f32_maskstore_maskstore_raw_mask(
-; CHECK-NEXT: tail call void @llvm.x86.avx.maskstore.ps.256(i8* [[PTR:%.*]], <8 x i32> [[MASK:%.*]], <8 x float> [[X:%.*]])
-; CHECK-NEXT: tail call void @llvm.x86.avx.maskstore.ps.256(i8* [[PTR]], <8 x i32> [[MASK]], <8 x float> [[Y:%.*]])
+; CHECK-NEXT: tail call void @llvm.x86.avx.maskstore.ps.256(ptr [[PTR:%.*]], <8 x i32> [[MASK:%.*]], <8 x float> [[X:%.*]])
+; CHECK-NEXT: tail call void @llvm.x86.avx.maskstore.ps.256(ptr [[PTR]], <8 x i32> [[MASK]], <8 x float> [[Y:%.*]])
; CHECK-NEXT: ret void
;
- call void @llvm.x86.avx.maskstore.ps.256(i8* %ptr, <8 x i32> %mask, <8 x float> %x)
- call void @llvm.x86.avx.maskstore.ps.256(i8* %ptr, <8 x i32> %mask, <8 x float> %y)
+ call void @llvm.x86.avx.maskstore.ps.256(ptr %ptr, <8 x i32> %mask, <8 x float> %x)
+ call void @llvm.x86.avx.maskstore.ps.256(ptr %ptr, <8 x i32> %mask, <8 x float> %y)
ret void
}
; Mix AVX and generic masked stores.
-define void @PR11210_v8f32_mstore_maskstore(i8* %ptr, <8 x float> %x, <8 x float> %y, <8 x i32> %src) {
+define void @PR11210_v8f32_mstore_maskstore(ptr %ptr, <8 x float> %x, <8 x float> %y, <8 x i32> %src) {
; CHECK-LABEL: @PR11210_v8f32_mstore_maskstore(
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <8 x i32> [[SRC:%.*]], zeroinitializer
-; CHECK-NEXT: [[PTRF:%.*]] = bitcast i8* [[PTR:%.*]] to <8 x float>*
-; CHECK-NEXT: tail call void @llvm.masked.store.v8f32.p0v8f32(<8 x float> [[Y:%.*]], <8 x float>* [[PTRF]], i32 1, <8 x i1> [[CMP]])
+; CHECK-NEXT: tail call void @llvm.masked.store.v8f32.p0(<8 x float> [[Y:%.*]], ptr [[PTR:%.*]], i32 1, <8 x i1> [[CMP]])
; CHECK-NEXT: ret void
;
%cmp = icmp sgt <8 x i32> %src, zeroinitializer
%mask = sext <8 x i1> %cmp to <8 x i32>
- %ptrf = bitcast i8* %ptr to <8 x float>*
- tail call void @llvm.masked.store.v8f32.p0v8f32(<8 x float> %x, <8 x float>* %ptrf, i32 1, <8 x i1> %cmp)
- call void @llvm.x86.avx.maskstore.ps.256(i8* %ptr, <8 x i32> %mask, <8 x float> %y)
+ tail call void @llvm.masked.store.v8f32.p0(<8 x float> %x, ptr %ptr, i32 1, <8 x i1> %cmp)
+ call void @llvm.x86.avx.maskstore.ps.256(ptr %ptr, <8 x i32> %mask, <8 x float> %y)
ret void
}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/merge-functions.ll b/llvm/test/Transforms/PhaseOrdering/X86/merge-functions.ll
index ed8db4af23f47..0e751ce4e55a5 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/merge-functions.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/merge-functions.ll
@@ -28,62 +28,62 @@ entry:
br i1 %i1, label %bb10, label %bb11
bb10: ; preds = %entry
- store i8 1, i8* %_4, align 1
+ store i8 1, ptr %_4, align 1
br label %bb12
bb11: ; preds = %entry
%_6 = icmp eq i32 %c, 109
%i2 = zext i1 %_6 to i8
- store i8 %i2, i8* %_4, align 1
+ store i8 %i2, ptr %_4, align 1
br label %bb12
bb12: ; preds = %bb11, %bb10
- %i3 = load i8, i8* %_4, align 1
+ %i3 = load i8, ptr %_4, align 1
%i4 = trunc i8 %i3 to i1
br i1 %i4, label %bb7, label %bb8
bb8: ; preds = %bb12
%_8 = icmp eq i32 %c, 104
%i5 = zext i1 %_8 to i8
- store i8 %i5, i8* %_3, align 1
+ store i8 %i5, ptr %_3, align 1
br label %bb9
bb7: ; preds = %bb12
- store i8 1, i8* %_3, align 1
+ store i8 1, ptr %_3, align 1
br label %bb9
bb9: ; preds = %bb7, %bb8
- %i6 = load i8, i8* %_3, align 1
+ %i6 = load i8, ptr %_3, align 1
%i7 = trunc i8 %i6 to i1
br i1 %i7, label %bb4, label %bb5
bb5: ; preds = %bb9
%_10 = icmp eq i32 %c, 100
%i8 = zext i1 %_10 to i8
- store i8 %i8, i8* %_2, align 1
+ store i8 %i8, ptr %_2, align 1
br label %bb6
bb4: ; preds = %bb9
- store i8 1, i8* %_2, align 1
+ store i8 1, ptr %_2, align 1
br label %bb6
bb6: ; preds = %bb4, %bb5
- %i9 = load i8, i8* %_2, align 1
+ %i9 = load i8, ptr %_2, align 1
%i10 = trunc i8 %i9 to i1
br i1 %i10, label %bb1, label %bb2
bb2: ; preds = %bb6
%_12 = icmp eq i32 %c, 119
%i11 = zext i1 %_12 to i8
- store i8 %i11, i8* %i, align 1
+ store i8 %i11, ptr %i, align 1
br label %bb3
bb1: ; preds = %bb6
- store i8 1, i8* %i, align 1
+ store i8 1, ptr %i, align 1
br label %bb3
bb3: ; preds = %bb1, %bb2
- %i12 = load i8, i8* %i, align 1
+ %i12 = load i8, ptr %i, align 1
%i13 = trunc i8 %i12 to i1
ret i1 %i13
}
@@ -104,15 +104,15 @@ entry:
]
bb1: ; preds = %entry
- store i8 0, i8* %i, align 1
+ store i8 0, ptr %i, align 1
br label %bb3
bb2: ; preds = %entry, %entry, %entry, %entry, %entry
- store i8 1, i8* %i, align 1
+ store i8 1, ptr %i, align 1
br label %bb3
bb3: ; preds = %bb2, %bb1
- %i1 = load i8, i8* %i, align 1
+ %i1 = load i8, ptr %i, align 1
%i2 = trunc i8 %i1 to i1
ret i1 %i2
}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/nancvt.ll b/llvm/test/Transforms/PhaseOrdering/X86/nancvt.ll
index 1ea183b46a4bf..2127ee2353b04 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/nancvt.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/nancvt.ll
@@ -24,24 +24,24 @@ target triple = "i686-apple-darwin8"
define i32 @main() {
; CHECK-LABEL: @main(
; CHECK-NEXT: entry:
-; CHECK-NEXT: store volatile i32 2147027116, i32* @var, align 4
-; CHECK-NEXT: store volatile i32 -1610612736, i32* @var, align 4
-; CHECK-NEXT: store volatile i32 2147027116, i32* @var, align 4
-; CHECK-NEXT: store volatile i32 -2147483648, i32* @var, align 4
-; CHECK-NEXT: store volatile i32 2147027116, i32* @var, align 4
-; CHECK-NEXT: store volatile i32 -1073741824, i32* @var, align 4
-; CHECK-NEXT: store volatile i32 2147228864, i32* @var, align 4
-; CHECK-NEXT: store volatile i32 2147228864, i32* @var, align 4
-; CHECK-NEXT: store volatile i32 2147228864, i32* @var, align 4
-; CHECK-NEXT: store volatile i32 2147027116, i32* @var, align 4
-; CHECK-NEXT: store volatile i32 -1610612736, i32* @var, align 4
-; CHECK-NEXT: store volatile i32 2147027116, i32* @var, align 4
-; CHECK-NEXT: store volatile i32 -2147483648, i32* @var, align 4
-; CHECK-NEXT: store volatile i32 2147027116, i32* @var, align 4
-; CHECK-NEXT: store volatile i32 -1073741824, i32* @var, align 4
-; CHECK-NEXT: store volatile i32 2147228864, i32* @var, align 4
-; CHECK-NEXT: store volatile i32 2147228864, i32* @var, align 4
-; CHECK-NEXT: store volatile i32 2147228864, i32* @var, align 4
+; CHECK-NEXT: store volatile i32 2147027116, ptr @var, align 4
+; CHECK-NEXT: store volatile i32 -1610612736, ptr @var, align 4
+; CHECK-NEXT: store volatile i32 2147027116, ptr @var, align 4
+; CHECK-NEXT: store volatile i32 -2147483648, ptr @var, align 4
+; CHECK-NEXT: store volatile i32 2147027116, ptr @var, align 4
+; CHECK-NEXT: store volatile i32 -1073741824, ptr @var, align 4
+; CHECK-NEXT: store volatile i32 2147228864, ptr @var, align 4
+; CHECK-NEXT: store volatile i32 2147228864, ptr @var, align 4
+; CHECK-NEXT: store volatile i32 2147228864, ptr @var, align 4
+; CHECK-NEXT: store volatile i32 2147027116, ptr @var, align 4
+; CHECK-NEXT: store volatile i32 -1610612736, ptr @var, align 4
+; CHECK-NEXT: store volatile i32 2147027116, ptr @var, align 4
+; CHECK-NEXT: store volatile i32 -2147483648, ptr @var, align 4
+; CHECK-NEXT: store volatile i32 2147027116, ptr @var, align 4
+; CHECK-NEXT: store volatile i32 -1073741824, ptr @var, align 4
+; CHECK-NEXT: store volatile i32 2147228864, ptr @var, align 4
+; CHECK-NEXT: store volatile i32 2147228864, ptr @var, align 4
+; CHECK-NEXT: store volatile i32 2147228864, ptr @var, align 4
; CHECK-NEXT: ret i32 undef
;
entry:
@@ -50,150 +50,118 @@ entry:
%uf = alloca %struct..0anon, align 4
%ud = alloca %struct..1anon, align 8
%"alloca point" = bitcast i32 0 to i32
- store i32 0, i32* %i, align 4
+ store i32 0, ptr %i, align 4
br label %bb23
bb: ; preds = %bb23
- %t = load i32, i32* %i, align 4
- %t1 = getelementptr [3 x i32], [3 x i32]* @fnan, i32 0, i32 %t
- %t2 = load i32, i32* %t1, align 4
- %t3 = getelementptr %struct..0anon, %struct..0anon* %uf, i32 0, i32 0
- %t34 = bitcast float* %t3 to i32*
- store i32 %t2, i32* %t34, align 4
- %t5 = getelementptr %struct..0anon, %struct..0anon* %uf, i32 0, i32 0
- %t6 = load float, float* %t5, align 4
+ %t = load i32, ptr %i, align 4
+ %t1 = getelementptr [3 x i32], ptr @fnan, i32 0, i32 %t
+ %t2 = load i32, ptr %t1, align 4
+ store i32 %t2, ptr %uf, align 4
+ %t6 = load float, ptr %uf, align 4
%t67 = fpext float %t6 to double
- %t8 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0
- store double %t67, double* %t8, align 8
- %t9 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0
- %t910 = bitcast double* %t9 to i64*
- %t11 = load i64, i64* %t910, align 8
+ store double %t67, ptr %ud, align 8
+ %t11 = load i64, ptr %ud, align 8
%t1112 = trunc i64 %t11 to i32
%t13 = and i32 %t1112, -1
- %t14 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0
- %t1415 = bitcast double* %t14 to i64*
- %t16 = load i64, i64* %t1415, align 8
+ %t16 = load i64, ptr %ud, align 8
%.cast = zext i32 32 to i64
%t17 = ashr i64 %t16, %.cast
%t1718 = trunc i64 %t17 to i32
- %t19 = getelementptr [10 x i8], [10 x i8]* @.str, i32 0, i32 0
- store volatile i32 %t1718, i32* @var
- store volatile i32 %t13, i32* @var
- %t21 = load i32, i32* %i, align 4
+ store volatile i32 %t1718, ptr @var
+ store volatile i32 %t13, ptr @var
+ %t21 = load i32, ptr %i, align 4
%t22 = add i32 %t21, 1
- store i32 %t22, i32* %i, align 4
+ store i32 %t22, ptr %i, align 4
br label %bb23
bb23: ; preds = %bb, %entry
- %t24 = load i32, i32* %i, align 4
+ %t24 = load i32, ptr %i, align 4
%t25 = icmp sle i32 %t24, 2
%t2526 = zext i1 %t25 to i8
%toBool = icmp ne i8 %t2526, 0
br i1 %toBool, label %bb, label %bb27
bb27: ; preds = %bb23
- store i32 0, i32* %i, align 4
+ store i32 0, ptr %i, align 4
br label %bb46
bb28: ; preds = %bb46
- %t29 = load i32, i32* %i, align 4
- %t30 = getelementptr [3 x i64], [3 x i64]* @dnan, i32 0, i32 %t29
- %t31 = load i64, i64* %t30, align 8
- %t32 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0
- %t3233 = bitcast double* %t32 to i64*
- store i64 %t31, i64* %t3233, align 8
- %t35 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0
- %t36 = load double, double* %t35, align 8
+ %t29 = load i32, ptr %i, align 4
+ %t30 = getelementptr [3 x i64], ptr @dnan, i32 0, i32 %t29
+ %t31 = load i64, ptr %t30, align 8
+ store i64 %t31, ptr %ud, align 8
+ %t36 = load double, ptr %ud, align 8
%t3637 = fptrunc double %t36 to float
- %t38 = getelementptr %struct..0anon, %struct..0anon* %uf, i32 0, i32 0
- store float %t3637, float* %t38, align 4
- %t39 = getelementptr %struct..0anon, %struct..0anon* %uf, i32 0, i32 0
- %t3940 = bitcast float* %t39 to i32*
- %t41 = load i32, i32* %t3940, align 4
- %t42 = getelementptr [6 x i8], [6 x i8]* @.str1, i32 0, i32 0
- store volatile i32 %t41, i32* @var
- %t44 = load i32, i32* %i, align 4
+ store float %t3637, ptr %uf, align 4
+ %t41 = load i32, ptr %uf, align 4
+ store volatile i32 %t41, ptr @var
+ %t44 = load i32, ptr %i, align 4
%t45 = add i32 %t44, 1
- store i32 %t45, i32* %i, align 4
+ store i32 %t45, ptr %i, align 4
br label %bb46
bb46: ; preds = %bb28, %bb27
- %t47 = load i32, i32* %i, align 4
+ %t47 = load i32, ptr %i, align 4
%t48 = icmp sle i32 %t47, 2
%t4849 = zext i1 %t48 to i8
%toBool50 = icmp ne i8 %t4849, 0
br i1 %toBool50, label %bb28, label %bb51
bb51: ; preds = %bb46
- store i32 0, i32* %i, align 4
+ store i32 0, ptr %i, align 4
br label %bb78
bb52: ; preds = %bb78
- %t53 = load i32, i32* %i, align 4
- %t54 = getelementptr [3 x i32], [3 x i32]* @fsnan, i32 0, i32 %t53
- %t55 = load i32, i32* %t54, align 4
- %t56 = getelementptr %struct..0anon, %struct..0anon* %uf, i32 0, i32 0
- %t5657 = bitcast float* %t56 to i32*
- store i32 %t55, i32* %t5657, align 4
- %t58 = getelementptr %struct..0anon, %struct..0anon* %uf, i32 0, i32 0
- %t59 = load float, float* %t58, align 4
+ %t53 = load i32, ptr %i, align 4
+ %t54 = getelementptr [3 x i32], ptr @fsnan, i32 0, i32 %t53
+ %t55 = load i32, ptr %t54, align 4
+ store i32 %t55, ptr %uf, align 4
+ %t59 = load float, ptr %uf, align 4
%t5960 = fpext float %t59 to double
- %t61 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0
- store double %t5960, double* %t61, align 8
- %t62 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0
- %t6263 = bitcast double* %t62 to i64*
- %t64 = load i64, i64* %t6263, align 8
+ store double %t5960, ptr %ud, align 8
+ %t64 = load i64, ptr %ud, align 8
%t6465 = trunc i64 %t64 to i32
%t66 = and i32 %t6465, -1
- %t68 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0
- %t6869 = bitcast double* %t68 to i64*
- %t70 = load i64, i64* %t6869, align 8
+ %t70 = load i64, ptr %ud, align 8
%.cast71 = zext i32 32 to i64
%t72 = ashr i64 %t70, %.cast71
%t7273 = trunc i64 %t72 to i32
- %t74 = getelementptr [10 x i8], [10 x i8]* @.str, i32 0, i32 0
- store volatile i32 %t7273, i32* @var
- store volatile i32 %t66, i32* @var
- %t76 = load i32, i32* %i, align 4
+ store volatile i32 %t7273, ptr @var
+ store volatile i32 %t66, ptr @var
+ %t76 = load i32, ptr %i, align 4
%t77 = add i32 %t76, 1
- store i32 %t77, i32* %i, align 4
+ store i32 %t77, ptr %i, align 4
br label %bb78
bb78: ; preds = %bb52, %bb51
- %t79 = load i32, i32* %i, align 4
+ %t79 = load i32, ptr %i, align 4
%t80 = icmp sle i32 %t79, 2
%t8081 = zext i1 %t80 to i8
%toBool82 = icmp ne i8 %t8081, 0
br i1 %toBool82, label %bb52, label %bb83
bb83: ; preds = %bb78
- store i32 0, i32* %i, align 4
+ store i32 0, ptr %i, align 4
br label %bb101
bb84: ; preds = %bb101
- %t85 = load i32, i32* %i, align 4
- %t86 = getelementptr [3 x i64], [3 x i64]* @dsnan, i32 0, i32 %t85
- %t87 = load i64, i64* %t86, align 8
- %t88 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0
- %t8889 = bitcast double* %t88 to i64*
- store i64 %t87, i64* %t8889, align 8
- %t90 = getelementptr %struct..1anon, %struct..1anon* %ud, i32 0, i32 0
- %t91 = load double, double* %t90, align 8
+ %t85 = load i32, ptr %i, align 4
+ %t86 = getelementptr [3 x i64], ptr @dsnan, i32 0, i32 %t85
+ %t87 = load i64, ptr %t86, align 8
+ store i64 %t87, ptr %ud, align 8
+ %t91 = load double, ptr %ud, align 8
%t9192 = fptrunc double %t91 to float
- %t93 = getelementptr %struct..0anon, %struct..0anon* %uf, i32 0, i32 0
- store float %t9192, float* %t93, align 4
- %t94 = getelementptr %struct..0anon, %struct..0anon* %uf, i32 0, i32 0
- %t9495 = bitcast float* %t94 to i32*
- %t96 = load i32, i32* %t9495, align 4
- %t97 = getelementptr [6 x i8], [6 x i8]* @.str1, i32 0, i32 0
- store volatile i32 %t96, i32* @var
- %t99 = load i32, i32* %i, align 4
+ store float %t9192, ptr %uf, align 4
+ %t96 = load i32, ptr %uf, align 4
+ store volatile i32 %t96, ptr @var
+ %t99 = load i32, ptr %i, align 4
%t100 = add i32 %t99, 1
- store i32 %t100, i32* %i, align 4
+ store i32 %t100, ptr %i, align 4
br label %bb101
bb101: ; preds = %bb84, %bb83
- %t102 = load i32, i32* %i, align 4
+ %t102 = load i32, ptr %i, align 4
%t103 = icmp sle i32 %t102, 2
%t103104 = zext i1 %t103 to i8
%toBool105 = icmp ne i8 %t103104, 0
@@ -203,6 +171,6 @@ bb106: ; preds = %bb101
br label %return
return: ; preds = %bb106
- %retval107 = load i32, i32* %retval
+ %retval107 = load i32, ptr %retval
ret i32 %retval107
}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/peel-before-lv-to-enable-vectorization.ll b/llvm/test/Transforms/PhaseOrdering/X86/peel-before-lv-to-enable-vectorization.ll
index 946eaf0b09ba9..73ca87f34de06 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/peel-before-lv-to-enable-vectorization.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/peel-before-lv-to-enable-vectorization.ll
@@ -9,14 +9,14 @@ target triple = "x86_64-apple-macosx"
;
; Test case from PR47671.
-define i32 @test(i32* readonly %p, i32* readnone %q) {
+define i32 @test(ptr readonly %p, ptr readnone %q) {
; CHECK-LABEL: define i32 @test(
; CHECK: vector.body:
; CHECK: %index.next = add nuw i64 %index, 8
; CHECK: middle.block:
;
entry:
- %cmp.not7 = icmp eq i32* %p, %q
+ %cmp.not7 = icmp eq ptr %p, %q
br i1 %cmp.not7, label %exit, label %loop.ph
loop.ph:
@@ -25,13 +25,13 @@ loop.ph:
loop:
%sum = phi i32 [ %sum.next, %loop ], [ 0, %loop.ph ]
%first = phi i1 [ false, %loop ], [ true, %loop.ph ]
- %iv = phi i32* [ %iv.next, %loop ], [ %p, %loop.ph ]
+ %iv = phi ptr [ %iv.next, %loop ], [ %p, %loop.ph ]
%add = add nsw i32 %sum, 2
%spec.select = select i1 %first, i32 %sum, i32 %add
- %lv = load i32, i32* %iv, align 4
+ %lv = load i32, ptr %iv, align 4
%sum.next = add nsw i32 %lv, %spec.select
- %iv.next = getelementptr inbounds i32, i32* %iv, i64 1
- %cmp.not = icmp eq i32* %iv.next, %q
+ %iv.next = getelementptr inbounds i32, ptr %iv, i64 1
+ %cmp.not = icmp eq ptr %iv.next, %q
br i1 %cmp.not, label %loopexit, label %loop
loopexit:
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/pixel-splat.ll b/llvm/test/Transforms/PhaseOrdering/X86/pixel-splat.ll
index 93e219655ccd2..f484b04a90776 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/pixel-splat.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/pixel-splat.ll
@@ -18,7 +18,7 @@ target triple = "x86_64-apple-macosx10.15.0"
;
; We are looking for the shifts to get combined into mul along with vectorization.
-define void @loop_or(i8* noalias %pIn, i32* noalias %pOut, i32 %s) {
+define void @loop_or(ptr noalias %pIn, ptr noalias %pOut, i32 %s) {
; CHECK-LABEL: @loop_or(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[S:%.*]], 0
@@ -32,24 +32,20 @@ define void @loop_or(i8* noalias %pIn, i32* noalias %pOut, i32 %s) {
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, i8* [[PIN:%.*]], i64 [[INDEX]]
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i8>*
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, <4 x i8>* [[TMP1]], align 1
-; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8* [[TMP0]], i64 4
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to <4 x i8>*
-; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i8>, <4 x i8>* [[TMP3]], align 1
+; CHECK-NEXT: [[TMP0:%.*]] = getelementptr inbounds i8, ptr [[PIN:%.*]], i64 [[INDEX]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP0]], align 1
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 4
+; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i8>, ptr [[TMP2]], align 1
; CHECK-NEXT: [[TMP4:%.*]] = zext <4 x i8> [[WIDE_LOAD]] to <4 x i32>
; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i8> [[WIDE_LOAD4]] to <4 x i32>
; CHECK-NEXT: [[TMP6:%.*]] = mul nuw nsw <4 x i32> [[TMP4]], <i32 65793, i32 65793, i32 65793, i32 65793>
; CHECK-NEXT: [[TMP7:%.*]] = mul nuw nsw <4 x i32> [[TMP5]], <i32 65793, i32 65793, i32 65793, i32 65793>
; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i32> [[TMP6]], <i32 -16777216, i32 -16777216, i32 -16777216, i32 -16777216>
; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i32> [[TMP7]], <i32 -16777216, i32 -16777216, i32 -16777216, i32 -16777216>
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, i32* [[POUT:%.*]], i64 [[INDEX]]
-; CHECK-NEXT: [[TMP11:%.*]] = bitcast i32* [[TMP10]] to <4 x i32>*
-; CHECK-NEXT: store <4 x i32> [[TMP8]], <4 x i32>* [[TMP11]], align 4
-; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, i32* [[TMP10]], i64 4
-; CHECK-NEXT: [[TMP13:%.*]] = bitcast i32* [[TMP12]] to <4 x i32>*
-; CHECK-NEXT: store <4 x i32> [[TMP9]], <4 x i32>* [[TMP13]], align 4
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[POUT:%.*]], i64 [[INDEX]]
+; CHECK-NEXT: store <4 x i32> [[TMP8]], ptr [[TMP10]], align 4
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i64 4
+; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr [[TMP12]], align 4
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
@@ -61,13 +57,13 @@ define void @loop_or(i8* noalias %pIn, i32* noalias %pOut, i32 %s) {
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ], [ [[INDVARS_IV_PH]], [[FOR_BODY_PREHEADER5]] ]
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, i8* [[PIN]], i64 [[INDVARS_IV]]
-; CHECK-NEXT: [[TMP15:%.*]] = load i8, i8* [[ARRAYIDX]], align 1
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[PIN]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[TMP15:%.*]] = load i8, ptr [[ARRAYIDX]], align 1
; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[TMP15]] to i32
; CHECK-NEXT: [[OR2:%.*]] = mul nuw nsw i32 [[CONV]], 65793
; CHECK-NEXT: [[OR3:%.*]] = or i32 [[OR2]], -16777216
-; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, i32* [[POUT]], i64 [[INDVARS_IV]]
-; CHECK-NEXT: store i32 [[OR3]], i32* [[ARRAYIDX5]], align 4
+; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i32, ptr [[POUT]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: store i32 [[OR3]], ptr [[ARRAYIDX5]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]]
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]]
@@ -87,8 +83,8 @@ for.cond.cleanup:
for.body:
%idxprom = sext i32 %i.0 to i64
- %arrayidx = getelementptr inbounds i8, i8* %pIn, i64 %idxprom
- %0 = load i8, i8* %arrayidx, align 1
+ %arrayidx = getelementptr inbounds i8, ptr %pIn, i64 %idxprom
+ %0 = load i8, ptr %arrayidx, align 1
%conv = zext i8 %0 to i32
%shl = shl i32 %conv, 8
%or = or i32 %conv, %shl
@@ -96,8 +92,8 @@ for.body:
%or2 = or i32 %or, %shl1
%or3 = or i32 %or2, -16777216
%idxprom4 = sext i32 %i.0 to i64
- %arrayidx5 = getelementptr inbounds i32, i32* %pOut, i64 %idxprom4
- store i32 %or3, i32* %arrayidx5, align 4
+ %arrayidx5 = getelementptr inbounds i32, ptr %pOut, i64 %idxprom4
+ store i32 %or3, ptr %arrayidx5, align 4
br label %for.inc
for.inc:
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll b/llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll
index c8def48204e1a..b52dd6743649a 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll
@@ -7,24 +7,24 @@ target triple = "x86_64-unknown-linux-gnu"
; FIXME: The br -> switch conversion blocks vectorization.
-define dso_local void @test(i32* %start, i32* %end) #0 {
+define dso_local void @test(ptr %start, ptr %end) #0 {
; CHECK-LABEL: @test(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[I11_NOT1:%.*]] = icmp eq i32* [[START:%.*]], [[END:%.*]]
+; CHECK-NEXT: [[I11_NOT1:%.*]] = icmp eq ptr [[START:%.*]], [[END:%.*]]
; CHECK-NEXT: br i1 [[I11_NOT1]], label [[EXIT:%.*]], label [[BB12:%.*]]
; CHECK: bb12:
-; CHECK-NEXT: [[PTR2:%.*]] = phi i32* [ [[PTR_NEXT:%.*]], [[LATCH:%.*]] ], [ [[START]], [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[VAL:%.*]] = load i32, i32* [[PTR2]], align 4
+; CHECK-NEXT: [[PTR2:%.*]] = phi ptr [ [[PTR_NEXT:%.*]], [[LATCH:%.*]] ], [ [[START]], [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[PTR2]], align 4
; CHECK-NEXT: switch i32 [[VAL]], label [[LATCH]] [
; CHECK-NEXT: i32 -12, label [[STORE:%.*]]
; CHECK-NEXT: i32 13, label [[STORE]]
; CHECK-NEXT: ]
; CHECK: store:
-; CHECK-NEXT: store i32 42, i32* [[PTR2]], align 4
+; CHECK-NEXT: store i32 42, ptr [[PTR2]], align 4
; CHECK-NEXT: br label [[LATCH]]
; CHECK: latch:
-; CHECK-NEXT: [[PTR_NEXT]] = getelementptr inbounds i32, i32* [[PTR2]], i64 1
-; CHECK-NEXT: [[I11_NOT:%.*]] = icmp eq i32* [[PTR_NEXT]], [[END]]
+; CHECK-NEXT: [[PTR_NEXT]] = getelementptr inbounds i32, ptr [[PTR2]], i64 1
+; CHECK-NEXT: [[I11_NOT:%.*]] = icmp eq ptr [[PTR_NEXT]], [[END]]
; CHECK-NEXT: br i1 [[I11_NOT]], label [[EXIT]], label [[BB12]]
; CHECK: exit:
; CHECK-NEXT: ret void
@@ -33,23 +33,23 @@ entry:
br label %header
header:
- %ptr = phi i32* [ %start, %entry ], [ %ptr.next, %latch ]
- %i11 = icmp ne i32* %ptr, %end
+ %ptr = phi ptr [ %start, %entry ], [ %ptr.next, %latch ]
+ %i11 = icmp ne ptr %ptr, %end
br i1 %i11, label %bb12, label %exit
bb12:
- %val = load i32, i32* %ptr, align 4
+ %val = load i32, ptr %ptr, align 4
%c1 = icmp eq i32 %val, 13
%c2 = icmp eq i32 %val, -12
%c3 = or i1 %c1, %c2
br i1 %c3, label %store, label %latch
store:
- store i32 42, i32* %ptr, align 4
+ store i32 42, ptr %ptr, align 4
br label %latch
latch:
- %ptr.next = getelementptr inbounds i32, i32* %ptr, i32 1
+ %ptr.next = getelementptr inbounds i32, ptr %ptr, i32 1
br label %header
exit:
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/pr50555.ll b/llvm/test/Transforms/PhaseOrdering/X86/pr50555.ll
index 39b7d6792275a..7b7658279a897 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/pr50555.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/pr50555.ll
@@ -2,434 +2,419 @@
; RUN: opt < %s -O3 -S -mtriple=x86_64-- | FileCheck %s --check-prefixes=SSE
; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mattr=avx | FileCheck %s --check-prefixes=AVX
-define void @trunc_through_one_add(i16* noalias %0, i8* noalias readonly %1) {
+define void @trunc_through_one_add(ptr noalias %0, ptr noalias readonly %1) {
; SSE-LABEL: @trunc_through_one_add(
-; SSE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP1:%.*]] to <8 x i8>*
-; SSE-NEXT: [[TMP4:%.*]] = load <8 x i8>, <8 x i8>* [[TMP3]], align 1
+; SSE-NEXT: [[TMP4:%.*]] = load <8 x i8>, ptr [[TMP1:%.*]], align 1
; SSE-NEXT: [[TMP5:%.*]] = zext <8 x i8> [[TMP4]] to <8 x i16>
; SSE-NEXT: [[TMP6:%.*]] = lshr <8 x i16> [[TMP5]], <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
; SSE-NEXT: [[TMP7:%.*]] = add nuw nsw <8 x i16> [[TMP6]], [[TMP5]]
; SSE-NEXT: [[TMP8:%.*]] = lshr <8 x i16> [[TMP7]], <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
-; SSE-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP0:%.*]] to <8 x i16>*
-; SSE-NEXT: store <8 x i16> [[TMP8]], <8 x i16>* [[TMP9]], align 2
-; SSE-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, i8* [[TMP1]], i64 8
-; SSE-NEXT: [[TMP11:%.*]] = getelementptr inbounds i16, i16* [[TMP0]], i64 8
-; SSE-NEXT: [[TMP12:%.*]] = bitcast i8* [[TMP10]] to <8 x i8>*
-; SSE-NEXT: [[TMP13:%.*]] = load <8 x i8>, <8 x i8>* [[TMP12]], align 1
+; SSE-NEXT: store <8 x i16> [[TMP8]], ptr [[TMP0:%.*]], align 2
+; SSE-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 8
+; SSE-NEXT: [[TMP11:%.*]] = getelementptr inbounds i16, ptr [[TMP0]], i64 8
+; SSE-NEXT: [[TMP13:%.*]] = load <8 x i8>, ptr [[TMP10]], align 1
; SSE-NEXT: [[TMP14:%.*]] = zext <8 x i8> [[TMP13]] to <8 x i16>
; SSE-NEXT: [[TMP15:%.*]] = lshr <8 x i16> [[TMP14]], <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
; SSE-NEXT: [[TMP16:%.*]] = add nuw nsw <8 x i16> [[TMP15]], [[TMP14]]
; SSE-NEXT: [[TMP17:%.*]] = lshr <8 x i16> [[TMP16]], <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
-; SSE-NEXT: [[TMP18:%.*]] = bitcast i16* [[TMP11]] to <8 x i16>*
-; SSE-NEXT: store <8 x i16> [[TMP17]], <8 x i16>* [[TMP18]], align 2
+; SSE-NEXT: store <8 x i16> [[TMP17]], ptr [[TMP11]], align 2
; SSE-NEXT: ret void
;
; AVX-LABEL: @trunc_through_one_add(
-; AVX-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP1:%.*]] to <16 x i8>*
-; AVX-NEXT: [[TMP4:%.*]] = load <16 x i8>, <16 x i8>* [[TMP3]], align 1
+; AVX-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr [[TMP1:%.*]], align 1
; AVX-NEXT: [[TMP5:%.*]] = zext <16 x i8> [[TMP4]] to <16 x i16>
; AVX-NEXT: [[TMP6:%.*]] = lshr <16 x i16> [[TMP5]], <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
; AVX-NEXT: [[TMP7:%.*]] = add nuw nsw <16 x i16> [[TMP6]], [[TMP5]]
; AVX-NEXT: [[TMP8:%.*]] = lshr <16 x i16> [[TMP7]], <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
-; AVX-NEXT: [[TMP9:%.*]] = bitcast i16* [[TMP0:%.*]] to <16 x i16>*
-; AVX-NEXT: store <16 x i16> [[TMP8]], <16 x i16>* [[TMP9]], align 2
+; AVX-NEXT: store <16 x i16> [[TMP8]], ptr [[TMP0:%.*]], align 2
; AVX-NEXT: ret void
;
- %3 = load i8, i8* %1, align 1
+ %3 = load i8, ptr %1, align 1
%4 = zext i8 %3 to i32
%5 = lshr i32 %4, 1
%6 = add nuw nsw i32 %5, %4
%7 = lshr i32 %6, 2
%8 = trunc i32 %7 to i16
- store i16 %8, i16* %0, align 2
- %9 = getelementptr inbounds i8, i8* %1, i64 1
- %10 = load i8, i8* %9, align 1
+ store i16 %8, ptr %0, align 2
+ %9 = getelementptr inbounds i8, ptr %1, i64 1
+ %10 = load i8, ptr %9, align 1
%11 = zext i8 %10 to i32
%12 = lshr i32 %11, 1
%13 = add nuw nsw i32 %12, %11
%14 = lshr i32 %13, 2
%15 = trunc i32 %14 to i16
- %16 = getelementptr inbounds i16, i16* %0, i64 1
- store i16 %15, i16* %16, align 2
- %17 = getelementptr inbounds i8, i8* %1, i64 2
- %18 = load i8, i8* %17, align 1
+ %16 = getelementptr inbounds i16, ptr %0, i64 1
+ store i16 %15, ptr %16, align 2
+ %17 = getelementptr inbounds i8, ptr %1, i64 2
+ %18 = load i8, ptr %17, align 1
%19 = zext i8 %18 to i32
%20 = lshr i32 %19, 1
%21 = add nuw nsw i32 %20, %19
%22 = lshr i32 %21, 2
%23 = trunc i32 %22 to i16
- %24 = getelementptr inbounds i16, i16* %0, i64 2
- store i16 %23, i16* %24, align 2
- %25 = getelementptr inbounds i8, i8* %1, i64 3
- %26 = load i8, i8* %25, align 1
+ %24 = getelementptr inbounds i16, ptr %0, i64 2
+ store i16 %23, ptr %24, align 2
+ %25 = getelementptr inbounds i8, ptr %1, i64 3
+ %26 = load i8, ptr %25, align 1
%27 = zext i8 %26 to i32
%28 = lshr i32 %27, 1
%29 = add nuw nsw i32 %28, %27
%30 = lshr i32 %29, 2
%31 = trunc i32 %30 to i16
- %32 = getelementptr inbounds i16, i16* %0, i64 3
- store i16 %31, i16* %32, align 2
- %33 = getelementptr inbounds i8, i8* %1, i64 4
- %34 = load i8, i8* %33, align 1
+ %32 = getelementptr inbounds i16, ptr %0, i64 3
+ store i16 %31, ptr %32, align 2
+ %33 = getelementptr inbounds i8, ptr %1, i64 4
+ %34 = load i8, ptr %33, align 1
%35 = zext i8 %34 to i32
%36 = lshr i32 %35, 1
%37 = add nuw nsw i32 %36, %35
%38 = lshr i32 %37, 2
%39 = trunc i32 %38 to i16
- %40 = getelementptr inbounds i16, i16* %0, i64 4
- store i16 %39, i16* %40, align 2
- %41 = getelementptr inbounds i8, i8* %1, i64 5
- %42 = load i8, i8* %41, align 1
+ %40 = getelementptr inbounds i16, ptr %0, i64 4
+ store i16 %39, ptr %40, align 2
+ %41 = getelementptr inbounds i8, ptr %1, i64 5
+ %42 = load i8, ptr %41, align 1
%43 = zext i8 %42 to i32
%44 = lshr i32 %43, 1
%45 = add nuw nsw i32 %44, %43
%46 = lshr i32 %45, 2
%47 = trunc i32 %46 to i16
- %48 = getelementptr inbounds i16, i16* %0, i64 5
- store i16 %47, i16* %48, align 2
- %49 = getelementptr inbounds i8, i8* %1, i64 6
- %50 = load i8, i8* %49, align 1
+ %48 = getelementptr inbounds i16, ptr %0, i64 5
+ store i16 %47, ptr %48, align 2
+ %49 = getelementptr inbounds i8, ptr %1, i64 6
+ %50 = load i8, ptr %49, align 1
%51 = zext i8 %50 to i32
%52 = lshr i32 %51, 1
%53 = add nuw nsw i32 %52, %51
%54 = lshr i32 %53, 2
%55 = trunc i32 %54 to i16
- %56 = getelementptr inbounds i16, i16* %0, i64 6
- store i16 %55, i16* %56, align 2
- %57 = getelementptr inbounds i8, i8* %1, i64 7
- %58 = load i8, i8* %57, align 1
+ %56 = getelementptr inbounds i16, ptr %0, i64 6
+ store i16 %55, ptr %56, align 2
+ %57 = getelementptr inbounds i8, ptr %1, i64 7
+ %58 = load i8, ptr %57, align 1
%59 = zext i8 %58 to i32
%60 = lshr i32 %59, 1
%61 = add nuw nsw i32 %60, %59
%62 = lshr i32 %61, 2
%63 = trunc i32 %62 to i16
- %64 = getelementptr inbounds i16, i16* %0, i64 7
- store i16 %63, i16* %64, align 2
- %65 = getelementptr inbounds i8, i8* %1, i64 8
- %66 = load i8, i8* %65, align 1
+ %64 = getelementptr inbounds i16, ptr %0, i64 7
+ store i16 %63, ptr %64, align 2
+ %65 = getelementptr inbounds i8, ptr %1, i64 8
+ %66 = load i8, ptr %65, align 1
%67 = zext i8 %66 to i32
%68 = lshr i32 %67, 1
%69 = add nuw nsw i32 %68, %67
%70 = lshr i32 %69, 2
%71 = trunc i32 %70 to i16
- %72 = getelementptr inbounds i16, i16* %0, i64 8
- store i16 %71, i16* %72, align 2
- %73 = getelementptr inbounds i8, i8* %1, i64 9
- %74 = load i8, i8* %73, align 1
+ %72 = getelementptr inbounds i16, ptr %0, i64 8
+ store i16 %71, ptr %72, align 2
+ %73 = getelementptr inbounds i8, ptr %1, i64 9
+ %74 = load i8, ptr %73, align 1
%75 = zext i8 %74 to i32
%76 = lshr i32 %75, 1
%77 = add nuw nsw i32 %76, %75
%78 = lshr i32 %77, 2
%79 = trunc i32 %78 to i16
- %80 = getelementptr inbounds i16, i16* %0, i64 9
- store i16 %79, i16* %80, align 2
- %81 = getelementptr inbounds i8, i8* %1, i64 10
- %82 = load i8, i8* %81, align 1
+ %80 = getelementptr inbounds i16, ptr %0, i64 9
+ store i16 %79, ptr %80, align 2
+ %81 = getelementptr inbounds i8, ptr %1, i64 10
+ %82 = load i8, ptr %81, align 1
%83 = zext i8 %82 to i32
%84 = lshr i32 %83, 1
%85 = add nuw nsw i32 %84, %83
%86 = lshr i32 %85, 2
%87 = trunc i32 %86 to i16
- %88 = getelementptr inbounds i16, i16* %0, i64 10
- store i16 %87, i16* %88, align 2
- %89 = getelementptr inbounds i8, i8* %1, i64 11
- %90 = load i8, i8* %89, align 1
+ %88 = getelementptr inbounds i16, ptr %0, i64 10
+ store i16 %87, ptr %88, align 2
+ %89 = getelementptr inbounds i8, ptr %1, i64 11
+ %90 = load i8, ptr %89, align 1
%91 = zext i8 %90 to i32
%92 = lshr i32 %91, 1
%93 = add nuw nsw i32 %92, %91
%94 = lshr i32 %93, 2
%95 = trunc i32 %94 to i16
- %96 = getelementptr inbounds i16, i16* %0, i64 11
- store i16 %95, i16* %96, align 2
- %97 = getelementptr inbounds i8, i8* %1, i64 12
- %98 = load i8, i8* %97, align 1
+ %96 = getelementptr inbounds i16, ptr %0, i64 11
+ store i16 %95, ptr %96, align 2
+ %97 = getelementptr inbounds i8, ptr %1, i64 12
+ %98 = load i8, ptr %97, align 1
%99 = zext i8 %98 to i32
%100 = lshr i32 %99, 1
%101 = add nuw nsw i32 %100, %99
%102 = lshr i32 %101, 2
%103 = trunc i32 %102 to i16
- %104 = getelementptr inbounds i16, i16* %0, i64 12
- store i16 %103, i16* %104, align 2
- %105 = getelementptr inbounds i8, i8* %1, i64 13
- %106 = load i8, i8* %105, align 1
+ %104 = getelementptr inbounds i16, ptr %0, i64 12
+ store i16 %103, ptr %104, align 2
+ %105 = getelementptr inbounds i8, ptr %1, i64 13
+ %106 = load i8, ptr %105, align 1
%107 = zext i8 %106 to i32
%108 = lshr i32 %107, 1
%109 = add nuw nsw i32 %108, %107
%110 = lshr i32 %109, 2
%111 = trunc i32 %110 to i16
- %112 = getelementptr inbounds i16, i16* %0, i64 13
- store i16 %111, i16* %112, align 2
- %113 = getelementptr inbounds i8, i8* %1, i64 14
- %114 = load i8, i8* %113, align 1
+ %112 = getelementptr inbounds i16, ptr %0, i64 13
+ store i16 %111, ptr %112, align 2
+ %113 = getelementptr inbounds i8, ptr %1, i64 14
+ %114 = load i8, ptr %113, align 1
%115 = zext i8 %114 to i32
%116 = lshr i32 %115, 1
%117 = add nuw nsw i32 %116, %115
%118 = lshr i32 %117, 2
%119 = trunc i32 %118 to i16
- %120 = getelementptr inbounds i16, i16* %0, i64 14
- store i16 %119, i16* %120, align 2
- %121 = getelementptr inbounds i8, i8* %1, i64 15
- %122 = load i8, i8* %121, align 1
+ %120 = getelementptr inbounds i16, ptr %0, i64 14
+ store i16 %119, ptr %120, align 2
+ %121 = getelementptr inbounds i8, ptr %1, i64 15
+ %122 = load i8, ptr %121, align 1
%123 = zext i8 %122 to i32
%124 = lshr i32 %123, 1
%125 = add nuw nsw i32 %124, %123
%126 = lshr i32 %125, 2
%127 = trunc i32 %126 to i16
- %128 = getelementptr inbounds i16, i16* %0, i64 15
- store i16 %127, i16* %128, align 2
+ %128 = getelementptr inbounds i16, ptr %0, i64 15
+ store i16 %127, ptr %128, align 2
ret void
}
-define void @trunc_through_two_adds(i16* noalias %0, i8* noalias readonly %1, i8* noalias readonly %2) {
+define void @trunc_through_two_adds(ptr noalias %0, ptr noalias readonly %1, ptr noalias readonly %2) {
; SSE-LABEL: @trunc_through_two_adds(
-; SSE-NEXT: [[TMP4:%.*]] = bitcast i8* [[TMP1:%.*]] to <8 x i8>*
-; SSE-NEXT: [[TMP5:%.*]] = load <8 x i8>, <8 x i8>* [[TMP4]], align 1
+; SSE-NEXT: [[TMP5:%.*]] = load <8 x i8>, ptr [[TMP1:%.*]], align 1
; SSE-NEXT: [[TMP6:%.*]] = zext <8 x i8> [[TMP5]] to <8 x i16>
-; SSE-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP2:%.*]] to <8 x i8>*
-; SSE-NEXT: [[TMP8:%.*]] = load <8 x i8>, <8 x i8>* [[TMP7]], align 1
+; SSE-NEXT: [[TMP8:%.*]] = load <8 x i8>, ptr [[TMP2:%.*]], align 1
; SSE-NEXT: [[TMP9:%.*]] = zext <8 x i8> [[TMP8]] to <8 x i16>
; SSE-NEXT: [[TMP10:%.*]] = add nuw nsw <8 x i16> [[TMP9]], [[TMP6]]
; SSE-NEXT: [[TMP11:%.*]] = lshr <8 x i16> [[TMP10]], <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
; SSE-NEXT: [[TMP12:%.*]] = add nuw nsw <8 x i16> [[TMP11]], [[TMP10]]
; SSE-NEXT: [[TMP13:%.*]] = lshr <8 x i16> [[TMP12]], <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
-; SSE-NEXT: [[TMP14:%.*]] = bitcast i16* [[TMP0:%.*]] to <8 x i16>*
-; SSE-NEXT: store <8 x i16> [[TMP13]], <8 x i16>* [[TMP14]], align 2
-; SSE-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, i8* [[TMP1]], i64 8
-; SSE-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i64 8
-; SSE-NEXT: [[TMP17:%.*]] = getelementptr inbounds i16, i16* [[TMP0]], i64 8
-; SSE-NEXT: [[TMP18:%.*]] = bitcast i8* [[TMP15]] to <8 x i8>*
-; SSE-NEXT: [[TMP19:%.*]] = load <8 x i8>, <8 x i8>* [[TMP18]], align 1
+; SSE-NEXT: store <8 x i16> [[TMP13]], ptr [[TMP0:%.*]], align 2
+; SSE-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[TMP1]], i64 8
+; SSE-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[TMP2]], i64 8
+; SSE-NEXT: [[TMP17:%.*]] = getelementptr inbounds i16, ptr [[TMP0]], i64 8
+; SSE-NEXT: [[TMP19:%.*]] = load <8 x i8>, ptr [[TMP15]], align 1
; SSE-NEXT: [[TMP20:%.*]] = zext <8 x i8> [[TMP19]] to <8 x i16>
-; SSE-NEXT: [[TMP21:%.*]] = bitcast i8* [[TMP16]] to <8 x i8>*
-; SSE-NEXT: [[TMP22:%.*]] = load <8 x i8>, <8 x i8>* [[TMP21]], align 1
+; SSE-NEXT: [[TMP22:%.*]] = load <8 x i8>, ptr [[TMP16]], align 1
; SSE-NEXT: [[TMP23:%.*]] = zext <8 x i8> [[TMP22]] to <8 x i16>
; SSE-NEXT: [[TMP24:%.*]] = add nuw nsw <8 x i16> [[TMP23]], [[TMP20]]
; SSE-NEXT: [[TMP25:%.*]] = lshr <8 x i16> [[TMP24]], <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
; SSE-NEXT: [[TMP26:%.*]] = add nuw nsw <8 x i16> [[TMP25]], [[TMP24]]
; SSE-NEXT: [[TMP27:%.*]] = lshr <8 x i16> [[TMP26]], <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
-; SSE-NEXT: [[TMP28:%.*]] = bitcast i16* [[TMP17]] to <8 x i16>*
-; SSE-NEXT: store <8 x i16> [[TMP27]], <8 x i16>* [[TMP28]], align 2
+; SSE-NEXT: store <8 x i16> [[TMP27]], ptr [[TMP17]], align 2
; SSE-NEXT: ret void
;
; AVX-LABEL: @trunc_through_two_adds(
-; AVX-NEXT: [[TMP4:%.*]] = bitcast i8* [[TMP1:%.*]] to <16 x i8>*
-; AVX-NEXT: [[TMP5:%.*]] = load <16 x i8>, <16 x i8>* [[TMP4]], align 1
+; AVX-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr [[TMP1:%.*]], align 1
; AVX-NEXT: [[TMP6:%.*]] = zext <16 x i8> [[TMP5]] to <16 x i16>
-; AVX-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP2:%.*]] to <16 x i8>*
-; AVX-NEXT: [[TMP8:%.*]] = load <16 x i8>, <16 x i8>* [[TMP7]], align 1
+; AVX-NEXT: [[TMP8:%.*]] = load <16 x i8>, ptr [[TMP2:%.*]], align 1
; AVX-NEXT: [[TMP9:%.*]] = zext <16 x i8> [[TMP8]] to <16 x i16>
; AVX-NEXT: [[TMP10:%.*]] = add nuw nsw <16 x i16> [[TMP9]], [[TMP6]]
; AVX-NEXT: [[TMP11:%.*]] = lshr <16 x i16> [[TMP10]], <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
; AVX-NEXT: [[TMP12:%.*]] = add nuw nsw <16 x i16> [[TMP11]], [[TMP10]]
; AVX-NEXT: [[TMP13:%.*]] = lshr <16 x i16> [[TMP12]], <i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
-; AVX-NEXT: [[TMP14:%.*]] = bitcast i16* [[TMP0:%.*]] to <16 x i16>*
-; AVX-NEXT: store <16 x i16> [[TMP13]], <16 x i16>* [[TMP14]], align 2
+; AVX-NEXT: store <16 x i16> [[TMP13]], ptr [[TMP0:%.*]], align 2
; AVX-NEXT: ret void
;
- %4 = load i8, i8* %1, align 1
+ %4 = load i8, ptr %1, align 1
%5 = zext i8 %4 to i32
- %6 = load i8, i8* %2, align 1
+ %6 = load i8, ptr %2, align 1
%7 = zext i8 %6 to i32
%8 = add nuw nsw i32 %7, %5
%9 = lshr i32 %8, 1
%10 = add nuw nsw i32 %9, %8
%11 = lshr i32 %10, 2
%12 = trunc i32 %11 to i16
- store i16 %12, i16* %0, align 2
- %13 = getelementptr inbounds i8, i8* %1, i64 1
- %14 = load i8, i8* %13, align 1
+ store i16 %12, ptr %0, align 2
+ %13 = getelementptr inbounds i8, ptr %1, i64 1
+ %14 = load i8, ptr %13, align 1
%15 = zext i8 %14 to i32
- %16 = getelementptr inbounds i8, i8* %2, i64 1
- %17 = load i8, i8* %16, align 1
+ %16 = getelementptr inbounds i8, ptr %2, i64 1
+ %17 = load i8, ptr %16, align 1
%18 = zext i8 %17 to i32
%19 = add nuw nsw i32 %18, %15
%20 = lshr i32 %19, 1
%21 = add nuw nsw i32 %20, %19
%22 = lshr i32 %21, 2
%23 = trunc i32 %22 to i16
- %24 = getelementptr inbounds i16, i16* %0, i64 1
- store i16 %23, i16* %24, align 2
- %25 = getelementptr inbounds i8, i8* %1, i64 2
- %26 = load i8, i8* %25, align 1
+ %24 = getelementptr inbounds i16, ptr %0, i64 1
+ store i16 %23, ptr %24, align 2
+ %25 = getelementptr inbounds i8, ptr %1, i64 2
+ %26 = load i8, ptr %25, align 1
%27 = zext i8 %26 to i32
- %28 = getelementptr inbounds i8, i8* %2, i64 2
- %29 = load i8, i8* %28, align 1
+ %28 = getelementptr inbounds i8, ptr %2, i64 2
+ %29 = load i8, ptr %28, align 1
%30 = zext i8 %29 to i32
%31 = add nuw nsw i32 %30, %27
%32 = lshr i32 %31, 1
%33 = add nuw nsw i32 %32, %31
%34 = lshr i32 %33, 2
%35 = trunc i32 %34 to i16
- %36 = getelementptr inbounds i16, i16* %0, i64 2
- store i16 %35, i16* %36, align 2
- %37 = getelementptr inbounds i8, i8* %1, i64 3
- %38 = load i8, i8* %37, align 1
+ %36 = getelementptr inbounds i16, ptr %0, i64 2
+ store i16 %35, ptr %36, align 2
+ %37 = getelementptr inbounds i8, ptr %1, i64 3
+ %38 = load i8, ptr %37, align 1
%39 = zext i8 %38 to i32
- %40 = getelementptr inbounds i8, i8* %2, i64 3
- %41 = load i8, i8* %40, align 1
+ %40 = getelementptr inbounds i8, ptr %2, i64 3
+ %41 = load i8, ptr %40, align 1
%42 = zext i8 %41 to i32
%43 = add nuw nsw i32 %42, %39
%44 = lshr i32 %43, 1
%45 = add nuw nsw i32 %44, %43
%46 = lshr i32 %45, 2
%47 = trunc i32 %46 to i16
- %48 = getelementptr inbounds i16, i16* %0, i64 3
- store i16 %47, i16* %48, align 2
- %49 = getelementptr inbounds i8, i8* %1, i64 4
- %50 = load i8, i8* %49, align 1
+ %48 = getelementptr inbounds i16, ptr %0, i64 3
+ store i16 %47, ptr %48, align 2
+ %49 = getelementptr inbounds i8, ptr %1, i64 4
+ %50 = load i8, ptr %49, align 1
%51 = zext i8 %50 to i32
- %52 = getelementptr inbounds i8, i8* %2, i64 4
- %53 = load i8, i8* %52, align 1
+ %52 = getelementptr inbounds i8, ptr %2, i64 4
+ %53 = load i8, ptr %52, align 1
%54 = zext i8 %53 to i32
%55 = add nuw nsw i32 %54, %51
%56 = lshr i32 %55, 1
%57 = add nuw nsw i32 %56, %55
%58 = lshr i32 %57, 2
%59 = trunc i32 %58 to i16
- %60 = getelementptr inbounds i16, i16* %0, i64 4
- store i16 %59, i16* %60, align 2
- %61 = getelementptr inbounds i8, i8* %1, i64 5
- %62 = load i8, i8* %61, align 1
+ %60 = getelementptr inbounds i16, ptr %0, i64 4
+ store i16 %59, ptr %60, align 2
+ %61 = getelementptr inbounds i8, ptr %1, i64 5
+ %62 = load i8, ptr %61, align 1
%63 = zext i8 %62 to i32
- %64 = getelementptr inbounds i8, i8* %2, i64 5
- %65 = load i8, i8* %64, align 1
+ %64 = getelementptr inbounds i8, ptr %2, i64 5
+ %65 = load i8, ptr %64, align 1
%66 = zext i8 %65 to i32
%67 = add nuw nsw i32 %66, %63
%68 = lshr i32 %67, 1
%69 = add nuw nsw i32 %68, %67
%70 = lshr i32 %69, 2
%71 = trunc i32 %70 to i16
- %72 = getelementptr inbounds i16, i16* %0, i64 5
- store i16 %71, i16* %72, align 2
- %73 = getelementptr inbounds i8, i8* %1, i64 6
- %74 = load i8, i8* %73, align 1
+ %72 = getelementptr inbounds i16, ptr %0, i64 5
+ store i16 %71, ptr %72, align 2
+ %73 = getelementptr inbounds i8, ptr %1, i64 6
+ %74 = load i8, ptr %73, align 1
%75 = zext i8 %74 to i32
- %76 = getelementptr inbounds i8, i8* %2, i64 6
- %77 = load i8, i8* %76, align 1
+ %76 = getelementptr inbounds i8, ptr %2, i64 6
+ %77 = load i8, ptr %76, align 1
%78 = zext i8 %77 to i32
%79 = add nuw nsw i32 %78, %75
%80 = lshr i32 %79, 1
%81 = add nuw nsw i32 %80, %79
%82 = lshr i32 %81, 2
%83 = trunc i32 %82 to i16
- %84 = getelementptr inbounds i16, i16* %0, i64 6
- store i16 %83, i16* %84, align 2
- %85 = getelementptr inbounds i8, i8* %1, i64 7
- %86 = load i8, i8* %85, align 1
+ %84 = getelementptr inbounds i16, ptr %0, i64 6
+ store i16 %83, ptr %84, align 2
+ %85 = getelementptr inbounds i8, ptr %1, i64 7
+ %86 = load i8, ptr %85, align 1
%87 = zext i8 %86 to i32
- %88 = getelementptr inbounds i8, i8* %2, i64 7
- %89 = load i8, i8* %88, align 1
+ %88 = getelementptr inbounds i8, ptr %2, i64 7
+ %89 = load i8, ptr %88, align 1
%90 = zext i8 %89 to i32
%91 = add nuw nsw i32 %90, %87
%92 = lshr i32 %91, 1
%93 = add nuw nsw i32 %92, %91
%94 = lshr i32 %93, 2
%95 = trunc i32 %94 to i16
- %96 = getelementptr inbounds i16, i16* %0, i64 7
- store i16 %95, i16* %96, align 2
- %97 = getelementptr inbounds i8, i8* %1, i64 8
- %98 = load i8, i8* %97, align 1
+ %96 = getelementptr inbounds i16, ptr %0, i64 7
+ store i16 %95, ptr %96, align 2
+ %97 = getelementptr inbounds i8, ptr %1, i64 8
+ %98 = load i8, ptr %97, align 1
%99 = zext i8 %98 to i32
- %100 = getelementptr inbounds i8, i8* %2, i64 8
- %101 = load i8, i8* %100, align 1
+ %100 = getelementptr inbounds i8, ptr %2, i64 8
+ %101 = load i8, ptr %100, align 1
%102 = zext i8 %101 to i32
%103 = add nuw nsw i32 %102, %99
%104 = lshr i32 %103, 1
%105 = add nuw nsw i32 %104, %103
%106 = lshr i32 %105, 2
%107 = trunc i32 %106 to i16
- %108 = getelementptr inbounds i16, i16* %0, i64 8
- store i16 %107, i16* %108, align 2
- %109 = getelementptr inbounds i8, i8* %1, i64 9
- %110 = load i8, i8* %109, align 1
+ %108 = getelementptr inbounds i16, ptr %0, i64 8
+ store i16 %107, ptr %108, align 2
+ %109 = getelementptr inbounds i8, ptr %1, i64 9
+ %110 = load i8, ptr %109, align 1
%111 = zext i8 %110 to i32
- %112 = getelementptr inbounds i8, i8* %2, i64 9
- %113 = load i8, i8* %112, align 1
+ %112 = getelementptr inbounds i8, ptr %2, i64 9
+ %113 = load i8, ptr %112, align 1
%114 = zext i8 %113 to i32
%115 = add nuw nsw i32 %114, %111
%116 = lshr i32 %115, 1
%117 = add nuw nsw i32 %116, %115
%118 = lshr i32 %117, 2
%119 = trunc i32 %118 to i16
- %120 = getelementptr inbounds i16, i16* %0, i64 9
- store i16 %119, i16* %120, align 2
- %121 = getelementptr inbounds i8, i8* %1, i64 10
- %122 = load i8, i8* %121, align 1
+ %120 = getelementptr inbounds i16, ptr %0, i64 9
+ store i16 %119, ptr %120, align 2
+ %121 = getelementptr inbounds i8, ptr %1, i64 10
+ %122 = load i8, ptr %121, align 1
%123 = zext i8 %122 to i32
- %124 = getelementptr inbounds i8, i8* %2, i64 10
- %125 = load i8, i8* %124, align 1
+ %124 = getelementptr inbounds i8, ptr %2, i64 10
+ %125 = load i8, ptr %124, align 1
%126 = zext i8 %125 to i32
%127 = add nuw nsw i32 %126, %123
%128 = lshr i32 %127, 1
%129 = add nuw nsw i32 %128, %127
%130 = lshr i32 %129, 2
%131 = trunc i32 %130 to i16
- %132 = getelementptr inbounds i16, i16* %0, i64 10
- store i16 %131, i16* %132, align 2
- %133 = getelementptr inbounds i8, i8* %1, i64 11
- %134 = load i8, i8* %133, align 1
+ %132 = getelementptr inbounds i16, ptr %0, i64 10
+ store i16 %131, ptr %132, align 2
+ %133 = getelementptr inbounds i8, ptr %1, i64 11
+ %134 = load i8, ptr %133, align 1
%135 = zext i8 %134 to i32
- %136 = getelementptr inbounds i8, i8* %2, i64 11
- %137 = load i8, i8* %136, align 1
+ %136 = getelementptr inbounds i8, ptr %2, i64 11
+ %137 = load i8, ptr %136, align 1
%138 = zext i8 %137 to i32
%139 = add nuw nsw i32 %138, %135
%140 = lshr i32 %139, 1
%141 = add nuw nsw i32 %140, %139
%142 = lshr i32 %141, 2
%143 = trunc i32 %142 to i16
- %144 = getelementptr inbounds i16, i16* %0, i64 11
- store i16 %143, i16* %144, align 2
- %145 = getelementptr inbounds i8, i8* %1, i64 12
- %146 = load i8, i8* %145, align 1
+ %144 = getelementptr inbounds i16, ptr %0, i64 11
+ store i16 %143, ptr %144, align 2
+ %145 = getelementptr inbounds i8, ptr %1, i64 12
+ %146 = load i8, ptr %145, align 1
%147 = zext i8 %146 to i32
- %148 = getelementptr inbounds i8, i8* %2, i64 12
- %149 = load i8, i8* %148, align 1
+ %148 = getelementptr inbounds i8, ptr %2, i64 12
+ %149 = load i8, ptr %148, align 1
%150 = zext i8 %149 to i32
%151 = add nuw nsw i32 %150, %147
%152 = lshr i32 %151, 1
%153 = add nuw nsw i32 %152, %151
%154 = lshr i32 %153, 2
%155 = trunc i32 %154 to i16
- %156 = getelementptr inbounds i16, i16* %0, i64 12
- store i16 %155, i16* %156, align 2
- %157 = getelementptr inbounds i8, i8* %1, i64 13
- %158 = load i8, i8* %157, align 1
+ %156 = getelementptr inbounds i16, ptr %0, i64 12
+ store i16 %155, ptr %156, align 2
+ %157 = getelementptr inbounds i8, ptr %1, i64 13
+ %158 = load i8, ptr %157, align 1
%159 = zext i8 %158 to i32
- %160 = getelementptr inbounds i8, i8* %2, i64 13
- %161 = load i8, i8* %160, align 1
+ %160 = getelementptr inbounds i8, ptr %2, i64 13
+ %161 = load i8, ptr %160, align 1
%162 = zext i8 %161 to i32
%163 = add nuw nsw i32 %162, %159
%164 = lshr i32 %163, 1
%165 = add nuw nsw i32 %164, %163
%166 = lshr i32 %165, 2
%167 = trunc i32 %166 to i16
- %168 = getelementptr inbounds i16, i16* %0, i64 13
- store i16 %167, i16* %168, align 2
- %169 = getelementptr inbounds i8, i8* %1, i64 14
- %170 = load i8, i8* %169, align 1
+ %168 = getelementptr inbounds i16, ptr %0, i64 13
+ store i16 %167, ptr %168, align 2
+ %169 = getelementptr inbounds i8, ptr %1, i64 14
+ %170 = load i8, ptr %169, align 1
%171 = zext i8 %170 to i32
- %172 = getelementptr inbounds i8, i8* %2, i64 14
- %173 = load i8, i8* %172, align 1
+ %172 = getelementptr inbounds i8, ptr %2, i64 14
+ %173 = load i8, ptr %172, align 1
%174 = zext i8 %173 to i32
%175 = add nuw nsw i32 %174, %171
%176 = lshr i32 %175, 1
%177 = add nuw nsw i32 %176, %175
%178 = lshr i32 %177, 2
%179 = trunc i32 %178 to i16
- %180 = getelementptr inbounds i16, i16* %0, i64 14
- store i16 %179, i16* %180, align 2
- %181 = getelementptr inbounds i8, i8* %1, i64 15
- %182 = load i8, i8* %181, align 1
+ %180 = getelementptr inbounds i16, ptr %0, i64 14
+ store i16 %179, ptr %180, align 2
+ %181 = getelementptr inbounds i8, ptr %1, i64 15
+ %182 = load i8, ptr %181, align 1
%183 = zext i8 %182 to i32
- %184 = getelementptr inbounds i8, i8* %2, i64 15
- %185 = load i8, i8* %184, align 1
+ %184 = getelementptr inbounds i8, ptr %2, i64 15
+ %185 = load i8, ptr %184, align 1
%186 = zext i8 %185 to i32
%187 = add nuw nsw i32 %186, %183
%188 = lshr i32 %187, 1
%189 = add nuw nsw i32 %188, %187
%190 = lshr i32 %189, 2
%191 = trunc i32 %190 to i16
- %192 = getelementptr inbounds i16, i16* %0, i64 15
- store i16 %191, i16* %192, align 2
+ %192 = getelementptr inbounds i16, ptr %0, i64 15
+ store i16 %191, ptr %192, align 2
ret void
}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll b/llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll
index a31f462ce5128..f691f8dfae3b3 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll
@@ -8,18 +8,18 @@ target triple = "x86_64-unknown-linux-gnu"
; We should retain the TBAA on the load here, not lose it.
-define void @licm(double** align 8 dereferenceable(8) %_M_start.i, i64 %numElem) {
+define void @licm(ptr align 8 dereferenceable(8) %_M_start.i, i64 %numElem) {
; O1-LABEL: @licm(
; O1-NEXT: entry:
; O1-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0
; O1-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_LR_PH:%.*]]
; O1: for.body.lr.ph:
-; O1-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8, !tbaa [[TBAA3:![0-9]+]]
+; O1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[_M_START_I:%.*]], align 8, !tbaa [[TBAA3:![0-9]+]]
; O1-NEXT: br label [[FOR_BODY:%.*]]
; O1: for.body:
; O1-NEXT: [[K_02:%.*]] = phi i64 [ 0, [[FOR_BODY_LR_PH]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
-; O1-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[K_02]]
-; O1-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA8:![0-9]+]]
+; O1-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i64 [[K_02]]
+; O1-NEXT: store double 2.000000e+00, ptr [[ADD_PTR_I]], align 8, !tbaa [[TBAA8:![0-9]+]]
; O1-NEXT: [[INC]] = add nuw i64 [[K_02]], 1
; O1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[NUMELEM]]
; O1-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]]
@@ -31,7 +31,7 @@ define void @licm(double** align 8 dereferenceable(8) %_M_start.i, i64 %numElem)
; O23-NEXT: [[CMP1_NOT:%.*]] = icmp eq i64 [[NUMELEM:%.*]], 0
; O23-NEXT: br i1 [[CMP1_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_LR_PH:%.*]]
; O23: for.body.lr.ph:
-; O23-NEXT: [[TMP0:%.*]] = load double*, double** [[_M_START_I:%.*]], align 8, !tbaa [[TBAA3:![0-9]+]]
+; O23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[_M_START_I:%.*]], align 8, !tbaa [[TBAA3:![0-9]+]]
; O23-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[NUMELEM]], 4
; O23-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER:%.*]], label [[VECTOR_PH:%.*]]
; O23: vector.ph:
@@ -39,12 +39,10 @@ define void @licm(double** align 8 dereferenceable(8) %_M_start.i, i64 %numElem)
; O23-NEXT: br label [[VECTOR_BODY:%.*]]
; O23: vector.body:
; O23-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; O23-NEXT: [[TMP1:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[INDEX]]
-; O23-NEXT: [[TMP2:%.*]] = bitcast double* [[TMP1]] to <2 x double>*
-; O23-NEXT: store <2 x double> <double 2.000000e+00, double 2.000000e+00>, <2 x double>* [[TMP2]], align 8, !tbaa [[TBAA8:![0-9]+]]
-; O23-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, double* [[TMP1]], i64 2
-; O23-NEXT: [[TMP4:%.*]] = bitcast double* [[TMP3]] to <2 x double>*
-; O23-NEXT: store <2 x double> <double 2.000000e+00, double 2.000000e+00>, <2 x double>* [[TMP4]], align 8, !tbaa [[TBAA8]]
+; O23-NEXT: [[TMP1:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i64 [[INDEX]]
+; O23-NEXT: store <2 x double> <double 2.000000e+00, double 2.000000e+00>, ptr [[TMP1]], align 8, !tbaa [[TBAA8:![0-9]+]]
+; O23-NEXT: [[TMP3:%.*]] = getelementptr inbounds double, ptr [[TMP1]], i64 2
+; O23-NEXT: store <2 x double> <double 2.000000e+00, double 2.000000e+00>, ptr [[TMP3]], align 8, !tbaa [[TBAA8]]
; O23-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; O23-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; O23-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
@@ -56,8 +54,8 @@ define void @licm(double** align 8 dereferenceable(8) %_M_start.i, i64 %numElem)
; O23-NEXT: br label [[FOR_BODY:%.*]]
; O23: for.body:
; O23-NEXT: [[K_02:%.*]] = phi i64 [ [[INC:%.*]], [[FOR_BODY]] ], [ [[K_02_PH]], [[FOR_BODY_PREHEADER]] ]
-; O23-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, double* [[TMP0]], i64 [[K_02]]
-; O23-NEXT: store double 2.000000e+00, double* [[ADD_PTR_I]], align 8, !tbaa [[TBAA8]]
+; O23-NEXT: [[ADD_PTR_I:%.*]] = getelementptr inbounds double, ptr [[TMP0]], i64 [[K_02]]
+; O23-NEXT: store double 2.000000e+00, ptr [[ADD_PTR_I]], align 8, !tbaa [[TBAA8]]
; O23-NEXT: [[INC]] = add nuw i64 [[K_02]], 1
; O23-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[NUMELEM]]
; O23-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
@@ -73,9 +71,9 @@ for.cond: ; preds = %for.body, %entry
br i1 %cmp, label %for.body, label %for.cond.cleanup
for.body: ; preds = %for.cond
- %0 = load double*, double** %_M_start.i, align 8, !tbaa !3
- %add.ptr.i = getelementptr inbounds double, double* %0, i64 %k.0
- store double 2.000000e+00, double* %add.ptr.i, align 8, !tbaa !8
+ %0 = load ptr, ptr %_M_start.i, align 8, !tbaa !3
+ %add.ptr.i = getelementptr inbounds double, ptr %0, i64 %k.0
+ store double 2.000000e+00, ptr %add.ptr.i, align 8, !tbaa !8
%inc = add nuw i64 %k.0, 1
br label %for.cond
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll b/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll
index 61790d1317ddc..57951d7754269 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll
@@ -7,104 +7,102 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16
target triple = "x86_64-unknown-linux-gnu"
%class.FloatVecPair = type { %class.HomemadeVector, %class.HomemadeVector }
-%class.HomemadeVector = type <{ %class.HomemadeVector.0*, i32, [4 x i8] }>
-%class.HomemadeVector.0 = type <{ float*, i32, [4 x i8] }>
+%class.HomemadeVector = type <{ ptr, i32, [4 x i8] }>
+%class.HomemadeVector.0 = type <{ ptr, i32, [4 x i8] }>
$_ZN12FloatVecPair6vecIncEv = comdat any
-define dso_local void @_Z13vecIncFromPtrP12FloatVecPair(%class.FloatVecPair* %FVP) {
+define dso_local void @_Z13vecIncFromPtrP12FloatVecPair(ptr %FVP) {
; O1-LABEL: define {{[^@]+}}@_Z13vecIncFromPtrP12FloatVecPair
-; O1-SAME: (%class.FloatVecPair* nocapture readonly [[FVP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+; O1-SAME: (ptr nocapture readonly [[FVP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
; O1-NEXT: entry:
-; O1-NEXT: [[BASE_I_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], %class.FloatVecPair* [[FVP]], i64 0, i32 1, i32 0
-; O1-NEXT: [[TMP0:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I_I]], align 8, !tbaa [[TBAA0:![0-9]+]]
-; O1-NEXT: [[SIZE4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 1
-; O1-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIZE4_I]], align 8, !tbaa [[TBAA6:![0-9]+]]
-; O1-NEXT: [[CMP510_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0
-; O1-NEXT: br i1 [[CMP510_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]]
+; O1-NEXT: [[VSRC23_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], ptr [[FVP]], i64 0, i32 1
+; O1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VSRC23_I]], align 8, !tbaa [[TBAA0:![0-9]+]]
+; O1-NEXT: [[SIZE4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], ptr [[TMP0]], i64 undef, i32 1
+; O1-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIZE4_I]], align 8, !tbaa [[TBAA6:![0-9]+]]
+; O1-NEXT: [[CMP56_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0
+; O1-NEXT: br i1 [[CMP56_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]]
; O1: for.body7.lr.ph.i:
-; O1-NEXT: [[BASE_I4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 0
-; O1-NEXT: [[TMP2:%.*]] = load float*, float** [[BASE_I4_I]], align 8, !tbaa [[TBAA8:![0-9]+]]
-; O1-NEXT: [[ARRAYIDX_I5_I:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 undef
-; O1-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0
-; O1-NEXT: [[TMP3:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I6_I]], align 8, !tbaa [[TBAA0]]
-; O1-NEXT: [[BASE_I8_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP3]], i64 undef, i32 0
-; O1-NEXT: [[TMP4:%.*]] = load float*, float** [[BASE_I8_I]], align 8, !tbaa [[TBAA8]]
-; O1-NEXT: [[ARRAYIDX_I9_I:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 undef
+; O1-NEXT: [[ARRAYIDX_I_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], ptr [[TMP0]], i64 undef
+; O1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX_I_I]], align 8, !tbaa [[TBAA8:![0-9]+]]
+; O1-NEXT: [[ARRAYIDX_I3_I:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 undef
+; O1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[FVP]], align 8, !tbaa [[TBAA0]]
+; O1-NEXT: [[ARRAYIDX_I4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], ptr [[TMP3]], i64 undef
+; O1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYIDX_I4_I]], align 8, !tbaa [[TBAA8]]
+; O1-NEXT: [[ARRAYIDX_I5_I:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 undef
; O1-NEXT: br label [[FOR_BODY7_I:%.*]]
; O1: for.body7.i:
-; O1-NEXT: [[J_011_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [ [[INC_I:%.*]], [[FOR_BODY7_I]] ]
-; O1-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX_I5_I]], align 4, !tbaa [[TBAA9:![0-9]+]]
-; O1-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX_I9_I]], align 4, !tbaa [[TBAA9]]
+; O1-NEXT: [[J_07_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [ [[INC_I:%.*]], [[FOR_BODY7_I]] ]
+; O1-NEXT: [[TMP5:%.*]] = load float, ptr [[ARRAYIDX_I3_I]], align 4, !tbaa [[TBAA9:![0-9]+]]
+; O1-NEXT: [[TMP6:%.*]] = load float, ptr [[ARRAYIDX_I5_I]], align 4, !tbaa [[TBAA9]]
; O1-NEXT: [[ADD_I:%.*]] = fadd float [[TMP5]], [[TMP6]]
-; O1-NEXT: store float [[ADD_I]], float* [[ARRAYIDX_I9_I]], align 4, !tbaa [[TBAA9]]
-; O1-NEXT: [[INC_I]] = add nuw i32 [[J_011_I]], 1
+; O1-NEXT: store float [[ADD_I]], ptr [[ARRAYIDX_I5_I]], align 4, !tbaa [[TBAA9]]
+; O1-NEXT: [[INC_I]] = add nuw i32 [[J_07_I]], 1
; O1-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]]
; O1-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label [[FOR_BODY7_I]], !llvm.loop [[LOOP11:![0-9]+]]
; O1: _ZN12FloatVecPair6vecIncEv.exit:
; O1-NEXT: ret void
;
; O23-LABEL: define {{[^@]+}}@_Z13vecIncFromPtrP12FloatVecPair
-; O23-SAME: (%class.FloatVecPair* nocapture readonly [[FVP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+; O23-SAME: (ptr nocapture readonly [[FVP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
; O23-NEXT: entry:
-; O23-NEXT: [[BASE_I_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], %class.FloatVecPair* [[FVP]], i64 0, i32 1, i32 0
-; O23-NEXT: [[TMP0:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I_I]], align 8, !tbaa [[TBAA0:![0-9]+]]
-; O23-NEXT: [[SIZE4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 1
-; O23-NEXT: [[TMP1:%.*]] = load i32, i32* [[SIZE4_I]], align 8, !tbaa [[TBAA6:![0-9]+]]
-; O23-NEXT: [[CMP510_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0
-; O23-NEXT: br i1 [[CMP510_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]]
+; O23-NEXT: [[VSRC23_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], ptr [[FVP]], i64 0, i32 1
+; O23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VSRC23_I]], align 8, !tbaa [[TBAA0:![0-9]+]]
+; O23-NEXT: [[SIZE4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], ptr [[TMP0]], i64 undef, i32 1
+; O23-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIZE4_I]], align 8, !tbaa [[TBAA6:![0-9]+]]
+; O23-NEXT: [[CMP56_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0
+; O23-NEXT: br i1 [[CMP56_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]]
; O23: for.body7.lr.ph.i:
-; O23-NEXT: [[BASE_I4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP0]], i64 undef, i32 0
-; O23-NEXT: [[TMP2:%.*]] = load float*, float** [[BASE_I4_I]], align 8, !tbaa [[TBAA8:![0-9]+]]
-; O23-NEXT: [[ARRAYIDX_I5_I:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 undef
-; O23-NEXT: [[BASE_I6_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR]], %class.FloatVecPair* [[FVP]], i64 0, i32 0, i32 0
-; O23-NEXT: [[TMP3:%.*]] = load %class.HomemadeVector.0*, %class.HomemadeVector.0** [[BASE_I6_I]], align 8, !tbaa [[TBAA0]]
-; O23-NEXT: [[BASE_I8_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], %class.HomemadeVector.0* [[TMP3]], i64 undef, i32 0
-; O23-NEXT: [[TMP4:%.*]] = load float*, float** [[BASE_I8_I]], align 8, !tbaa [[TBAA8]]
-; O23-NEXT: [[ARRAYIDX_I9_I:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 undef
-; O23-NEXT: [[DOTPRE_I:%.*]] = load float, float* [[ARRAYIDX_I9_I]], align 4, !tbaa [[TBAA9:![0-9]+]]
+; O23-NEXT: [[ARRAYIDX_I_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], ptr [[TMP0]], i64 undef
+; O23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX_I_I]], align 8, !tbaa [[TBAA8:![0-9]+]]
+; O23-NEXT: [[ARRAYIDX_I3_I:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 undef
+; O23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[FVP]], align 8, !tbaa [[TBAA0]]
+; O23-NEXT: [[ARRAYIDX_I4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], ptr [[TMP3]], i64 undef
+; O23-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYIDX_I4_I]], align 8, !tbaa [[TBAA8]]
+; O23-NEXT: [[ARRAYIDX_I5_I:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 undef
+; O23-NEXT: [[DOTPRE_I:%.*]] = load float, ptr [[ARRAYIDX_I5_I]], align 4, !tbaa [[TBAA9:![0-9]+]]
; O23-NEXT: br label [[FOR_BODY7_I:%.*]]
; O23: for.body7.i:
; O23-NEXT: [[TMP5:%.*]] = phi float [ [[DOTPRE_I]], [[FOR_BODY7_LR_PH_I]] ], [ [[ADD_I:%.*]], [[FOR_BODY7_I]] ]
-; O23-NEXT: [[J_011_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [ [[INC_I:%.*]], [[FOR_BODY7_I]] ]
-; O23-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX_I5_I]], align 4, !tbaa [[TBAA9]]
+; O23-NEXT: [[J_07_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [ [[INC_I:%.*]], [[FOR_BODY7_I]] ]
+; O23-NEXT: [[TMP6:%.*]] = load float, ptr [[ARRAYIDX_I3_I]], align 4, !tbaa [[TBAA9]]
; O23-NEXT: [[ADD_I]] = fadd float [[TMP5]], [[TMP6]]
-; O23-NEXT: store float [[ADD_I]], float* [[ARRAYIDX_I9_I]], align 4, !tbaa [[TBAA9]]
-; O23-NEXT: [[INC_I]] = add nuw i32 [[J_011_I]], 1
+; O23-NEXT: store float [[ADD_I]], ptr [[ARRAYIDX_I5_I]], align 4, !tbaa [[TBAA9]]
+; O23-NEXT: [[INC_I]] = add nuw i32 [[J_07_I]], 1
; O23-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]]
; O23-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label [[FOR_BODY7_I]], !llvm.loop [[LOOP11:![0-9]+]]
; O23: _ZN12FloatVecPair6vecIncEv.exit:
; O23-NEXT: ret void
;
entry:
- %FVP.addr = alloca %class.FloatVecPair*, align 8
- store %class.FloatVecPair* %FVP, %class.FloatVecPair** %FVP.addr, align 8, !tbaa !0
- %0 = load %class.FloatVecPair*, %class.FloatVecPair** %FVP.addr, align 8, !tbaa !0
- call void @_ZN12FloatVecPair6vecIncEv(%class.FloatVecPair* %0)
+ %FVP.addr = alloca ptr, align 8
+ store ptr %FVP, ptr %FVP.addr, align 8, !tbaa !0
+ %0 = load ptr, ptr %FVP.addr, align 8, !tbaa !0
+ call void @_ZN12FloatVecPair6vecIncEv(ptr %0)
ret void
}
-define linkonce_odr dso_local void @_ZN12FloatVecPair6vecIncEv(%class.FloatVecPair* %this) comdat align 2 {
+define linkonce_odr dso_local void @_ZN12FloatVecPair6vecIncEv(ptr %this) comdat align 2 {
entry:
- %this.addr = alloca %class.FloatVecPair*, align 8
+ %this.addr = alloca ptr, align 8
%j = alloca i32, align 4
- store %class.FloatVecPair* %this, %class.FloatVecPair** %this.addr, align 8, !tbaa !0
- %this1 = load %class.FloatVecPair*, %class.FloatVecPair** %this.addr, align 8
+ store ptr %this, ptr %this.addr, align 8, !tbaa !0
+ %this1 = load ptr, ptr %this.addr, align 8
br label %for.cond
for.cond: ; preds = %entry
br label %for.body
for.body: ; preds = %for.cond
- store i32 0, i32* %j, align 4, !tbaa !4
+ store i32 0, ptr %j, align 4, !tbaa !4
br label %for.cond2
for.cond2: ; preds = %for.inc, %for.body
- %0 = load i32, i32* %j, align 4, !tbaa !4
- %Vsrc23 = getelementptr inbounds %class.FloatVecPair, %class.FloatVecPair* %this1, i32 0, i32 1
- %call = call %class.HomemadeVector.0* @_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj(%class.HomemadeVector* %Vsrc23)
- %size4 = getelementptr inbounds %class.HomemadeVector.0, %class.HomemadeVector.0* %call, i32 0, i32 1
- %1 = load i32, i32* %size4, align 8, !tbaa !6
+ %0 = load i32, ptr %j, align 4, !tbaa !4
+ %Vsrc23 = getelementptr inbounds %class.FloatVecPair, ptr %this1, i32 0, i32 1
+ %call = call ptr @_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj(ptr %Vsrc23)
+ %size4 = getelementptr inbounds %class.HomemadeVector.0, ptr %call, i32 0, i32 1
+ %1 = load i32, ptr %size4, align 8, !tbaa !6
%cmp5 = icmp ult i32 %0, %1
br i1 %cmp5, label %for.body7, label %for.cond.cleanup6
@@ -112,49 +110,42 @@ for.cond.cleanup6: ; preds = %for.cond2
ret void
for.body7: ; preds = %for.cond2
- %Vsrc28 = getelementptr inbounds %class.FloatVecPair, %class.FloatVecPair* %this1, i32 0, i32 1
- %call9 = call %class.HomemadeVector.0* @_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj(%class.HomemadeVector* %Vsrc28)
- %call10 = call float* @_ZN14HomemadeVectorIfLj8EEixEj(%class.HomemadeVector.0* %call9)
- %2 = load float, float* %call10, align 4, !tbaa !8
- %Vsrcdst = getelementptr inbounds %class.FloatVecPair, %class.FloatVecPair* %this1, i32 0, i32 0
- %call11 = call %class.HomemadeVector.0* @_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj(%class.HomemadeVector* %Vsrcdst)
- %call12 = call float* @_ZN14HomemadeVectorIfLj8EEixEj(%class.HomemadeVector.0* %call11)
- %3 = load float, float* %call12, align 4, !tbaa !8
+ %Vsrc28 = getelementptr inbounds %class.FloatVecPair, ptr %this1, i32 0, i32 1
+ %call9 = call ptr @_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj(ptr %Vsrc28)
+ %call10 = call ptr @_ZN14HomemadeVectorIfLj8EEixEj(ptr %call9)
+ %2 = load float, ptr %call10, align 4, !tbaa !8
+ %call11 = call ptr @_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj(ptr %this1)
+ %call12 = call ptr @_ZN14HomemadeVectorIfLj8EEixEj(ptr %call11)
+ %3 = load float, ptr %call12, align 4, !tbaa !8
%add = fadd float %3, %2
- store float %add, float* %call12, align 4, !tbaa !8
+ store float %add, ptr %call12, align 4, !tbaa !8
br label %for.inc
for.inc: ; preds = %for.body7
- %4 = load i32, i32* %j, align 4, !tbaa !4
+ %4 = load i32, ptr %j, align 4, !tbaa !4
%inc = add i32 %4, 1
- store i32 %inc, i32* %j, align 4, !tbaa !4
+ store i32 %inc, ptr %j, align 4, !tbaa !4
br label %for.cond2, !llvm.loop !10
}
-define linkonce_odr dso_local %class.HomemadeVector.0* @_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj(%class.HomemadeVector* %this) align 2 {
+define linkonce_odr dso_local ptr @_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj(ptr %this) align 2 {
entry:
- %this.addr = alloca %class.HomemadeVector*, align 8
- store %class.HomemadeVector* %this, %class.HomemadeVector** %this.addr, align 8, !tbaa !0
- %this1 = load %class.HomemadeVector*, %class.HomemadeVector** %this.addr, align 8
- %base = getelementptr inbounds %class.HomemadeVector, %class.HomemadeVector* %this1, i32 0, i32 0
- %0 = load %class.HomemadeVector.0*, %class.HomemadeVector.0** %base, align 8, !tbaa !12
- %1 = bitcast %class.HomemadeVector.0* %0 to i8*
- %2 = bitcast i8* %1 to %class.HomemadeVector.0*
- %arrayidx = getelementptr inbounds %class.HomemadeVector.0, %class.HomemadeVector.0* %2, i64 undef
- ret %class.HomemadeVector.0* %arrayidx
+ %this.addr = alloca ptr, align 8
+ store ptr %this, ptr %this.addr, align 8, !tbaa !0
+ %this1 = load ptr, ptr %this.addr, align 8
+ %0 = load ptr, ptr %this1, align 8, !tbaa !12
+ %arrayidx = getelementptr inbounds %class.HomemadeVector.0, ptr %0, i64 undef
+ ret ptr %arrayidx
}
-define linkonce_odr dso_local float* @_ZN14HomemadeVectorIfLj8EEixEj(%class.HomemadeVector.0* %this) align 2 {
+define linkonce_odr dso_local ptr @_ZN14HomemadeVectorIfLj8EEixEj(ptr %this) align 2 {
entry:
- %this.addr = alloca %class.HomemadeVector.0*, align 8
- store %class.HomemadeVector.0* %this, %class.HomemadeVector.0** %this.addr, align 8, !tbaa !0
- %this1 = load %class.HomemadeVector.0*, %class.HomemadeVector.0** %this.addr, align 8
- %base = getelementptr inbounds %class.HomemadeVector.0, %class.HomemadeVector.0* %this1, i32 0, i32 0
- %0 = load float*, float** %base, align 8, !tbaa !14
- %1 = bitcast float* %0 to i8*
- %2 = bitcast i8* %1 to float*
- %arrayidx = getelementptr inbounds float, float* %2, i64 undef
- ret float* %arrayidx
+ %this.addr = alloca ptr, align 8
+ store ptr %this, ptr %this.addr, align 8, !tbaa !0
+ %this1 = load ptr, ptr %this.addr, align 8
+ %0 = load ptr, ptr %this1, align 8, !tbaa !14
+ %arrayidx = getelementptr inbounds float, ptr %0, i64 undef
+ ret ptr %arrayidx
}
!0 = !{!1, !1, i64 0}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/store-constant-merge.ll b/llvm/test/Transforms/PhaseOrdering/X86/store-constant-merge.ll
index ce9f9103bb681..04956776f257d 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/store-constant-merge.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/store-constant-merge.ll
@@ -20,34 +20,31 @@ define void @bad1() {
;
bb:
%i = alloca %struct.data_t, align 1
- %i1 = getelementptr inbounds %struct.data_t, %struct.data_t* %i, i32 0, i32 0
- %i2 = getelementptr inbounds [16 x i8], [16 x i8]* %i1, i64 0, i64 0
- store i8 1, i8* %i2, align 1
- %i3 = getelementptr inbounds i8, i8* %i2, i64 1
- store i8 2, i8* %i3, align 1
- %i4 = getelementptr inbounds i8, i8* %i3, i64 1
- store i8 3, i8* %i4, align 1
- %i5 = getelementptr inbounds i8, i8* %i4, i64 1
- store i8 4, i8* %i5, align 1
- %i6 = getelementptr inbounds i8, i8* %i5, i64 1
- store i8 5, i8* %i6, align 1
- %i7 = getelementptr inbounds i8, i8* %i6, i64 1
- %i8 = getelementptr inbounds i8, i8* %i2, i64 16
+ store i8 1, ptr %i, align 1
+ %i3 = getelementptr inbounds i8, ptr %i, i64 1
+ store i8 2, ptr %i3, align 1
+ %i4 = getelementptr inbounds i8, ptr %i3, i64 1
+ store i8 3, ptr %i4, align 1
+ %i5 = getelementptr inbounds i8, ptr %i4, i64 1
+ store i8 4, ptr %i5, align 1
+ %i6 = getelementptr inbounds i8, ptr %i5, i64 1
+ store i8 5, ptr %i6, align 1
+ %i7 = getelementptr inbounds i8, ptr %i6, i64 1
+ %i8 = getelementptr inbounds i8, ptr %i, i64 16
br label %bb9
bb9: ; preds = %bb9, %bb
- %i10 = phi i8* [ %i7, %bb ], [ %i11, %bb9 ]
- store i8 0, i8* %i10, align 1
- %i11 = getelementptr inbounds i8, i8* %i10, i64 1
- %i12 = icmp eq i8* %i11, %i8
+ %i10 = phi ptr [ %i7, %bb ], [ %i11, %bb9 ]
+ store i8 0, ptr %i10, align 1
+ %i11 = getelementptr inbounds i8, ptr %i10, i64 1
+ %i12 = icmp eq ptr %i11, %i8
br i1 %i12, label %bb13, label %bb9
bb13: ; preds = %bb9
- %i14 = bitcast %struct.data_t* %i to { i64, i64 }*
- %i15 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %i14, i32 0, i32 0
- %i16 = load i64, i64* %i15, align 1
- %i17 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %i14, i32 0, i32 1
- %i18 = load i64, i64* %i17, align 1
+ %i15 = getelementptr inbounds { i64, i64 }, ptr %i, i32 0, i32 0
+ %i16 = load i64, ptr %i15, align 1
+ %i17 = getelementptr inbounds { i64, i64 }, ptr %i, i32 0, i32 1
+ %i18 = load i64, ptr %i17, align 1
call void @process6data_t(i64 %i16, i64 %i18)
ret void
}
@@ -60,54 +57,51 @@ define void @bad2() {
;
bb:
%i = alloca %struct.data_t, align 1
- %i1 = getelementptr inbounds %struct.data_t, %struct.data_t* %i, i32 0, i32 0
- %i2 = getelementptr inbounds [16 x i8], [16 x i8]* %i1, i64 0, i64 0
- store i8 1, i8* %i2, align 1
- %i3 = getelementptr inbounds i8, i8* %i2, i64 1
- store i8 2, i8* %i3, align 1
- %i4 = getelementptr inbounds i8, i8* %i3, i64 1
- store i8 3, i8* %i4, align 1
- %i5 = getelementptr inbounds i8, i8* %i4, i64 1
- store i8 4, i8* %i5, align 1
- %i6 = getelementptr inbounds i8, i8* %i5, i64 1
- store i8 5, i8* %i6, align 1
- %i7 = getelementptr inbounds i8, i8* %i6, i64 1
- store i8 1, i8* %i7, align 1
- %i8 = getelementptr inbounds i8, i8* %i7, i64 1
- store i8 2, i8* %i8, align 1
- %i9 = getelementptr inbounds i8, i8* %i8, i64 1
- store i8 3, i8* %i9, align 1
- %i10 = getelementptr inbounds i8, i8* %i9, i64 1
- store i8 4, i8* %i10, align 1
- %i11 = getelementptr inbounds i8, i8* %i10, i64 1
- store i8 5, i8* %i11, align 1
- %i12 = getelementptr inbounds i8, i8* %i11, i64 1
- store i8 1, i8* %i12, align 1
- %i13 = getelementptr inbounds i8, i8* %i12, i64 1
- store i8 2, i8* %i13, align 1
- %i14 = getelementptr inbounds i8, i8* %i13, i64 1
- store i8 3, i8* %i14, align 1
- %i15 = getelementptr inbounds i8, i8* %i14, i64 1
- store i8 4, i8* %i15, align 1
- %i16 = getelementptr inbounds i8, i8* %i15, i64 1
- store i8 5, i8* %i16, align 1
- %i17 = getelementptr inbounds i8, i8* %i16, i64 1
- %i18 = getelementptr inbounds i8, i8* %i2, i64 16
+ store i8 1, ptr %i, align 1
+ %i3 = getelementptr inbounds i8, ptr %i, i64 1
+ store i8 2, ptr %i3, align 1
+ %i4 = getelementptr inbounds i8, ptr %i3, i64 1
+ store i8 3, ptr %i4, align 1
+ %i5 = getelementptr inbounds i8, ptr %i4, i64 1
+ store i8 4, ptr %i5, align 1
+ %i6 = getelementptr inbounds i8, ptr %i5, i64 1
+ store i8 5, ptr %i6, align 1
+ %i7 = getelementptr inbounds i8, ptr %i6, i64 1
+ store i8 1, ptr %i7, align 1
+ %i8 = getelementptr inbounds i8, ptr %i7, i64 1
+ store i8 2, ptr %i8, align 1
+ %i9 = getelementptr inbounds i8, ptr %i8, i64 1
+ store i8 3, ptr %i9, align 1
+ %i10 = getelementptr inbounds i8, ptr %i9, i64 1
+ store i8 4, ptr %i10, align 1
+ %i11 = getelementptr inbounds i8, ptr %i10, i64 1
+ store i8 5, ptr %i11, align 1
+ %i12 = getelementptr inbounds i8, ptr %i11, i64 1
+ store i8 1, ptr %i12, align 1
+ %i13 = getelementptr inbounds i8, ptr %i12, i64 1
+ store i8 2, ptr %i13, align 1
+ %i14 = getelementptr inbounds i8, ptr %i13, i64 1
+ store i8 3, ptr %i14, align 1
+ %i15 = getelementptr inbounds i8, ptr %i14, i64 1
+ store i8 4, ptr %i15, align 1
+ %i16 = getelementptr inbounds i8, ptr %i15, i64 1
+ store i8 5, ptr %i16, align 1
+ %i17 = getelementptr inbounds i8, ptr %i16, i64 1
+ %i18 = getelementptr inbounds i8, ptr %i, i64 16
br label %bb19
bb19: ; preds = %bb19, %bb
- %i20 = phi i8* [ %i17, %bb ], [ %i21, %bb19 ]
- store i8 0, i8* %i20, align 1
- %i21 = getelementptr inbounds i8, i8* %i20, i64 1
- %i22 = icmp eq i8* %i21, %i18
+ %i20 = phi ptr [ %i17, %bb ], [ %i21, %bb19 ]
+ store i8 0, ptr %i20, align 1
+ %i21 = getelementptr inbounds i8, ptr %i20, i64 1
+ %i22 = icmp eq ptr %i21, %i18
br i1 %i22, label %bb23, label %bb19
bb23: ; preds = %bb19
- %i24 = bitcast %struct.data_t* %i to { i64, i64 }*
- %i25 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %i24, i32 0, i32 0
- %i26 = load i64, i64* %i25, align 1
- %i27 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %i24, i32 0, i32 1
- %i28 = load i64, i64* %i27, align 1
+ %i25 = getelementptr inbounds { i64, i64 }, ptr %i, i32 0, i32 0
+ %i26 = load i64, ptr %i25, align 1
+ %i27 = getelementptr inbounds { i64, i64 }, ptr %i, i32 0, i32 1
+ %i28 = load i64, ptr %i27, align 1
call void @process6data_t(i64 %i26, i64 %i28)
ret void
}
@@ -122,130 +116,121 @@ bb:
%i = alloca %struct.data_t, align 1
%i1 = alloca %struct.data_t, align 1
%i2 = alloca %struct.data_t, align 1
- %i3 = getelementptr inbounds %struct.data_t, %struct.data_t* %i, i32 0, i32 0
- %i4 = getelementptr inbounds [16 x i8], [16 x i8]* %i3, i64 0, i64 0
- store i8 1, i8* %i4, align 1
- %i5 = getelementptr inbounds i8, i8* %i4, i64 1
- store i8 2, i8* %i5, align 1
- %i6 = getelementptr inbounds i8, i8* %i5, i64 1
- store i8 3, i8* %i6, align 1
- %i7 = getelementptr inbounds i8, i8* %i6, i64 1
- store i8 4, i8* %i7, align 1
- %i8 = getelementptr inbounds i8, i8* %i7, i64 1
- store i8 5, i8* %i8, align 1
- %i9 = getelementptr inbounds i8, i8* %i8, i64 1
- store i8 0, i8* %i9, align 1
- %i10 = getelementptr inbounds i8, i8* %i9, i64 1
- store i8 0, i8* %i10, align 1
- %i11 = getelementptr inbounds i8, i8* %i10, i64 1
- store i8 0, i8* %i11, align 1
- %i12 = getelementptr inbounds i8, i8* %i11, i64 1
- store i8 0, i8* %i12, align 1
- %i13 = getelementptr inbounds i8, i8* %i12, i64 1
- store i8 0, i8* %i13, align 1
- %i14 = getelementptr inbounds i8, i8* %i13, i64 1
- store i8 0, i8* %i14, align 1
- %i15 = getelementptr inbounds i8, i8* %i14, i64 1
- store i8 0, i8* %i15, align 1
- %i16 = getelementptr inbounds i8, i8* %i15, i64 1
- store i8 0, i8* %i16, align 1
- %i17 = getelementptr inbounds i8, i8* %i16, i64 1
- store i8 0, i8* %i17, align 1
- %i18 = getelementptr inbounds i8, i8* %i17, i64 1
- store i8 0, i8* %i18, align 1
- %i19 = getelementptr inbounds i8, i8* %i18, i64 1
- store i8 0, i8* %i19, align 1
- %i20 = getelementptr inbounds %struct.data_t, %struct.data_t* %i1, i32 0, i32 0
- %i21 = getelementptr inbounds [16 x i8], [16 x i8]* %i20, i64 0, i64 0
- store i8 11, i8* %i21, align 1
- %i22 = getelementptr inbounds i8, i8* %i21, i64 1
- store i8 12, i8* %i22, align 1
- %i23 = getelementptr inbounds i8, i8* %i22, i64 1
- store i8 13, i8* %i23, align 1
- %i24 = getelementptr inbounds i8, i8* %i23, i64 1
- store i8 14, i8* %i24, align 1
- %i25 = getelementptr inbounds i8, i8* %i24, i64 1
- store i8 15, i8* %i25, align 1
- %i26 = getelementptr inbounds i8, i8* %i25, i64 1
- store i8 10, i8* %i26, align 1
- %i27 = getelementptr inbounds i8, i8* %i26, i64 1
- store i8 10, i8* %i27, align 1
- %i28 = getelementptr inbounds i8, i8* %i27, i64 1
- store i8 10, i8* %i28, align 1
- %i29 = getelementptr inbounds i8, i8* %i28, i64 1
- store i8 10, i8* %i29, align 1
- %i30 = getelementptr inbounds i8, i8* %i29, i64 1
- store i8 10, i8* %i30, align 1
- %i31 = getelementptr inbounds i8, i8* %i30, i64 1
- store i8 10, i8* %i31, align 1
- %i32 = getelementptr inbounds i8, i8* %i31, i64 1
- store i8 10, i8* %i32, align 1
- %i33 = getelementptr inbounds i8, i8* %i32, i64 1
- store i8 10, i8* %i33, align 1
- %i34 = getelementptr inbounds i8, i8* %i33, i64 1
- store i8 10, i8* %i34, align 1
- %i35 = getelementptr inbounds i8, i8* %i34, i64 1
- store i8 10, i8* %i35, align 1
- %i36 = getelementptr inbounds i8, i8* %i35, i64 1
- store i8 10, i8* %i36, align 1
- %i37 = getelementptr inbounds %struct.data_t, %struct.data_t* %i2, i32 0, i32 0
- %i38 = getelementptr inbounds [16 x i8], [16 x i8]* %i37, i64 0, i64 0
- store i8 21, i8* %i38, align 1
- %i39 = getelementptr inbounds i8, i8* %i38, i64 1
- store i8 22, i8* %i39, align 1
- %i40 = getelementptr inbounds i8, i8* %i39, i64 1
- store i8 23, i8* %i40, align 1
- %i41 = getelementptr inbounds i8, i8* %i40, i64 1
- store i8 24, i8* %i41, align 1
- %i42 = getelementptr inbounds i8, i8* %i41, i64 1
- store i8 25, i8* %i42, align 1
- %i43 = getelementptr inbounds i8, i8* %i42, i64 1
- store i8 20, i8* %i43, align 1
- %i44 = getelementptr inbounds i8, i8* %i43, i64 1
- store i8 20, i8* %i44, align 1
- %i45 = getelementptr inbounds i8, i8* %i44, i64 1
- store i8 20, i8* %i45, align 1
- %i46 = getelementptr inbounds i8, i8* %i45, i64 1
- store i8 10, i8* %i46, align 1
- %i47 = getelementptr inbounds i8, i8* %i46, i64 1
- store i8 20, i8* %i47, align 1
- %i48 = getelementptr inbounds i8, i8* %i47, i64 1
- store i8 20, i8* %i48, align 1
- %i49 = getelementptr inbounds i8, i8* %i48, i64 1
- store i8 20, i8* %i49, align 1
- %i50 = getelementptr inbounds i8, i8* %i49, i64 1
- store i8 20, i8* %i50, align 1
- %i51 = getelementptr inbounds i8, i8* %i50, i64 1
- store i8 20, i8* %i51, align 1
- %i52 = getelementptr inbounds i8, i8* %i51, i64 1
- store i8 20, i8* %i52, align 1
- %i53 = getelementptr inbounds i8, i8* %i52, i64 1
- %i54 = getelementptr inbounds i8, i8* %i38, i64 16
+ store i8 1, ptr %i, align 1
+ %i5 = getelementptr inbounds i8, ptr %i, i64 1
+ store i8 2, ptr %i5, align 1
+ %i6 = getelementptr inbounds i8, ptr %i5, i64 1
+ store i8 3, ptr %i6, align 1
+ %i7 = getelementptr inbounds i8, ptr %i6, i64 1
+ store i8 4, ptr %i7, align 1
+ %i8 = getelementptr inbounds i8, ptr %i7, i64 1
+ store i8 5, ptr %i8, align 1
+ %i9 = getelementptr inbounds i8, ptr %i8, i64 1
+ store i8 0, ptr %i9, align 1
+ %i10 = getelementptr inbounds i8, ptr %i9, i64 1
+ store i8 0, ptr %i10, align 1
+ %i11 = getelementptr inbounds i8, ptr %i10, i64 1
+ store i8 0, ptr %i11, align 1
+ %i12 = getelementptr inbounds i8, ptr %i11, i64 1
+ store i8 0, ptr %i12, align 1
+ %i13 = getelementptr inbounds i8, ptr %i12, i64 1
+ store i8 0, ptr %i13, align 1
+ %i14 = getelementptr inbounds i8, ptr %i13, i64 1
+ store i8 0, ptr %i14, align 1
+ %i15 = getelementptr inbounds i8, ptr %i14, i64 1
+ store i8 0, ptr %i15, align 1
+ %i16 = getelementptr inbounds i8, ptr %i15, i64 1
+ store i8 0, ptr %i16, align 1
+ %i17 = getelementptr inbounds i8, ptr %i16, i64 1
+ store i8 0, ptr %i17, align 1
+ %i18 = getelementptr inbounds i8, ptr %i17, i64 1
+ store i8 0, ptr %i18, align 1
+ %i19 = getelementptr inbounds i8, ptr %i18, i64 1
+ store i8 0, ptr %i19, align 1
+ store i8 11, ptr %i1, align 1
+ %i22 = getelementptr inbounds i8, ptr %i1, i64 1
+ store i8 12, ptr %i22, align 1
+ %i23 = getelementptr inbounds i8, ptr %i22, i64 1
+ store i8 13, ptr %i23, align 1
+ %i24 = getelementptr inbounds i8, ptr %i23, i64 1
+ store i8 14, ptr %i24, align 1
+ %i25 = getelementptr inbounds i8, ptr %i24, i64 1
+ store i8 15, ptr %i25, align 1
+ %i26 = getelementptr inbounds i8, ptr %i25, i64 1
+ store i8 10, ptr %i26, align 1
+ %i27 = getelementptr inbounds i8, ptr %i26, i64 1
+ store i8 10, ptr %i27, align 1
+ %i28 = getelementptr inbounds i8, ptr %i27, i64 1
+ store i8 10, ptr %i28, align 1
+ %i29 = getelementptr inbounds i8, ptr %i28, i64 1
+ store i8 10, ptr %i29, align 1
+ %i30 = getelementptr inbounds i8, ptr %i29, i64 1
+ store i8 10, ptr %i30, align 1
+ %i31 = getelementptr inbounds i8, ptr %i30, i64 1
+ store i8 10, ptr %i31, align 1
+ %i32 = getelementptr inbounds i8, ptr %i31, i64 1
+ store i8 10, ptr %i32, align 1
+ %i33 = getelementptr inbounds i8, ptr %i32, i64 1
+ store i8 10, ptr %i33, align 1
+ %i34 = getelementptr inbounds i8, ptr %i33, i64 1
+ store i8 10, ptr %i34, align 1
+ %i35 = getelementptr inbounds i8, ptr %i34, i64 1
+ store i8 10, ptr %i35, align 1
+ %i36 = getelementptr inbounds i8, ptr %i35, i64 1
+ store i8 10, ptr %i36, align 1
+ store i8 21, ptr %i2, align 1
+ %i39 = getelementptr inbounds i8, ptr %i2, i64 1
+ store i8 22, ptr %i39, align 1
+ %i40 = getelementptr inbounds i8, ptr %i39, i64 1
+ store i8 23, ptr %i40, align 1
+ %i41 = getelementptr inbounds i8, ptr %i40, i64 1
+ store i8 24, ptr %i41, align 1
+ %i42 = getelementptr inbounds i8, ptr %i41, i64 1
+ store i8 25, ptr %i42, align 1
+ %i43 = getelementptr inbounds i8, ptr %i42, i64 1
+ store i8 20, ptr %i43, align 1
+ %i44 = getelementptr inbounds i8, ptr %i43, i64 1
+ store i8 20, ptr %i44, align 1
+ %i45 = getelementptr inbounds i8, ptr %i44, i64 1
+ store i8 20, ptr %i45, align 1
+ %i46 = getelementptr inbounds i8, ptr %i45, i64 1
+ store i8 10, ptr %i46, align 1
+ %i47 = getelementptr inbounds i8, ptr %i46, i64 1
+ store i8 20, ptr %i47, align 1
+ %i48 = getelementptr inbounds i8, ptr %i47, i64 1
+ store i8 20, ptr %i48, align 1
+ %i49 = getelementptr inbounds i8, ptr %i48, i64 1
+ store i8 20, ptr %i49, align 1
+ %i50 = getelementptr inbounds i8, ptr %i49, i64 1
+ store i8 20, ptr %i50, align 1
+ %i51 = getelementptr inbounds i8, ptr %i50, i64 1
+ store i8 20, ptr %i51, align 1
+ %i52 = getelementptr inbounds i8, ptr %i51, i64 1
+ store i8 20, ptr %i52, align 1
+ %i53 = getelementptr inbounds i8, ptr %i52, i64 1
+ %i54 = getelementptr inbounds i8, ptr %i2, i64 16
br label %bb55
bb55: ; preds = %bb55, %bb
- %i56 = phi i8* [ %i53, %bb ], [ %i57, %bb55 ]
- store i8 0, i8* %i56, align 1
- %i57 = getelementptr inbounds i8, i8* %i56, i64 1
- %i58 = icmp eq i8* %i57, %i54
+ %i56 = phi ptr [ %i53, %bb ], [ %i57, %bb55 ]
+ store i8 0, ptr %i56, align 1
+ %i57 = getelementptr inbounds i8, ptr %i56, i64 1
+ %i58 = icmp eq ptr %i57, %i54
br i1 %i58, label %bb59, label %bb55
bb59: ; preds = %bb55
- %i60 = bitcast %struct.data_t* %i to { i64, i64 }*
- %i61 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %i60, i32 0, i32 0
- %i62 = load i64, i64* %i61, align 1
- %i63 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %i60, i32 0, i32 1
- %i64 = load i64, i64* %i63, align 1
- %i65 = bitcast %struct.data_t* %i1 to { i64, i64 }*
- %i66 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %i65, i32 0, i32 0
- %i67 = load i64, i64* %i66, align 1
- %i68 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %i65, i32 0, i32 1
- %i69 = load i64, i64* %i68, align 1
- %i70 = bitcast %struct.data_t* %i2 to { i64, i64 }*
- %i71 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %i70, i32 0, i32 0
- %i72 = load i64, i64* %i71, align 1
- %i73 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %i70, i32 0, i32 1
- %i74 = load i64, i64* %i73, align 1
+ %i61 = getelementptr inbounds { i64, i64 }, ptr %i, i32 0, i32 0
+ %i62 = load i64, ptr %i61, align 1
+ %i63 = getelementptr inbounds { i64, i64 }, ptr %i, i32 0, i32 1
+ %i64 = load i64, ptr %i63, align 1
+ %i66 = getelementptr inbounds { i64, i64 }, ptr %i1, i32 0, i32 0
+ %i67 = load i64, ptr %i66, align 1
+ %i68 = getelementptr inbounds { i64, i64 }, ptr %i1, i32 0, i32 1
+ %i69 = load i64, ptr %i68, align 1
+ %i71 = getelementptr inbounds { i64, i64 }, ptr %i2, i32 0, i32 0
+ %i72 = load i64, ptr %i71, align 1
+ %i73 = getelementptr inbounds { i64, i64 }, ptr %i2, i32 0, i32 1
+ %i74 = load i64, ptr %i73, align 1
call void @process36data_tS_S_(i64 %i62, i64 %i64, i64 %i67, i64 %i69, i64 %i72, i64 %i74)
ret void
}
@@ -260,120 +245,111 @@ bb:
%i = alloca %struct.data_t, align 1
%i1 = alloca %struct.data_t, align 1
%i2 = alloca %struct.data_t, align 1
- %i3 = getelementptr inbounds %struct.data_t, %struct.data_t* %i, i32 0, i32 0
- %i4 = getelementptr inbounds [16 x i8], [16 x i8]* %i3, i64 0, i64 0
- store i8 1, i8* %i4, align 1
- %i5 = getelementptr inbounds i8, i8* %i4, i64 1
- store i8 2, i8* %i5, align 1
- %i6 = getelementptr inbounds i8, i8* %i5, i64 1
- store i8 3, i8* %i6, align 1
- %i7 = getelementptr inbounds i8, i8* %i6, i64 1
- store i8 4, i8* %i7, align 1
- %i8 = getelementptr inbounds i8, i8* %i7, i64 1
- store i8 5, i8* %i8, align 1
- %i9 = getelementptr inbounds i8, i8* %i8, i64 1
- store i8 0, i8* %i9, align 1
- %i10 = getelementptr inbounds i8, i8* %i9, i64 1
- store i8 0, i8* %i10, align 1
- %i11 = getelementptr inbounds i8, i8* %i10, i64 1
- store i8 0, i8* %i11, align 1
- %i12 = getelementptr inbounds i8, i8* %i11, i64 1
- store i8 0, i8* %i12, align 1
- %i13 = getelementptr inbounds i8, i8* %i12, i64 1
- store i8 0, i8* %i13, align 1
- %i14 = getelementptr inbounds i8, i8* %i13, i64 1
- store i8 0, i8* %i14, align 1
- %i15 = getelementptr inbounds i8, i8* %i14, i64 1
- store i8 0, i8* %i15, align 1
- %i16 = getelementptr inbounds i8, i8* %i15, i64 1
- store i8 0, i8* %i16, align 1
- %i17 = getelementptr inbounds i8, i8* %i16, i64 1
- store i8 0, i8* %i17, align 1
- %i18 = getelementptr inbounds i8, i8* %i17, i64 1
- store i8 0, i8* %i18, align 1
- %i19 = getelementptr inbounds i8, i8* %i18, i64 1
- store i8 0, i8* %i19, align 1
- %i20 = getelementptr inbounds %struct.data_t, %struct.data_t* %i1, i32 0, i32 0
- %i21 = getelementptr inbounds [16 x i8], [16 x i8]* %i20, i64 0, i64 0
- store i8 11, i8* %i21, align 1
- %i22 = getelementptr inbounds i8, i8* %i21, i64 1
- store i8 12, i8* %i22, align 1
- %i23 = getelementptr inbounds i8, i8* %i22, i64 1
- store i8 13, i8* %i23, align 1
- %i24 = getelementptr inbounds i8, i8* %i23, i64 1
- store i8 14, i8* %i24, align 1
- %i25 = getelementptr inbounds i8, i8* %i24, i64 1
- store i8 15, i8* %i25, align 1
- %i26 = getelementptr inbounds i8, i8* %i25, i64 1
- store i8 10, i8* %i26, align 1
- %i27 = getelementptr inbounds i8, i8* %i26, i64 1
- store i8 10, i8* %i27, align 1
- %i28 = getelementptr inbounds i8, i8* %i27, i64 1
- store i8 10, i8* %i28, align 1
- %i29 = getelementptr inbounds i8, i8* %i28, i64 1
- store i8 10, i8* %i29, align 1
- %i30 = getelementptr inbounds i8, i8* %i29, i64 1
- store i8 10, i8* %i30, align 1
- %i31 = getelementptr inbounds i8, i8* %i30, i64 1
- store i8 10, i8* %i31, align 1
- %i32 = getelementptr inbounds i8, i8* %i31, i64 1
- store i8 10, i8* %i32, align 1
- %i33 = getelementptr inbounds i8, i8* %i32, i64 1
- store i8 10, i8* %i33, align 1
- %i34 = getelementptr inbounds i8, i8* %i33, i64 1
- store i8 10, i8* %i34, align 1
- %i35 = getelementptr inbounds i8, i8* %i34, i64 1
- store i8 10, i8* %i35, align 1
- %i36 = getelementptr inbounds i8, i8* %i35, i64 1
- store i8 10, i8* %i36, align 1
- %i37 = getelementptr inbounds %struct.data_t, %struct.data_t* %i2, i32 0, i32 0
- %i38 = getelementptr inbounds [16 x i8], [16 x i8]* %i37, i64 0, i64 0
- store i8 21, i8* %i38, align 1
- %i39 = getelementptr inbounds i8, i8* %i38, i64 1
- store i8 22, i8* %i39, align 1
- %i40 = getelementptr inbounds i8, i8* %i39, i64 1
- store i8 23, i8* %i40, align 1
- %i41 = getelementptr inbounds i8, i8* %i40, i64 1
- store i8 24, i8* %i41, align 1
- %i42 = getelementptr inbounds i8, i8* %i41, i64 1
- store i8 25, i8* %i42, align 1
- %i43 = getelementptr inbounds i8, i8* %i42, i64 1
- store i8 20, i8* %i43, align 1
- %i44 = getelementptr inbounds i8, i8* %i43, i64 1
- store i8 20, i8* %i44, align 1
- %i45 = getelementptr inbounds i8, i8* %i44, i64 1
- store i8 20, i8* %i45, align 1
- %i46 = getelementptr inbounds i8, i8* %i45, i64 1
- store i8 10, i8* %i46, align 1
- %i47 = getelementptr inbounds i8, i8* %i46, i64 1
- store i8 20, i8* %i47, align 1
- %i48 = getelementptr inbounds i8, i8* %i47, i64 1
- store i8 20, i8* %i48, align 1
- %i49 = getelementptr inbounds i8, i8* %i48, i64 1
- store i8 20, i8* %i49, align 1
- %i50 = getelementptr inbounds i8, i8* %i49, i64 1
- store i8 20, i8* %i50, align 1
- %i51 = getelementptr inbounds i8, i8* %i50, i64 1
- store i8 20, i8* %i51, align 1
- %i52 = getelementptr inbounds i8, i8* %i51, i64 1
- store i8 20, i8* %i52, align 1
- %i53 = getelementptr inbounds i8, i8* %i52, i64 1
- store i8 11, i8* %i53, align 1
- %i54 = bitcast %struct.data_t* %i to { i64, i64 }*
- %i55 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %i54, i32 0, i32 0
- %i56 = load i64, i64* %i55, align 1
- %i57 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %i54, i32 0, i32 1
- %i58 = load i64, i64* %i57, align 1
- %i59 = bitcast %struct.data_t* %i1 to { i64, i64 }*
- %i60 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %i59, i32 0, i32 0
- %i61 = load i64, i64* %i60, align 1
- %i62 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %i59, i32 0, i32 1
- %i63 = load i64, i64* %i62, align 1
- %i64 = bitcast %struct.data_t* %i2 to { i64, i64 }*
- %i65 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %i64, i32 0, i32 0
- %i66 = load i64, i64* %i65, align 1
- %i67 = getelementptr inbounds { i64, i64 }, { i64, i64 }* %i64, i32 0, i32 1
- %i68 = load i64, i64* %i67, align 1
+ store i8 1, ptr %i, align 1
+ %i5 = getelementptr inbounds i8, ptr %i, i64 1
+ store i8 2, ptr %i5, align 1
+ %i6 = getelementptr inbounds i8, ptr %i5, i64 1
+ store i8 3, ptr %i6, align 1
+ %i7 = getelementptr inbounds i8, ptr %i6, i64 1
+ store i8 4, ptr %i7, align 1
+ %i8 = getelementptr inbounds i8, ptr %i7, i64 1
+ store i8 5, ptr %i8, align 1
+ %i9 = getelementptr inbounds i8, ptr %i8, i64 1
+ store i8 0, ptr %i9, align 1
+ %i10 = getelementptr inbounds i8, ptr %i9, i64 1
+ store i8 0, ptr %i10, align 1
+ %i11 = getelementptr inbounds i8, ptr %i10, i64 1
+ store i8 0, ptr %i11, align 1
+ %i12 = getelementptr inbounds i8, ptr %i11, i64 1
+ store i8 0, ptr %i12, align 1
+ %i13 = getelementptr inbounds i8, ptr %i12, i64 1
+ store i8 0, ptr %i13, align 1
+ %i14 = getelementptr inbounds i8, ptr %i13, i64 1
+ store i8 0, ptr %i14, align 1
+ %i15 = getelementptr inbounds i8, ptr %i14, i64 1
+ store i8 0, ptr %i15, align 1
+ %i16 = getelementptr inbounds i8, ptr %i15, i64 1
+ store i8 0, ptr %i16, align 1
+ %i17 = getelementptr inbounds i8, ptr %i16, i64 1
+ store i8 0, ptr %i17, align 1
+ %i18 = getelementptr inbounds i8, ptr %i17, i64 1
+ store i8 0, ptr %i18, align 1
+ %i19 = getelementptr inbounds i8, ptr %i18, i64 1
+ store i8 0, ptr %i19, align 1
+ store i8 11, ptr %i1, align 1
+ %i22 = getelementptr inbounds i8, ptr %i1, i64 1
+ store i8 12, ptr %i22, align 1
+ %i23 = getelementptr inbounds i8, ptr %i22, i64 1
+ store i8 13, ptr %i23, align 1
+ %i24 = getelementptr inbounds i8, ptr %i23, i64 1
+ store i8 14, ptr %i24, align 1
+ %i25 = getelementptr inbounds i8, ptr %i24, i64 1
+ store i8 15, ptr %i25, align 1
+ %i26 = getelementptr inbounds i8, ptr %i25, i64 1
+ store i8 10, ptr %i26, align 1
+ %i27 = getelementptr inbounds i8, ptr %i26, i64 1
+ store i8 10, ptr %i27, align 1
+ %i28 = getelementptr inbounds i8, ptr %i27, i64 1
+ store i8 10, ptr %i28, align 1
+ %i29 = getelementptr inbounds i8, ptr %i28, i64 1
+ store i8 10, ptr %i29, align 1
+ %i30 = getelementptr inbounds i8, ptr %i29, i64 1
+ store i8 10, ptr %i30, align 1
+ %i31 = getelementptr inbounds i8, ptr %i30, i64 1
+ store i8 10, ptr %i31, align 1
+ %i32 = getelementptr inbounds i8, ptr %i31, i64 1
+ store i8 10, ptr %i32, align 1
+ %i33 = getelementptr inbounds i8, ptr %i32, i64 1
+ store i8 10, ptr %i33, align 1
+ %i34 = getelementptr inbounds i8, ptr %i33, i64 1
+ store i8 10, ptr %i34, align 1
+ %i35 = getelementptr inbounds i8, ptr %i34, i64 1
+ store i8 10, ptr %i35, align 1
+ %i36 = getelementptr inbounds i8, ptr %i35, i64 1
+ store i8 10, ptr %i36, align 1
+ store i8 21, ptr %i2, align 1
+ %i39 = getelementptr inbounds i8, ptr %i2, i64 1
+ store i8 22, ptr %i39, align 1
+ %i40 = getelementptr inbounds i8, ptr %i39, i64 1
+ store i8 23, ptr %i40, align 1
+ %i41 = getelementptr inbounds i8, ptr %i40, i64 1
+ store i8 24, ptr %i41, align 1
+ %i42 = getelementptr inbounds i8, ptr %i41, i64 1
+ store i8 25, ptr %i42, align 1
+ %i43 = getelementptr inbounds i8, ptr %i42, i64 1
+ store i8 20, ptr %i43, align 1
+ %i44 = getelementptr inbounds i8, ptr %i43, i64 1
+ store i8 20, ptr %i44, align 1
+ %i45 = getelementptr inbounds i8, ptr %i44, i64 1
+ store i8 20, ptr %i45, align 1
+ %i46 = getelementptr inbounds i8, ptr %i45, i64 1
+ store i8 10, ptr %i46, align 1
+ %i47 = getelementptr inbounds i8, ptr %i46, i64 1
+ store i8 20, ptr %i47, align 1
+ %i48 = getelementptr inbounds i8, ptr %i47, i64 1
+ store i8 20, ptr %i48, align 1
+ %i49 = getelementptr inbounds i8, ptr %i48, i64 1
+ store i8 20, ptr %i49, align 1
+ %i50 = getelementptr inbounds i8, ptr %i49, i64 1
+ store i8 20, ptr %i50, align 1
+ %i51 = getelementptr inbounds i8, ptr %i50, i64 1
+ store i8 20, ptr %i51, align 1
+ %i52 = getelementptr inbounds i8, ptr %i51, i64 1
+ store i8 20, ptr %i52, align 1
+ %i53 = getelementptr inbounds i8, ptr %i52, i64 1
+ store i8 11, ptr %i53, align 1
+ %i55 = getelementptr inbounds { i64, i64 }, ptr %i, i32 0, i32 0
+ %i56 = load i64, ptr %i55, align 1
+ %i57 = getelementptr inbounds { i64, i64 }, ptr %i, i32 0, i32 1
+ %i58 = load i64, ptr %i57, align 1
+ %i60 = getelementptr inbounds { i64, i64 }, ptr %i1, i32 0, i32 0
+ %i61 = load i64, ptr %i60, align 1
+ %i62 = getelementptr inbounds { i64, i64 }, ptr %i1, i32 0, i32 1
+ %i63 = load i64, ptr %i62, align 1
+ %i65 = getelementptr inbounds { i64, i64 }, ptr %i2, i32 0, i32 0
+ %i66 = load i64, ptr %i65, align 1
+ %i67 = getelementptr inbounds { i64, i64 }, ptr %i2, i32 0, i32 1
+ %i68 = load i64, ptr %i67, align 1
call void @process36data_tS_S_(i64 %i56, i64 %i58, i64 %i61, i64 %i63, i64 %i66, i64 %i68)
ret void
}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/vdiv-nounroll.ll b/llvm/test/Transforms/PhaseOrdering/X86/vdiv-nounroll.ll
index e5642a4f9d010..465b18ade1a7c 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/vdiv-nounroll.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/vdiv-nounroll.ll
@@ -9,12 +9,12 @@ target triple = "x86_64-apple-macosx11.0.0"
; Verify that fdiv is not sunk back into the loop
; after getting hoisted - based on this C source:
;
-; void vdiv(float *a, float b) {
+; void vdiv(ptr a, float b) {
; for (int i = 0; i != 1024; ++i)
; a[i] /= b;
; }
-define void @vdiv(float* %a, float %b) #0 {
+define void @vdiv(ptr %a, float %b) #0 {
; CHECK-LABEL: @vdiv(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i64 0
@@ -23,12 +23,10 @@ define void @vdiv(float* %a, float %b) #0 {
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, float* [[A:%.*]], i64 [[INDEX]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[TMP1]] to <4 x float>*
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, <4 x float>* [[TMP2]], align 4, !tbaa [[TBAA3:![0-9]+]]
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[INDEX]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP1]], align 4, !tbaa [[TBAA3:![0-9]+]]
; CHECK-NEXT: [[TMP3:%.*]] = fmul fast <4 x float> [[WIDE_LOAD]], [[TMP0]]
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast float* [[TMP1]] to <4 x float>*
-; CHECK-NEXT: store <4 x float> [[TMP3]], <4 x float>* [[TMP4]], align 4, !tbaa [[TBAA3]]
+; CHECK-NEXT: store <4 x float> [[TMP3]], ptr [[TMP1]], align 4, !tbaa [[TBAA3]]
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; CHECK-NEXT: br i1 [[TMP5]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
@@ -36,49 +34,47 @@ define void @vdiv(float* %a, float %b) #0 {
; CHECK-NEXT: ret void
;
entry:
- %a.addr = alloca float*, align 8
+ %a.addr = alloca ptr, align 8
%b.addr = alloca float, align 4
%i = alloca i32, align 4
- store float* %a, float** %a.addr, align 8, !tbaa !3
- store float %b, float* %b.addr, align 4, !tbaa !7
- %0 = bitcast i32* %i to i8*
- call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #2
- store i32 0, i32* %i, align 4, !tbaa !9
+ store ptr %a, ptr %a.addr, align 8, !tbaa !3
+ store float %b, ptr %b.addr, align 4, !tbaa !7
+ call void @llvm.lifetime.start.p0(i64 4, ptr %i) #2
+ store i32 0, ptr %i, align 4, !tbaa !9
br label %for.cond
for.cond: ; preds = %for.inc, %entry
- %1 = load i32, i32* %i, align 4, !tbaa !9
- %cmp = icmp ne i32 %1, 1024
+ %0 = load i32, ptr %i, align 4, !tbaa !9
+ %cmp = icmp ne i32 %0, 1024
br i1 %cmp, label %for.body, label %for.cond.cleanup
for.cond.cleanup: ; preds = %for.cond
- %2 = bitcast i32* %i to i8*
- call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #2
+ call void @llvm.lifetime.end.p0(i64 4, ptr %i) #2
br label %for.end
for.body: ; preds = %for.cond
- %3 = load float, float* %b.addr, align 4, !tbaa !7
- %4 = load float*, float** %a.addr, align 8, !tbaa !3
- %5 = load i32, i32* %i, align 4, !tbaa !9
- %idxprom = sext i32 %5 to i64
- %arrayidx = getelementptr inbounds float, float* %4, i64 %idxprom
- %6 = load float, float* %arrayidx, align 4, !tbaa !7
- %div = fdiv fast float %6, %3
- store float %div, float* %arrayidx, align 4, !tbaa !7
+ %1 = load float, ptr %b.addr, align 4, !tbaa !7
+ %2 = load ptr, ptr %a.addr, align 8, !tbaa !3
+ %3 = load i32, ptr %i, align 4, !tbaa !9
+ %idxprom = sext i32 %3 to i64
+ %arrayidx = getelementptr inbounds float, ptr %2, i64 %idxprom
+ %4 = load float, ptr %arrayidx, align 4, !tbaa !7
+ %div = fdiv fast float %4, %1
+ store float %div, ptr %arrayidx, align 4, !tbaa !7
br label %for.inc
for.inc: ; preds = %for.body
- %7 = load i32, i32* %i, align 4, !tbaa !9
- %inc = add nsw i32 %7, 1
- store i32 %inc, i32* %i, align 4, !tbaa !9
+ %5 = load i32, ptr %i, align 4, !tbaa !9
+ %inc = add nsw i32 %5, 1
+ store i32 %inc, ptr %i, align 4, !tbaa !9
br label %for.cond, !llvm.loop !11
for.end: ; preds = %for.cond.cleanup
ret void
}
-declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1
-declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1
attributes #0 = { nounwind ssp uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="penryn" "target-features"="+cx16,+cx8,+fxsr,+mmx,+sahf,+sse,+sse2,+sse3,+sse4.1,+ssse3,+x87" "tune-cpu"="generic" "unsafe-fp-math"="true" }
attributes #1 = { argmemonly nofree nosync nounwind willreturn }
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/vdiv.ll b/llvm/test/Transforms/PhaseOrdering/X86/vdiv.ll
index ff18d7c334b03..11b6f72793db0 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/vdiv.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/vdiv.ll
@@ -11,14 +11,14 @@
target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.15.0"
-define void @vdiv(double* %x, double* %y, double %a, i32 %N) #0 {
+define void @vdiv(ptr %x, ptr %y, double %a, i32 %N) #0 {
; CHECK-LABEL: @vdiv(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[N:%.*]], 0
; CHECK-NEXT: br i1 [[CMP1]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_END:%.*]]
; CHECK: for.body.preheader:
-; CHECK-NEXT: [[X4:%.*]] = ptrtoint double* [[X:%.*]] to i64
-; CHECK-NEXT: [[Y5:%.*]] = ptrtoint double* [[Y:%.*]] to i64
+; CHECK-NEXT: [[X4:%.*]] = ptrtoint ptr [[X:%.*]] to i64
+; CHECK-NEXT: [[Y5:%.*]] = ptrtoint ptr [[Y:%.*]] to i64
; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[N]] to i64
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 16
; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[X4]], [[Y5]]
@@ -55,63 +55,47 @@ define void @vdiv(double* %x, double* %y, double %a, i32 %N) #0 {
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH_NEW]] ], [ [[INDEX_NEXT_1:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[VECTOR_PH_NEW]] ], [ [[NITER_NEXT_1:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds double, double* [[Y]], i64 [[INDEX]]
-; CHECK-NEXT: [[TMP14:%.*]] = bitcast double* [[TMP13]] to <4 x double>*
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x double>, <4 x double>* [[TMP14]], align 8, !tbaa [[TBAA3:![0-9]+]]
-; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds double, double* [[TMP13]], i64 4
-; CHECK-NEXT: [[TMP16:%.*]] = bitcast double* [[TMP15]] to <4 x double>*
-; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x double>, <4 x double>* [[TMP16]], align 8, !tbaa [[TBAA3]]
-; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds double, double* [[TMP13]], i64 8
-; CHECK-NEXT: [[TMP18:%.*]] = bitcast double* [[TMP17]] to <4 x double>*
-; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x double>, <4 x double>* [[TMP18]], align 8, !tbaa [[TBAA3]]
-; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds double, double* [[TMP13]], i64 12
-; CHECK-NEXT: [[TMP20:%.*]] = bitcast double* [[TMP19]] to <4 x double>*
-; CHECK-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x double>, <4 x double>* [[TMP20]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds double, ptr [[Y]], i64 [[INDEX]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x double>, ptr [[TMP13]], align 8, !tbaa [[TBAA3:![0-9]+]]
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds double, ptr [[TMP13]], i64 4
+; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x double>, ptr [[TMP15]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds double, ptr [[TMP13]], i64 8
+; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x double>, ptr [[TMP17]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds double, ptr [[TMP13]], i64 12
+; CHECK-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x double>, ptr [[TMP19]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[TMP21:%.*]] = fmul fast <4 x double> [[WIDE_LOAD]], [[TMP5]]
; CHECK-NEXT: [[TMP22:%.*]] = fmul fast <4 x double> [[WIDE_LOAD6]], [[TMP6]]
; CHECK-NEXT: [[TMP23:%.*]] = fmul fast <4 x double> [[WIDE_LOAD7]], [[TMP7]]
; CHECK-NEXT: [[TMP24:%.*]] = fmul fast <4 x double> [[WIDE_LOAD8]], [[TMP8]]
-; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds double, double* [[X]], i64 [[INDEX]]
-; CHECK-NEXT: [[TMP26:%.*]] = bitcast double* [[TMP25]] to <4 x double>*
-; CHECK-NEXT: store <4 x double> [[TMP21]], <4 x double>* [[TMP26]], align 8, !tbaa [[TBAA3]]
-; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds double, double* [[TMP25]], i64 4
-; CHECK-NEXT: [[TMP28:%.*]] = bitcast double* [[TMP27]] to <4 x double>*
-; CHECK-NEXT: store <4 x double> [[TMP22]], <4 x double>* [[TMP28]], align 8, !tbaa [[TBAA3]]
-; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds double, double* [[TMP25]], i64 8
-; CHECK-NEXT: [[TMP30:%.*]] = bitcast double* [[TMP29]] to <4 x double>*
-; CHECK-NEXT: store <4 x double> [[TMP23]], <4 x double>* [[TMP30]], align 8, !tbaa [[TBAA3]]
-; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds double, double* [[TMP25]], i64 12
-; CHECK-NEXT: [[TMP32:%.*]] = bitcast double* [[TMP31]] to <4 x double>*
-; CHECK-NEXT: store <4 x double> [[TMP24]], <4 x double>* [[TMP32]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds double, ptr [[X]], i64 [[INDEX]]
+; CHECK-NEXT: store <4 x double> [[TMP21]], ptr [[TMP25]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds double, ptr [[TMP25]], i64 4
+; CHECK-NEXT: store <4 x double> [[TMP22]], ptr [[TMP27]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds double, ptr [[TMP25]], i64 8
+; CHECK-NEXT: store <4 x double> [[TMP23]], ptr [[TMP29]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds double, ptr [[TMP25]], i64 12
+; CHECK-NEXT: store <4 x double> [[TMP24]], ptr [[TMP31]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[INDEX_NEXT:%.*]] = or i64 [[INDEX]], 16
-; CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds double, double* [[Y]], i64 [[INDEX_NEXT]]
-; CHECK-NEXT: [[TMP34:%.*]] = bitcast double* [[TMP33]] to <4 x double>*
-; CHECK-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x double>, <4 x double>* [[TMP34]], align 8, !tbaa [[TBAA3]]
-; CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds double, double* [[TMP33]], i64 4
-; CHECK-NEXT: [[TMP36:%.*]] = bitcast double* [[TMP35]] to <4 x double>*
-; CHECK-NEXT: [[WIDE_LOAD6_1:%.*]] = load <4 x double>, <4 x double>* [[TMP36]], align 8, !tbaa [[TBAA3]]
-; CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds double, double* [[TMP33]], i64 8
-; CHECK-NEXT: [[TMP38:%.*]] = bitcast double* [[TMP37]] to <4 x double>*
-; CHECK-NEXT: [[WIDE_LOAD7_1:%.*]] = load <4 x double>, <4 x double>* [[TMP38]], align 8, !tbaa [[TBAA3]]
-; CHECK-NEXT: [[TMP39:%.*]] = getelementptr inbounds double, double* [[TMP33]], i64 12
-; CHECK-NEXT: [[TMP40:%.*]] = bitcast double* [[TMP39]] to <4 x double>*
-; CHECK-NEXT: [[WIDE_LOAD8_1:%.*]] = load <4 x double>, <4 x double>* [[TMP40]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds double, ptr [[Y]], i64 [[INDEX_NEXT]]
+; CHECK-NEXT: [[WIDE_LOAD_1:%.*]] = load <4 x double>, ptr [[TMP33]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP35:%.*]] = getelementptr inbounds double, ptr [[TMP33]], i64 4
+; CHECK-NEXT: [[WIDE_LOAD6_1:%.*]] = load <4 x double>, ptr [[TMP35]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds double, ptr [[TMP33]], i64 8
+; CHECK-NEXT: [[WIDE_LOAD7_1:%.*]] = load <4 x double>, ptr [[TMP37]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP39:%.*]] = getelementptr inbounds double, ptr [[TMP33]], i64 12
+; CHECK-NEXT: [[WIDE_LOAD8_1:%.*]] = load <4 x double>, ptr [[TMP39]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[TMP41:%.*]] = fmul fast <4 x double> [[WIDE_LOAD_1]], [[TMP9]]
; CHECK-NEXT: [[TMP42:%.*]] = fmul fast <4 x double> [[WIDE_LOAD6_1]], [[TMP10]]
; CHECK-NEXT: [[TMP43:%.*]] = fmul fast <4 x double> [[WIDE_LOAD7_1]], [[TMP11]]
; CHECK-NEXT: [[TMP44:%.*]] = fmul fast <4 x double> [[WIDE_LOAD8_1]], [[TMP12]]
-; CHECK-NEXT: [[TMP45:%.*]] = getelementptr inbounds double, double* [[X]], i64 [[INDEX_NEXT]]
-; CHECK-NEXT: [[TMP46:%.*]] = bitcast double* [[TMP45]] to <4 x double>*
-; CHECK-NEXT: store <4 x double> [[TMP41]], <4 x double>* [[TMP46]], align 8, !tbaa [[TBAA3]]
-; CHECK-NEXT: [[TMP47:%.*]] = getelementptr inbounds double, double* [[TMP45]], i64 4
-; CHECK-NEXT: [[TMP48:%.*]] = bitcast double* [[TMP47]] to <4 x double>*
-; CHECK-NEXT: store <4 x double> [[TMP42]], <4 x double>* [[TMP48]], align 8, !tbaa [[TBAA3]]
-; CHECK-NEXT: [[TMP49:%.*]] = getelementptr inbounds double, double* [[TMP45]], i64 8
-; CHECK-NEXT: [[TMP50:%.*]] = bitcast double* [[TMP49]] to <4 x double>*
-; CHECK-NEXT: store <4 x double> [[TMP43]], <4 x double>* [[TMP50]], align 8, !tbaa [[TBAA3]]
-; CHECK-NEXT: [[TMP51:%.*]] = getelementptr inbounds double, double* [[TMP45]], i64 12
-; CHECK-NEXT: [[TMP52:%.*]] = bitcast double* [[TMP51]] to <4 x double>*
-; CHECK-NEXT: store <4 x double> [[TMP44]], <4 x double>* [[TMP52]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP45:%.*]] = getelementptr inbounds double, ptr [[X]], i64 [[INDEX_NEXT]]
+; CHECK-NEXT: store <4 x double> [[TMP41]], ptr [[TMP45]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP47:%.*]] = getelementptr inbounds double, ptr [[TMP45]], i64 4
+; CHECK-NEXT: store <4 x double> [[TMP42]], ptr [[TMP47]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP49:%.*]] = getelementptr inbounds double, ptr [[TMP45]], i64 8
+; CHECK-NEXT: store <4 x double> [[TMP43]], ptr [[TMP49]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP51:%.*]] = getelementptr inbounds double, ptr [[TMP45]], i64 12
+; CHECK-NEXT: store <4 x double> [[TMP44]], ptr [[TMP51]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[INDEX_NEXT_1]] = add nuw i64 [[INDEX]], 32
; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2
; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]]
@@ -121,34 +105,26 @@ define void @vdiv(double* %x, double* %y, double %a, i32 %N) #0 {
; CHECK-NEXT: [[LCMP_MOD_NOT:%.*]] = icmp eq i64 [[XTRAITER]], 0
; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY_EPIL:%.*]]
; CHECK: vector.body.epil:
-; CHECK-NEXT: [[TMP53:%.*]] = getelementptr inbounds double, double* [[Y]], i64 [[INDEX_UNR]]
-; CHECK-NEXT: [[TMP54:%.*]] = bitcast double* [[TMP53]] to <4 x double>*
-; CHECK-NEXT: [[WIDE_LOAD_EPIL:%.*]] = load <4 x double>, <4 x double>* [[TMP54]], align 8, !tbaa [[TBAA3]]
-; CHECK-NEXT: [[TMP55:%.*]] = getelementptr inbounds double, double* [[TMP53]], i64 4
-; CHECK-NEXT: [[TMP56:%.*]] = bitcast double* [[TMP55]] to <4 x double>*
-; CHECK-NEXT: [[WIDE_LOAD6_EPIL:%.*]] = load <4 x double>, <4 x double>* [[TMP56]], align 8, !tbaa [[TBAA3]]
-; CHECK-NEXT: [[TMP57:%.*]] = getelementptr inbounds double, double* [[TMP53]], i64 8
-; CHECK-NEXT: [[TMP58:%.*]] = bitcast double* [[TMP57]] to <4 x double>*
-; CHECK-NEXT: [[WIDE_LOAD7_EPIL:%.*]] = load <4 x double>, <4 x double>* [[TMP58]], align 8, !tbaa [[TBAA3]]
-; CHECK-NEXT: [[TMP59:%.*]] = getelementptr inbounds double, double* [[TMP53]], i64 12
-; CHECK-NEXT: [[TMP60:%.*]] = bitcast double* [[TMP59]] to <4 x double>*
-; CHECK-NEXT: [[WIDE_LOAD8_EPIL:%.*]] = load <4 x double>, <4 x double>* [[TMP60]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP53:%.*]] = getelementptr inbounds double, ptr [[Y]], i64 [[INDEX_UNR]]
+; CHECK-NEXT: [[WIDE_LOAD_EPIL:%.*]] = load <4 x double>, ptr [[TMP53]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP55:%.*]] = getelementptr inbounds double, ptr [[TMP53]], i64 4
+; CHECK-NEXT: [[WIDE_LOAD6_EPIL:%.*]] = load <4 x double>, ptr [[TMP55]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP57:%.*]] = getelementptr inbounds double, ptr [[TMP53]], i64 8
+; CHECK-NEXT: [[WIDE_LOAD7_EPIL:%.*]] = load <4 x double>, ptr [[TMP57]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP59:%.*]] = getelementptr inbounds double, ptr [[TMP53]], i64 12
+; CHECK-NEXT: [[WIDE_LOAD8_EPIL:%.*]] = load <4 x double>, ptr [[TMP59]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[TMP61:%.*]] = fdiv fast <4 x double> [[WIDE_LOAD_EPIL]], [[BROADCAST_SPLAT]]
; CHECK-NEXT: [[TMP62:%.*]] = fdiv fast <4 x double> [[WIDE_LOAD6_EPIL]], [[BROADCAST_SPLAT10]]
; CHECK-NEXT: [[TMP63:%.*]] = fdiv fast <4 x double> [[WIDE_LOAD7_EPIL]], [[BROADCAST_SPLAT12]]
; CHECK-NEXT: [[TMP64:%.*]] = fdiv fast <4 x double> [[WIDE_LOAD8_EPIL]], [[BROADCAST_SPLAT14]]
-; CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds double, double* [[X]], i64 [[INDEX_UNR]]
-; CHECK-NEXT: [[TMP66:%.*]] = bitcast double* [[TMP65]] to <4 x double>*
-; CHECK-NEXT: store <4 x double> [[TMP61]], <4 x double>* [[TMP66]], align 8, !tbaa [[TBAA3]]
-; CHECK-NEXT: [[TMP67:%.*]] = getelementptr inbounds double, double* [[TMP65]], i64 4
-; CHECK-NEXT: [[TMP68:%.*]] = bitcast double* [[TMP67]] to <4 x double>*
-; CHECK-NEXT: store <4 x double> [[TMP62]], <4 x double>* [[TMP68]], align 8, !tbaa [[TBAA3]]
-; CHECK-NEXT: [[TMP69:%.*]] = getelementptr inbounds double, double* [[TMP65]], i64 8
-; CHECK-NEXT: [[TMP70:%.*]] = bitcast double* [[TMP69]] to <4 x double>*
-; CHECK-NEXT: store <4 x double> [[TMP63]], <4 x double>* [[TMP70]], align 8, !tbaa [[TBAA3]]
-; CHECK-NEXT: [[TMP71:%.*]] = getelementptr inbounds double, double* [[TMP65]], i64 12
-; CHECK-NEXT: [[TMP72:%.*]] = bitcast double* [[TMP71]] to <4 x double>*
-; CHECK-NEXT: store <4 x double> [[TMP64]], <4 x double>* [[TMP72]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP65:%.*]] = getelementptr inbounds double, ptr [[X]], i64 [[INDEX_UNR]]
+; CHECK-NEXT: store <4 x double> [[TMP61]], ptr [[TMP65]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP67:%.*]] = getelementptr inbounds double, ptr [[TMP65]], i64 4
+; CHECK-NEXT: store <4 x double> [[TMP62]], ptr [[TMP67]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP69:%.*]] = getelementptr inbounds double, ptr [[TMP65]], i64 8
+; CHECK-NEXT: store <4 x double> [[TMP63]], ptr [[TMP69]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[TMP71:%.*]] = getelementptr inbounds double, ptr [[TMP65]], i64 12
+; CHECK-NEXT: store <4 x double> [[TMP64]], ptr [[TMP71]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: br label [[MIDDLE_BLOCK]]
; CHECK: middle.block:
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[WIDE_TRIP_COUNT]]
@@ -166,11 +142,11 @@ define void @vdiv(double* %x, double* %y, double %a, i32 %N) #0 {
; CHECK: for.body.prol:
; CHECK-NEXT: [[INDVARS_IV_PROL:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_PROL:%.*]], [[FOR_BODY_PROL]] ], [ [[INDVARS_IV_PH]], [[FOR_BODY_PROL_PREHEADER]] ]
; CHECK-NEXT: [[PROL_ITER:%.*]] = phi i64 [ [[PROL_ITER_NEXT:%.*]], [[FOR_BODY_PROL]] ], [ 0, [[FOR_BODY_PROL_PREHEADER]] ]
-; CHECK-NEXT: [[ARRAYIDX_PROL:%.*]] = getelementptr inbounds double, double* [[Y]], i64 [[INDVARS_IV_PROL]]
-; CHECK-NEXT: [[T0_PROL:%.*]] = load double, double* [[ARRAYIDX_PROL]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[ARRAYIDX_PROL:%.*]] = getelementptr inbounds double, ptr [[Y]], i64 [[INDVARS_IV_PROL]]
+; CHECK-NEXT: [[T0_PROL:%.*]] = load double, ptr [[ARRAYIDX_PROL]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[TMP76:%.*]] = fmul fast double [[T0_PROL]], [[TMP75]]
-; CHECK-NEXT: [[ARRAYIDX2_PROL:%.*]] = getelementptr inbounds double, double* [[X]], i64 [[INDVARS_IV_PROL]]
-; CHECK-NEXT: store double [[TMP76]], double* [[ARRAYIDX2_PROL]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[ARRAYIDX2_PROL:%.*]] = getelementptr inbounds double, ptr [[X]], i64 [[INDVARS_IV_PROL]]
+; CHECK-NEXT: store double [[TMP76]], ptr [[ARRAYIDX2_PROL]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[INDVARS_IV_NEXT_PROL]] = add nuw nsw i64 [[INDVARS_IV_PROL]], 1
; CHECK-NEXT: [[PROL_ITER_NEXT]] = add i64 [[PROL_ITER]], 1
; CHECK-NEXT: [[PROL_ITER_CMP_NOT:%.*]] = icmp eq i64 [[PROL_ITER_NEXT]], [[XTRAITER16]]
@@ -191,53 +167,53 @@ define void @vdiv(double* %x, double* %y, double %a, i32 %N) #0 {
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_UNR]], [[FOR_BODY_PREHEADER15_NEW]] ], [ [[INDVARS_IV_NEXT_7:%.*]], [[FOR_BODY]] ]
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, double* [[Y]], i64 [[INDVARS_IV]]
-; CHECK-NEXT: [[T0:%.*]] = load double, double* [[ARRAYIDX]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr [[Y]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: [[T0:%.*]] = load double, ptr [[ARRAYIDX]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[TMP86:%.*]] = fmul fast double [[T0]], [[TMP78]]
-; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[X]], i64 [[INDVARS_IV]]
-; CHECK-NEXT: store double [[TMP86]], double* [[ARRAYIDX2]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds double, ptr [[X]], i64 [[INDVARS_IV]]
+; CHECK-NEXT: store double [[TMP86]], ptr [[ARRAYIDX2]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
-; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds double, double* [[Y]], i64 [[INDVARS_IV_NEXT]]
-; CHECK-NEXT: [[T0_1:%.*]] = load double, double* [[ARRAYIDX_1]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds double, ptr [[Y]], i64 [[INDVARS_IV_NEXT]]
+; CHECK-NEXT: [[T0_1:%.*]] = load double, ptr [[ARRAYIDX_1]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[TMP87:%.*]] = fmul fast double [[T0_1]], [[TMP79]]
-; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds double, double* [[X]], i64 [[INDVARS_IV_NEXT]]
-; CHECK-NEXT: store double [[TMP87]], double* [[ARRAYIDX2_1]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds double, ptr [[X]], i64 [[INDVARS_IV_NEXT]]
+; CHECK-NEXT: store double [[TMP87]], ptr [[ARRAYIDX2_1]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 2
-; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds double, double* [[Y]], i64 [[INDVARS_IV_NEXT_1]]
-; CHECK-NEXT: [[T0_2:%.*]] = load double, double* [[ARRAYIDX_2]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds double, ptr [[Y]], i64 [[INDVARS_IV_NEXT_1]]
+; CHECK-NEXT: [[T0_2:%.*]] = load double, ptr [[ARRAYIDX_2]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[TMP88:%.*]] = fmul fast double [[T0_2]], [[TMP80]]
-; CHECK-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds double, double* [[X]], i64 [[INDVARS_IV_NEXT_1]]
-; CHECK-NEXT: store double [[TMP88]], double* [[ARRAYIDX2_2]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds double, ptr [[X]], i64 [[INDVARS_IV_NEXT_1]]
+; CHECK-NEXT: store double [[TMP88]], ptr [[ARRAYIDX2_2]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 3
-; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds double, double* [[Y]], i64 [[INDVARS_IV_NEXT_2]]
-; CHECK-NEXT: [[T0_3:%.*]] = load double, double* [[ARRAYIDX_3]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds double, ptr [[Y]], i64 [[INDVARS_IV_NEXT_2]]
+; CHECK-NEXT: [[T0_3:%.*]] = load double, ptr [[ARRAYIDX_3]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[TMP89:%.*]] = fmul fast double [[T0_3]], [[TMP81]]
-; CHECK-NEXT: [[ARRAYIDX2_3:%.*]] = getelementptr inbounds double, double* [[X]], i64 [[INDVARS_IV_NEXT_2]]
-; CHECK-NEXT: store double [[TMP89]], double* [[ARRAYIDX2_3]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[ARRAYIDX2_3:%.*]] = getelementptr inbounds double, ptr [[X]], i64 [[INDVARS_IV_NEXT_2]]
+; CHECK-NEXT: store double [[TMP89]], ptr [[ARRAYIDX2_3]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 4
-; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds double, double* [[Y]], i64 [[INDVARS_IV_NEXT_3]]
-; CHECK-NEXT: [[T0_4:%.*]] = load double, double* [[ARRAYIDX_4]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds double, ptr [[Y]], i64 [[INDVARS_IV_NEXT_3]]
+; CHECK-NEXT: [[T0_4:%.*]] = load double, ptr [[ARRAYIDX_4]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[TMP90:%.*]] = fmul fast double [[T0_4]], [[TMP82]]
-; CHECK-NEXT: [[ARRAYIDX2_4:%.*]] = getelementptr inbounds double, double* [[X]], i64 [[INDVARS_IV_NEXT_3]]
-; CHECK-NEXT: store double [[TMP90]], double* [[ARRAYIDX2_4]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[ARRAYIDX2_4:%.*]] = getelementptr inbounds double, ptr [[X]], i64 [[INDVARS_IV_NEXT_3]]
+; CHECK-NEXT: store double [[TMP90]], ptr [[ARRAYIDX2_4]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 5
-; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds double, double* [[Y]], i64 [[INDVARS_IV_NEXT_4]]
-; CHECK-NEXT: [[T0_5:%.*]] = load double, double* [[ARRAYIDX_5]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds double, ptr [[Y]], i64 [[INDVARS_IV_NEXT_4]]
+; CHECK-NEXT: [[T0_5:%.*]] = load double, ptr [[ARRAYIDX_5]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[TMP91:%.*]] = fmul fast double [[T0_5]], [[TMP83]]
-; CHECK-NEXT: [[ARRAYIDX2_5:%.*]] = getelementptr inbounds double, double* [[X]], i64 [[INDVARS_IV_NEXT_4]]
-; CHECK-NEXT: store double [[TMP91]], double* [[ARRAYIDX2_5]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[ARRAYIDX2_5:%.*]] = getelementptr inbounds double, ptr [[X]], i64 [[INDVARS_IV_NEXT_4]]
+; CHECK-NEXT: store double [[TMP91]], ptr [[ARRAYIDX2_5]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 6
-; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds double, double* [[Y]], i64 [[INDVARS_IV_NEXT_5]]
-; CHECK-NEXT: [[T0_6:%.*]] = load double, double* [[ARRAYIDX_6]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds double, ptr [[Y]], i64 [[INDVARS_IV_NEXT_5]]
+; CHECK-NEXT: [[T0_6:%.*]] = load double, ptr [[ARRAYIDX_6]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[TMP92:%.*]] = fmul fast double [[T0_6]], [[TMP84]]
-; CHECK-NEXT: [[ARRAYIDX2_6:%.*]] = getelementptr inbounds double, double* [[X]], i64 [[INDVARS_IV_NEXT_5]]
-; CHECK-NEXT: store double [[TMP92]], double* [[ARRAYIDX2_6]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[ARRAYIDX2_6:%.*]] = getelementptr inbounds double, ptr [[X]], i64 [[INDVARS_IV_NEXT_5]]
+; CHECK-NEXT: store double [[TMP92]], ptr [[ARRAYIDX2_6]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 7
-; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds double, double* [[Y]], i64 [[INDVARS_IV_NEXT_6]]
-; CHECK-NEXT: [[T0_7:%.*]] = load double, double* [[ARRAYIDX_7]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds double, ptr [[Y]], i64 [[INDVARS_IV_NEXT_6]]
+; CHECK-NEXT: [[T0_7:%.*]] = load double, ptr [[ARRAYIDX_7]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[TMP93:%.*]] = fmul fast double [[T0_7]], [[TMP85]]
-; CHECK-NEXT: [[ARRAYIDX2_7:%.*]] = getelementptr inbounds double, double* [[X]], i64 [[INDVARS_IV_NEXT_6]]
-; CHECK-NEXT: store double [[TMP93]], double* [[ARRAYIDX2_7]], align 8, !tbaa [[TBAA3]]
+; CHECK-NEXT: [[ARRAYIDX2_7:%.*]] = getelementptr inbounds double, ptr [[X]], i64 [[INDVARS_IV_NEXT_6]]
+; CHECK-NEXT: store double [[TMP93]], ptr [[ARRAYIDX2_7]], align 8, !tbaa [[TBAA3]]
; CHECK-NEXT: [[INDVARS_IV_NEXT_7]] = add nuw nsw i64 [[INDVARS_IV]], 8
; CHECK-NEXT: [[EXITCOND_NOT_7:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_7]], [[WIDE_TRIP_COUNT]]
; CHECK-NEXT: br i1 [[EXITCOND_NOT_7]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
@@ -258,12 +234,12 @@ for.cond.cleanup:
for.body:
%idxprom = sext i32 %n.0 to i64
- %arrayidx = getelementptr inbounds double, double* %y, i64 %idxprom
- %t0 = load double, double* %arrayidx, align 8, !tbaa !3
+ %arrayidx = getelementptr inbounds double, ptr %y, i64 %idxprom
+ %t0 = load double, ptr %arrayidx, align 8, !tbaa !3
%mul = fmul fast double %t0, %div
%idxprom1 = sext i32 %n.0 to i64
- %arrayidx2 = getelementptr inbounds double, double* %x, i64 %idxprom1
- store double %mul, double* %arrayidx2, align 8, !tbaa !3
+ %arrayidx2 = getelementptr inbounds double, ptr %x, i64 %idxprom1
+ store double %mul, ptr %arrayidx2, align 8, !tbaa !3
br label %for.inc
for.inc:
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll
index 00902f0fd9243..c2266435bbc58 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-expanded.ll
@@ -8,11 +8,10 @@
target triple = "x86_64--"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
-define i32 @add_v4i32(i32* %p) #0 {
+define i32 @add_v4i32(ptr %p) #0 {
; CHECK-LABEL: @add_v4i32(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[P:%.*]] to <4 x i32>*
-; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[TMP0]], align 4, !tbaa [[TBAA0:![0-9]+]]
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[P:%.*]], align 4, !tbaa [[TBAA0:![0-9]+]]
; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP1]], [[RDX_SHUF]]
; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <4 x i32> [[BIN_RDX]], <4 x i32> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
@@ -34,8 +33,8 @@ for.cond.cleanup:
for.body:
%idxprom = sext i32 %i.0 to i64
- %arrayidx = getelementptr inbounds i32, i32* %p, i64 %idxprom
- %0 = load i32, i32* %arrayidx, align 4, !tbaa !3
+ %arrayidx = getelementptr inbounds i32, ptr %p, i64 %idxprom
+ %0 = load i32, ptr %arrayidx, align 4, !tbaa !3
%add = add nsw i32 %r.0, %0
br label %for.inc
@@ -47,11 +46,10 @@ for.end:
ret i32 %r.0
}
-define signext i16 @mul_v8i16(i16* %p) #0 {
+define signext i16 @mul_v8i16(ptr %p) #0 {
; CHECK-LABEL: @mul_v8i16(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast i16* [[P:%.*]] to <8 x i16>*
-; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[TMP0]], align 2, !tbaa [[TBAA4:![0-9]+]]
+; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[P:%.*]], align 2, !tbaa [[TBAA4:![0-9]+]]
; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
; CHECK-NEXT: [[BIN_RDX:%.*]] = mul <8 x i16> [[TMP1]], [[RDX_SHUF]]
; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <8 x i16> [[BIN_RDX]], <8 x i16> poison, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
@@ -75,8 +73,8 @@ for.cond.cleanup:
for.body:
%idxprom = sext i32 %i.0 to i64
- %arrayidx = getelementptr inbounds i16, i16* %p, i64 %idxprom
- %0 = load i16, i16* %arrayidx, align 2, !tbaa !7
+ %arrayidx = getelementptr inbounds i16, ptr %p, i64 %idxprom
+ %0 = load i16, ptr %arrayidx, align 2, !tbaa !7
%conv = sext i16 %0 to i32
%conv1 = sext i16 %r.0 to i32
%mul = mul nsw i32 %conv1, %conv
@@ -91,11 +89,10 @@ for.end:
ret i16 %r.0
}
-define signext i8 @or_v16i8(i8* %p) #0 {
+define signext i8 @or_v16i8(ptr %p) #0 {
; CHECK-LABEL: @or_v16i8(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[P:%.*]] to <16 x i8>*
-; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]], align 1, !tbaa [[TBAA6:![0-9]+]]
+; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[P:%.*]], align 1, !tbaa [[TBAA6:![0-9]+]]
; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
; CHECK-NEXT: [[BIN_RDX:%.*]] = or <16 x i8> [[TMP1]], [[RDX_SHUF]]
; CHECK-NEXT: [[RDX_SHUF4:%.*]] = shufflevector <16 x i8> [[BIN_RDX]], <16 x i8> poison, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
@@ -121,8 +118,8 @@ for.cond.cleanup:
for.body:
%idxprom = sext i32 %i.0 to i64
- %arrayidx = getelementptr inbounds i8, i8* %p, i64 %idxprom
- %0 = load i8, i8* %arrayidx, align 1, !tbaa !9
+ %arrayidx = getelementptr inbounds i8, ptr %p, i64 %idxprom
+ %0 = load i8, ptr %arrayidx, align 1, !tbaa !9
%conv = sext i8 %0 to i32
%conv1 = sext i8 %r.0 to i32
%or = or i32 %conv1, %conv
@@ -137,11 +134,10 @@ for.end:
ret i8 %r.0
}
-define i32 @smin_v4i32(i32* %p) #0 {
+define i32 @smin_v4i32(ptr %p) #0 {
; CHECK-LABEL: @smin_v4i32(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[P:%.*]] to <4 x i32>*
-; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[TMP0]], align 4, !tbaa [[TBAA0]]
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[P:%.*]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
; CHECK-NEXT: [[RDX_MINMAX_CMP:%.*]] = icmp slt <4 x i32> [[TMP1]], [[RDX_SHUF]]
; CHECK-NEXT: [[RDX_MINMAX_SELECT:%.*]] = select <4 x i1> [[RDX_MINMAX_CMP]], <4 x i32> [[TMP1]], <4 x i32> [[RDX_SHUF]]
@@ -165,15 +161,15 @@ for.cond.cleanup:
for.body:
%idxprom = sext i32 %i.0 to i64
- %arrayidx = getelementptr inbounds i32, i32* %p, i64 %idxprom
- %0 = load i32, i32* %arrayidx, align 4, !tbaa !3
+ %arrayidx = getelementptr inbounds i32, ptr %p, i64 %idxprom
+ %0 = load i32, ptr %arrayidx, align 4, !tbaa !3
%cmp1 = icmp slt i32 %0, %r.0
br i1 %cmp1, label %cond.true, label %cond.false
cond.true:
%idxprom2 = sext i32 %i.0 to i64
- %arrayidx3 = getelementptr inbounds i32, i32* %p, i64 %idxprom2
- %1 = load i32, i32* %arrayidx3, align 4, !tbaa !3
+ %arrayidx3 = getelementptr inbounds i32, ptr %p, i64 %idxprom2
+ %1 = load i32, ptr %arrayidx3, align 4, !tbaa !3
br label %cond.end
cond.false:
@@ -191,11 +187,10 @@ for.end:
ret i32 %r.0
}
-define i32 @umax_v4i32(i32* %p) #0 {
+define i32 @umax_v4i32(ptr %p) #0 {
; CHECK-LABEL: @umax_v4i32(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[P:%.*]] to <4 x i32>*
-; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[TMP0]], align 4, !tbaa [[TBAA0]]
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[P:%.*]], align 4, !tbaa [[TBAA0]]
; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
; CHECK-NEXT: [[RDX_MINMAX_CMP:%.*]] = icmp ugt <4 x i32> [[TMP1]], [[RDX_SHUF]]
; CHECK-NEXT: [[RDX_MINMAX_SELECT:%.*]] = select <4 x i1> [[RDX_MINMAX_CMP]], <4 x i32> [[TMP1]], <4 x i32> [[RDX_SHUF]]
@@ -219,15 +214,15 @@ for.cond.cleanup:
for.body:
%idxprom = sext i32 %i.0 to i64
- %arrayidx = getelementptr inbounds i32, i32* %p, i64 %idxprom
- %0 = load i32, i32* %arrayidx, align 4, !tbaa !3
+ %arrayidx = getelementptr inbounds i32, ptr %p, i64 %idxprom
+ %0 = load i32, ptr %arrayidx, align 4, !tbaa !3
%cmp1 = icmp ugt i32 %0, %r.0
br i1 %cmp1, label %cond.true, label %cond.false
cond.true:
%idxprom2 = sext i32 %i.0 to i64
- %arrayidx3 = getelementptr inbounds i32, i32* %p, i64 %idxprom2
- %1 = load i32, i32* %arrayidx3, align 4, !tbaa !3
+ %arrayidx3 = getelementptr inbounds i32, ptr %p, i64 %idxprom2
+ %1 = load i32, ptr %arrayidx3, align 4, !tbaa !3
br label %cond.end
cond.false:
@@ -245,11 +240,10 @@ for.end:
ret i32 %r.0
}
-define float @fadd_v4i32(float* %p) #0 {
+define float @fadd_v4i32(ptr %p) #0 {
; CHECK-LABEL: @fadd_v4i32(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast float* [[P:%.*]] to <4 x float>*
-; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[TMP0]], align 4, !tbaa [[TBAA7:![0-9]+]]
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[P:%.*]], align 4, !tbaa [[TBAA7:![0-9]+]]
; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
; CHECK-NEXT: [[BIN_RDX:%.*]] = fadd fast <4 x float> [[TMP1]], [[RDX_SHUF]]
; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <4 x float> [[BIN_RDX]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
@@ -272,8 +266,8 @@ for.cond.cleanup:
for.body:
%idxprom = sext i32 %i.0 to i64
- %arrayidx = getelementptr inbounds float, float* %p, i64 %idxprom
- %0 = load float, float* %arrayidx, align 4, !tbaa !10
+ %arrayidx = getelementptr inbounds float, ptr %p, i64 %idxprom
+ %0 = load float, ptr %arrayidx, align 4, !tbaa !10
%add = fadd fast float %r.0, %0
br label %for.inc
@@ -285,11 +279,10 @@ for.end:
ret float %r.0
}
-define float @fmul_v4i32(float* %p) #0 {
+define float @fmul_v4i32(ptr %p) #0 {
; CHECK-LABEL: @fmul_v4i32(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast float* [[P:%.*]] to <4 x float>*
-; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[TMP0]], align 4, !tbaa [[TBAA7]]
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[P:%.*]], align 4, !tbaa [[TBAA7]]
; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
; CHECK-NEXT: [[BIN_RDX:%.*]] = fmul fast <4 x float> [[TMP1]], [[RDX_SHUF]]
; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <4 x float> [[BIN_RDX]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
@@ -313,8 +306,8 @@ for.cond.cleanup:
for.body:
%idxprom = sext i32 %i.0 to i64
- %arrayidx = getelementptr inbounds float, float* %p, i64 %idxprom
- %0 = load float, float* %arrayidx, align 4, !tbaa !10
+ %arrayidx = getelementptr inbounds float, ptr %p, i64 %idxprom
+ %0 = load float, ptr %arrayidx, align 4, !tbaa !10
%mul = fmul fast float %r.0, %0
br label %for.inc
@@ -326,11 +319,10 @@ for.end:
ret float %r.0
}
-define float @fmin_v4f32(float* %p) #0 {
+define float @fmin_v4f32(ptr %p) #0 {
; CHECK-LABEL: @fmin_v4f32(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast float* [[P:%.*]] to <4 x float>*
-; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[TMP0]], align 4, !tbaa [[TBAA7]]
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[P:%.*]], align 4, !tbaa [[TBAA7]]
; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
; CHECK-NEXT: [[RDX_MINMAX_CMP:%.*]] = fcmp fast olt <4 x float> [[TMP1]], [[RDX_SHUF]]
; CHECK-NEXT: [[RDX_MINMAX_SELECT:%.*]] = select fast <4 x i1> [[RDX_MINMAX_CMP]], <4 x float> [[TMP1]], <4 x float> [[RDX_SHUF]]
@@ -354,15 +346,15 @@ for.cond.cleanup:
for.body:
%idxprom = sext i32 %i.0 to i64
- %arrayidx = getelementptr inbounds float, float* %p, i64 %idxprom
- %0 = load float, float* %arrayidx, align 4, !tbaa !10
+ %arrayidx = getelementptr inbounds float, ptr %p, i64 %idxprom
+ %0 = load float, ptr %arrayidx, align 4, !tbaa !10
%cmp1 = fcmp fast olt float %0, %r.0
br i1 %cmp1, label %cond.true, label %cond.false
cond.true:
%idxprom2 = sext i32 %i.0 to i64
- %arrayidx3 = getelementptr inbounds float, float* %p, i64 %idxprom2
- %1 = load float, float* %arrayidx3, align 4, !tbaa !10
+ %arrayidx3 = getelementptr inbounds float, ptr %p, i64 %idxprom2
+ %1 = load float, ptr %arrayidx3, align 4, !tbaa !10
br label %cond.end
cond.false:
@@ -384,19 +376,19 @@ define available_externally float @max(float %a, float %b) {
entry:
%a.addr = alloca float, align 4
%b.addr = alloca float, align 4
- store float %a, float* %a.addr, align 4
- store float %b, float* %b.addr, align 4
- %0 = load float, float* %a.addr, align 4
- %1 = load float, float* %b.addr, align 4
+ store float %a, ptr %a.addr, align 4
+ store float %b, ptr %b.addr, align 4
+ %0 = load float, ptr %a.addr, align 4
+ %1 = load float, ptr %b.addr, align 4
%cmp = fcmp nnan ninf nsz ogt float %0, %1
br i1 %cmp, label %cond.true, label %cond.false
cond.true: ; preds = %entry
- %2 = load float, float* %a.addr, align 4
+ %2 = load float, ptr %a.addr, align 4
br label %cond.end
cond.false: ; preds = %entry
- %3 = load float, float* %b.addr, align 4
+ %3 = load float, ptr %b.addr, align 4
br label %cond.end
cond.end: ; preds = %cond.false, %cond.true
@@ -406,10 +398,10 @@ cond.end: ; preds = %cond.false, %cond.t
; PR23116
-define float @findMax(<8 x float>* byval(<8 x float>) align 16 %0) {
+define float @findMax(ptr byval(<8 x float>) align 16 %0) {
; CHECK-LABEL: @findMax(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[V:%.*]] = load <8 x float>, <8 x float>* [[TMP0:%.*]], align 16, !tbaa [[TBAA0]]
+; CHECK-NEXT: [[V:%.*]] = load <8 x float>, ptr [[TMP0:%.*]], align 16, !tbaa [[TBAA0]]
; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <8 x float> [[V]], <8 x float> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
; CHECK-NEXT: [[RDX_MINMAX_CMP:%.*]] = fcmp nnan ninf nsz ogt <8 x float> [[V]], [[RDX_SHUF]]
; CHECK-NEXT: [[RDX_MINMAX_SELECT:%.*]] = select nnan ninf nsz <8 x i1> [[RDX_MINMAX_CMP]], <8 x float> [[V]], <8 x float> [[RDX_SHUF]]
@@ -424,29 +416,29 @@ define float @findMax(<8 x float>* byval(<8 x float>) align 16 %0) {
;
entry:
%v.addr = alloca <8 x float>, align 32
- %v = load <8 x float>, <8 x float>* %0, align 16, !tbaa !3
- store <8 x float> %v, <8 x float>* %v.addr, align 32, !tbaa !3
- %1 = load <8 x float>, <8 x float>* %v.addr, align 32, !tbaa !3
+ %v = load <8 x float>, ptr %0, align 16, !tbaa !3
+ store <8 x float> %v, ptr %v.addr, align 32, !tbaa !3
+ %1 = load <8 x float>, ptr %v.addr, align 32, !tbaa !3
%vecext = extractelement <8 x float> %1, i32 0
- %2 = load <8 x float>, <8 x float>* %v.addr, align 32, !tbaa !3
+ %2 = load <8 x float>, ptr %v.addr, align 32, !tbaa !3
%vecext1 = extractelement <8 x float> %2, i32 1
%call = call nnan ninf nsz float @max(float %vecext, float %vecext1)
- %3 = load <8 x float>, <8 x float>* %v.addr, align 32, !tbaa !3
+ %3 = load <8 x float>, ptr %v.addr, align 32, !tbaa !3
%vecext2 = extractelement <8 x float> %3, i32 2
%call3 = call nnan ninf nsz float @max(float %call, float %vecext2)
- %4 = load <8 x float>, <8 x float>* %v.addr, align 32, !tbaa !3
+ %4 = load <8 x float>, ptr %v.addr, align 32, !tbaa !3
%vecext4 = extractelement <8 x float> %4, i32 3
%call5 = call nnan ninf nsz float @max(float %call3, float %vecext4)
- %5 = load <8 x float>, <8 x float>* %v.addr, align 32, !tbaa !3
+ %5 = load <8 x float>, ptr %v.addr, align 32, !tbaa !3
%vecext6 = extractelement <8 x float> %5, i32 4
%call7 = call nnan ninf nsz float @max(float %call5, float %vecext6)
- %6 = load <8 x float>, <8 x float>* %v.addr, align 32, !tbaa !3
+ %6 = load <8 x float>, ptr %v.addr, align 32, !tbaa !3
%vecext8 = extractelement <8 x float> %6, i32 5
%call9 = call nnan ninf nsz float @max(float %call7, float %vecext8)
- %7 = load <8 x float>, <8 x float>* %v.addr, align 32, !tbaa !3
+ %7 = load <8 x float>, ptr %v.addr, align 32, !tbaa !3
%vecext10 = extractelement <8 x float> %7, i32 6
%call11 = call nnan ninf nsz float @max(float %call9, float %vecext10)
- %8 = load <8 x float>, <8 x float>* %v.addr, align 32, !tbaa !3
+ %8 = load <8 x float>, ptr %v.addr, align 32, !tbaa !3
%vecext12 = extractelement <8 x float> %8, i32 7
%call13 = call nnan ninf nsz float @max(float %call11, float %vecext12)
ret float %call13
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
index 1ea2c75062a59..2f5640e5dcfba 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll
@@ -58,13 +58,11 @@ define i32 @ext_ext_partial_add_reduction_and_extra_add_v4i32(<4 x i32> %x, <4 x
; PR43953 - https://bugs.llvm.org/show_bug.cgi?id=43953
; We want to end up with a single reduction on the next 4 tests.
-define i32 @TestVectorsEqual(i32* noalias %Vec0, i32* noalias %Vec1, i32 %Tolerance) {
+define i32 @TestVectorsEqual(ptr noalias %Vec0, ptr noalias %Vec1, i32 %Tolerance) {
; CHECK-LABEL: @TestVectorsEqual(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[VEC0:%.*]] to <4 x i32>*
-; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[TMP0]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32* [[VEC1:%.*]] to <4 x i32>*
-; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* [[TMP2]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[VEC0:%.*]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[VEC1:%.*]], align 4
; CHECK-NEXT: [[TMP4:%.*]] = sub nsw <4 x i32> [[TMP1]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = tail call <4 x i32> @llvm.abs.v4i32(<4 x i32> [[TMP4]], i1 true)
; CHECK-NEXT: [[TMP6:%.*]] = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP5]])
@@ -86,11 +84,11 @@ for.cond.cleanup:
for.body:
%idxprom = sext i32 %Component.0 to i64
- %arrayidx = getelementptr inbounds i32, i32* %Vec0, i64 %idxprom
- %0 = load i32, i32* %arrayidx, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %Vec0, i64 %idxprom
+ %0 = load i32, ptr %arrayidx, align 4
%idxprom1 = sext i32 %Component.0 to i64
- %arrayidx2 = getelementptr inbounds i32, i32* %Vec1, i64 %idxprom1
- %1 = load i32, i32* %arrayidx2, align 4
+ %arrayidx2 = getelementptr inbounds i32, ptr %Vec1, i64 %idxprom1
+ %1 = load i32, ptr %arrayidx2, align 4
%sub = sub nsw i32 %0, %1
%cmp3 = icmp sge i32 %sub, 0
br i1 %cmp3, label %cond.true, label %cond.false
@@ -118,13 +116,11 @@ for.end:
ret i32 %cond6
}
-define i32 @TestVectorsEqual_alt(i32* noalias %Vec0, i32* noalias %Vec1, i32 %Tolerance) {
+define i32 @TestVectorsEqual_alt(ptr noalias %Vec0, ptr noalias %Vec1, i32 %Tolerance) {
; CHECK-LABEL: @TestVectorsEqual_alt(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[VEC0:%.*]] to <4 x i32>*
-; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[TMP0]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32* [[VEC1:%.*]] to <4 x i32>*
-; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* [[TMP2]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[VEC0:%.*]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[VEC1:%.*]], align 4
; CHECK-NEXT: [[TMP4:%.*]] = sub <4 x i32> [[TMP1]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP4]])
; CHECK-NEXT: [[CMP3_NOT:%.*]] = icmp ule i32 [[TMP5]], [[TOLERANCE:%.*]]
@@ -145,11 +141,11 @@ for.cond.cleanup:
for.body:
%idxprom = sext i32 %Component.0 to i64
- %arrayidx = getelementptr inbounds i32, i32* %Vec0, i64 %idxprom
- %0 = load i32, i32* %arrayidx, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %Vec0, i64 %idxprom
+ %0 = load i32, ptr %arrayidx, align 4
%idxprom1 = sext i32 %Component.0 to i64
- %arrayidx2 = getelementptr inbounds i32, i32* %Vec1, i64 %idxprom1
- %1 = load i32, i32* %arrayidx2, align 4
+ %arrayidx2 = getelementptr inbounds i32, ptr %Vec1, i64 %idxprom1
+ %1 = load i32, ptr %arrayidx2, align 4
%sub = sub i32 %0, %1
%add = add i32 %sum.0, %sub
br label %for.inc
@@ -165,13 +161,11 @@ for.end:
ret i32 %cond
}
-define i32 @TestVectorsEqualFP(float* noalias %Vec0, float* noalias %Vec1, float %Tolerance) {
+define i32 @TestVectorsEqualFP(ptr noalias %Vec0, ptr noalias %Vec1, float %Tolerance) {
; CHECK-LABEL: @TestVectorsEqualFP(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast float* [[VEC0:%.*]] to <4 x float>*
-; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[TMP0]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[VEC1:%.*]] to <4 x float>*
-; CHECK-NEXT: [[TMP3:%.*]] = load <4 x float>, <4 x float>* [[TMP2]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[VEC0:%.*]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr [[VEC1:%.*]], align 4
; CHECK-NEXT: [[TMP4:%.*]] = fsub fast <4 x float> [[TMP1]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = tail call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP4]])
; CHECK-NEXT: [[TMP6:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP5]])
@@ -193,11 +187,11 @@ for.cond.cleanup:
for.body:
%idxprom = sext i32 %Component.0 to i64
- %arrayidx = getelementptr inbounds float, float* %Vec0, i64 %idxprom
- %0 = load float, float* %arrayidx, align 4
+ %arrayidx = getelementptr inbounds float, ptr %Vec0, i64 %idxprom
+ %0 = load float, ptr %arrayidx, align 4
%idxprom1 = sext i32 %Component.0 to i64
- %arrayidx2 = getelementptr inbounds float, float* %Vec1, i64 %idxprom1
- %1 = load float, float* %arrayidx2, align 4
+ %arrayidx2 = getelementptr inbounds float, ptr %Vec1, i64 %idxprom1
+ %1 = load float, ptr %arrayidx2, align 4
%sub = fsub fast float %0, %1
%cmp3 = fcmp fast oge float %sub, 0.000000e+00
br i1 %cmp3, label %cond.true, label %cond.false
@@ -225,13 +219,11 @@ for.end:
ret i32 %cond5
}
-define i32 @TestVectorsEqualFP_alt(float* noalias %Vec0, float* noalias %Vec1, float %Tolerance) {
+define i32 @TestVectorsEqualFP_alt(ptr noalias %Vec0, ptr noalias %Vec1, float %Tolerance) {
; CHECK-LABEL: @TestVectorsEqualFP_alt(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast float* [[VEC0:%.*]] to <4 x float>*
-; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[TMP0]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[VEC1:%.*]] to <4 x float>*
-; CHECK-NEXT: [[TMP3:%.*]] = load <4 x float>, <4 x float>* [[TMP2]], align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[VEC0:%.*]], align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr [[VEC1:%.*]], align 4
; CHECK-NEXT: [[TMP4:%.*]] = fsub fast <4 x float> [[TMP1]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = tail call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP4]])
; CHECK-NEXT: [[CMP3:%.*]] = fcmp fast ole float [[TMP5]], [[TOLERANCE:%.*]]
@@ -252,11 +244,11 @@ for.cond.cleanup:
for.body:
%idxprom = sext i32 %Component.0 to i64
- %arrayidx = getelementptr inbounds float, float* %Vec0, i64 %idxprom
- %0 = load float, float* %arrayidx, align 4
+ %arrayidx = getelementptr inbounds float, ptr %Vec0, i64 %idxprom
+ %0 = load float, ptr %arrayidx, align 4
%idxprom1 = sext i32 %Component.0 to i64
- %arrayidx2 = getelementptr inbounds float, float* %Vec1, i64 %idxprom1
- %1 = load float, float* %arrayidx2, align 4
+ %arrayidx2 = getelementptr inbounds float, ptr %Vec1, i64 %idxprom1
+ %1 = load float, ptr %arrayidx2, align 4
%sub = fsub fast float %0, %1
%add = fadd fast float %sum.0, %sub
br label %for.inc
diff --git a/llvm/test/Transforms/PhaseOrdering/assume-explosion.ll b/llvm/test/Transforms/PhaseOrdering/assume-explosion.ll
index 245996cebc800..4d0f039299e76 100644
--- a/llvm/test/Transforms/PhaseOrdering/assume-explosion.ll
+++ b/llvm/test/Transforms/PhaseOrdering/assume-explosion.ll
@@ -23,70 +23,70 @@ define void @f() #0 {
; CHECK-LABEL: @f(
;
entry:
- store i32 5, i32* @c, align 4, !tbaa !3
+ store i32 5, ptr @c, align 4, !tbaa !3
br label %for.cond
for.cond:
- %0 = load i32, i32* @c, align 4, !tbaa !3
+ %0 = load i32, ptr @c, align 4, !tbaa !3
%cmp = icmp sle i32 %0, 63
br i1 %cmp, label %for.body, label %for.end34
for.body:
- store i16 9, i16* @e, align 2, !tbaa !7
+ store i16 9, ptr @e, align 2, !tbaa !7
br label %for.cond1
for.cond1:
- %1 = load i16, i16* @e, align 2, !tbaa !7
+ %1 = load i16, ptr @e, align 2, !tbaa !7
%conv = zext i16 %1 to i32
%cmp2 = icmp sle i32 %conv, 60
br i1 %cmp2, label %for.body4, label %for.end32
for.body4:
- %2 = load i16, i16* @e, align 2, !tbaa !7
+ %2 = load i16, ptr @e, align 2, !tbaa !7
%conv5 = zext i16 %2 to i32
- %3 = load i32, i32* @b, align 4, !tbaa !3
+ %3 = load i32, ptr @b, align 4, !tbaa !3
%xor = xor i32 %conv5, %3
- %4 = load i32, i32* @d, align 4, !tbaa !3
+ %4 = load i32, ptr @d, align 4, !tbaa !3
%cmp6 = icmp ne i32 %xor, %4
br i1 %cmp6, label %if.then, label %if.end27
if.then:
- %5 = load i32, i32* @a, align 4, !tbaa !3
+ %5 = load i32, ptr @a, align 4, !tbaa !3
%conv8 = sext i32 %5 to i64
- %6 = inttoptr i64 %conv8 to i8*
- store i8 3, i8* %6, align 1, !tbaa !9
+ %6 = inttoptr i64 %conv8 to ptr
+ store i8 3, ptr %6, align 1, !tbaa !9
br label %for.cond9
for.cond9:
- %7 = load i8, i8* %6, align 1, !tbaa !9
+ %7 = load i8, ptr %6, align 1, !tbaa !9
%conv10 = sext i8 %7 to i32
%cmp11 = icmp sle i32 %conv10, 32
br i1 %cmp11, label %for.body13, label %for.end26
for.body13:
- %8 = load i8, i8* %6, align 1, !tbaa !9
+ %8 = load i8, ptr %6, align 1, !tbaa !9
%tobool = icmp ne i8 %8, 0
br i1 %tobool, label %if.then14, label %if.end
if.then14:
- store i8 1, i8* bitcast (i32* @a to i8*), align 1, !tbaa !9
+ store i8 1, ptr @a, align 1, !tbaa !9
br label %for.cond15
for.cond15:
- %9 = load i8, i8* bitcast (i32* @a to i8*), align 1, !tbaa !9
+ %9 = load i8, ptr @a, align 1, !tbaa !9
%conv16 = sext i8 %9 to i32
%cmp17 = icmp sle i32 %conv16, 30
br i1 %cmp17, label %for.body19, label %for.end
for.body19:
- %10 = load i32, i32* @c, align 4, !tbaa !3
+ %10 = load i32, ptr @c, align 4, !tbaa !3
%cmp20 = icmp eq i32 0, %10
%conv21 = zext i1 %cmp20 to i32
- %11 = load i8, i8* bitcast (i32* @a to i8*), align 1, !tbaa !9
+ %11 = load i8, ptr @a, align 1, !tbaa !9
%conv22 = sext i8 %11 to i32
%and = and i32 %conv22, %conv21
%conv23 = trunc i32 %and to i8
- store i8 %conv23, i8* bitcast (i32* @a to i8*), align 1, !tbaa !9
+ store i8 %conv23, ptr @a, align 1, !tbaa !9
br label %for.cond15, !llvm.loop !10
for.end:
@@ -96,11 +96,11 @@ if.end:
br label %for.inc
for.inc:
- %12 = load i8, i8* %6, align 1, !tbaa !9
+ %12 = load i8, ptr %6, align 1, !tbaa !9
%conv24 = sext i8 %12 to i32
%add = add nsw i32 %conv24, 1
%conv25 = trunc i32 %add to i8
- store i8 %conv25, i8* %6, align 1, !tbaa !9
+ store i8 %conv25, ptr %6, align 1, !tbaa !9
br label %for.cond9, !llvm.loop !12
for.end26:
@@ -110,28 +110,28 @@ if.end27:
br label %for.inc28
for.inc28:
- %13 = load i16, i16* @e, align 2, !tbaa !7
+ %13 = load i16, ptr @e, align 2, !tbaa !7
%conv29 = zext i16 %13 to i32
%add30 = add nsw i32 %conv29, 1
%conv31 = trunc i32 %add30 to i16
- store i16 %conv31, i16* @e, align 2, !tbaa !7
+ store i16 %conv31, ptr @e, align 2, !tbaa !7
br label %for.cond1, !llvm.loop !13
for.end32:
br label %for.inc33
for.inc33:
- %14 = load i32, i32* @c, align 4, !tbaa !3
+ %14 = load i32, ptr @c, align 4, !tbaa !3
%inc = add nsw i32 %14, 1
- store i32 %inc, i32* @c, align 4, !tbaa !3
+ store i32 %inc, ptr @c, align 4, !tbaa !3
br label %for.cond, !llvm.loop !14
for.end34:
ret void
}
-declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1
-declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1
attributes #0 = { nounwind ssp uwtable "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="penryn" "target-features"="+cx16,+cx8,+fxsr,+mmx,+sahf,+sse,+sse2,+sse3,+sse4.1,+ssse3,+x87" "tune-cpu"="generic" }
attributes #1 = { argmemonly nofree nosync nounwind willreturn }
diff --git a/llvm/test/Transforms/PhaseOrdering/basic.ll b/llvm/test/Transforms/PhaseOrdering/basic.ll
index cc577c801da3a..43d2e522e96e3 100644
--- a/llvm/test/Transforms/PhaseOrdering/basic.ll
+++ b/llvm/test/Transforms/PhaseOrdering/basic.ll
@@ -4,8 +4,8 @@
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-macosx10.6.7"
-declare i8* @malloc(i64)
-declare void @free(i8*)
+declare ptr @malloc(i64)
+declare void @free(ptr)
; PR2338
define void @test1() nounwind ssp {
@@ -13,13 +13,13 @@ define void @test1() nounwind ssp {
; CHECK-NEXT: ret void
;
%retval = alloca i32, align 4
- %i = alloca i8*, align 8
- %call = call i8* @malloc(i64 1)
- store i8* %call, i8** %i, align 8
- %tmp = load i8*, i8** %i, align 8
- store i8 1, i8* %tmp
- %tmp1 = load i8*, i8** %i, align 8
- call void @free(i8* %tmp1)
+ %i = alloca ptr, align 8
+ %call = call ptr @malloc(i64 1)
+ store ptr %call, ptr %i, align 8
+ %tmp = load ptr, ptr %i, align 8
+ store i8 1, ptr %tmp
+ %tmp1 = load ptr, ptr %i, align 8
+ call void @free(ptr %tmp1)
ret void
}
@@ -29,27 +29,25 @@ define void @test1() nounwind ssp {
;
; It it also important that %add is expressed as a multiple of %div so scalar
; evolution can recognize it.
-define i32 @test2(i32 %a, i32* %p) nounwind uwtable ssp {
+define i32 @test2(i32 %a, ptr %p) nounwind uwtable ssp {
; CHECK-LABEL: @test2(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[DIV:%.*]] = lshr i32 [[A:%.*]], 2
-; CHECK-NEXT: store i32 [[DIV]], i32* [[P:%.*]], align 4
+; CHECK-NEXT: store i32 [[DIV]], ptr [[P:%.*]], align 4
; CHECK-NEXT: [[ADD:%.*]] = shl nuw nsw i32 [[DIV]], 1
-; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 1
-; CHECK-NEXT: store i32 [[ADD]], i32* [[ARRAYIDX1]], align 4
+; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[P]], i64 1
+; CHECK-NEXT: store i32 [[ADD]], ptr [[ARRAYIDX1]], align 4
; CHECK-NEXT: ret i32 0
;
entry:
%div = udiv i32 %a, 4
- %arrayidx = getelementptr inbounds i32, i32* %p, i64 0
- store i32 %div, i32* %arrayidx, align 4
+ store i32 %div, ptr %p, align 4
%add = add i32 %div, %div
- %arrayidx1 = getelementptr inbounds i32, i32* %p, i64 1
- store i32 %add, i32* %arrayidx1, align 4
- %arrayidx2 = getelementptr inbounds i32, i32* %p, i64 1
- %0 = load i32, i32* %arrayidx2, align 4
- %arrayidx3 = getelementptr inbounds i32, i32* %p, i64 0
- %1 = load i32, i32* %arrayidx3, align 4
+ %arrayidx1 = getelementptr inbounds i32, ptr %p, i64 1
+ store i32 %add, ptr %arrayidx1, align 4
+ %arrayidx2 = getelementptr inbounds i32, ptr %p, i64 1
+ %0 = load i32, ptr %arrayidx2, align 4
+ %1 = load i32, ptr %p, align 4
%mul = mul i32 2, %1
%sub = sub i32 %0, %mul
ret i32 %sub
diff --git a/llvm/test/Transforms/PhaseOrdering/cmp-logic.ll b/llvm/test/Transforms/PhaseOrdering/cmp-logic.ll
index b1c07a354cd38..923ad9b473692 100644
--- a/llvm/test/Transforms/PhaseOrdering/cmp-logic.ll
+++ b/llvm/test/Transforms/PhaseOrdering/cmp-logic.ll
@@ -136,10 +136,8 @@ define i32 @PR56119(i32 %e.coerce) {
;
entry:
%e = alloca %struct.a, align 4
- %coerce.dive = getelementptr inbounds %struct.a, ptr %e, i32 0, i32 0
- store i32 %e.coerce, ptr %coerce.dive, align 4
- %b = getelementptr inbounds %struct.a, ptr %e, i32 0, i32 0
- %0 = load i32, ptr %b, align 4
+ store i32 %e.coerce, ptr %e, align 4
+ %0 = load i32, ptr %e, align 4
%conv = trunc i32 %0 to i8
%conv1 = trunc i64 -1 to i8
%conv2 = zext i8 %conv to i32
diff --git a/llvm/test/Transforms/PhaseOrdering/d83507-knowledge-retention-bug.ll b/llvm/test/Transforms/PhaseOrdering/d83507-knowledge-retention-bug.ll
index e5dd8dbd77ec9..298af9efc3476 100644
--- a/llvm/test/Transforms/PhaseOrdering/d83507-knowledge-retention-bug.ll
+++ b/llvm/test/Transforms/PhaseOrdering/d83507-knowledge-retention-bug.ll
@@ -2,38 +2,36 @@
; RUN: opt -loop-rotate -instcombine -enable-knowledge-retention -S < %s | FileCheck %s
; RUN: opt -passes='loop(loop-rotate),instcombine' -enable-knowledge-retention -S < %s | FileCheck %s
-%0 = type { %0* }
+%0 = type { ptr }
-define %0* @f1(%0* %i0) local_unnamed_addr {
+define ptr @f1(ptr %i0) local_unnamed_addr {
; CHECK-LABEL: @f1(
; CHECK-NEXT: bb:
; CHECK: br label [[BB3:%.*]]
; CHECK: bb3:
-; CHECK-NEXT: [[I1:%.*]] = phi %0* [ %i0, [[BB:%.*]] ], [ [[I5:%.*]], [[BB3]] ]
-; CHECK-NEXT: call void @llvm.assume(i1 true) [ "nonnull"(%0* [[I1]]) ]
-; CHECK-NEXT: [[I4:%.*]] = getelementptr inbounds [[TMP0:%.*]], %0* [[I1]], i64 0, i32 0
-; CHECK-NEXT: [[I5]] = load %0*, %0** [[I4]], align 8
-; CHECK-NEXT: [[I2:%.*]] = icmp eq %0* [[I5]], null
+; CHECK-NEXT: [[I1:%.*]] = phi ptr [ %i0, [[BB:%.*]] ], [ [[I5:%.*]], [[BB3]] ]
+; CHECK-NEXT: call void @llvm.assume(i1 true) [ "nonnull"(ptr [[I1]]) ]
+; CHECK-NEXT: [[I5]] = load ptr, ptr [[I1]], align 8
+; CHECK-NEXT: [[I2:%.*]] = icmp eq ptr [[I5]], null
; CHECK-NEXT: br i1 [[I2]], label [[BB6:%.*]], label [[BB3]]
; CHECK: bb6:
-; CHECK-NEXT: ret %0* undef
+; CHECK-NEXT: ret ptr undef
;
bb:
br label %bb1
bb1:
- %i = phi %0* [ %i0, %bb ], [ %i5, %bb3 ]
- %i2 = icmp eq %0* %i, null
+ %i = phi ptr [ %i0, %bb ], [ %i5, %bb3 ]
+ %i2 = icmp eq ptr %i, null
br i1 %i2, label %bb6, label %bb3
bb3:
- call void @llvm.assume(i1 true) [ "nonnull"(%0* %i) ]
- %i4 = getelementptr inbounds %0, %0* %i, i64 0, i32 0
- %i5 = load %0*, %0** %i4, align 8
+ call void @llvm.assume(i1 true) [ "nonnull"(ptr %i) ]
+ %i5 = load ptr, ptr %i, align 8
br label %bb1
bb6:
- ret %0* undef
+ ret ptr undef
}
declare void @llvm.assume(i1)
diff --git a/llvm/test/Transforms/PhaseOrdering/dce-after-argument-promotion.ll b/llvm/test/Transforms/PhaseOrdering/dce-after-argument-promotion.ll
index 3f7c224985166..c33fcfbe6ed97 100644
--- a/llvm/test/Transforms/PhaseOrdering/dce-after-argument-promotion.ll
+++ b/llvm/test/Transforms/PhaseOrdering/dce-after-argument-promotion.ll
@@ -7,36 +7,34 @@
@dummy = global i32 0
; CHECK: [[DUMMY:@.*]] = local_unnamed_addr global i32 0
-define internal void @f(%struct.ss* byval(%struct.ss) align 8 %b, i32* byval(i32) align 4 %X) noinline nounwind {
+define internal void @f(ptr byval(%struct.ss) align 8 %b, ptr byval(i32) align 4 %X) noinline nounwind {
; CHECK-LABEL: define {{[^@]+}}@f
; CHECK-SAME: (i32 [[B_0:%.*]]){{[^#]*}} #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TEMP:%.*]] = add i32 [[B_0]], 1
-; CHECK-NEXT: store i32 [[TEMP]], i32* [[DUMMY]], align 4
+; CHECK-NEXT: store i32 [[TEMP]], ptr [[DUMMY]], align 4
; CHECK-NEXT: ret void
;
entry:
- %temp = getelementptr %struct.ss, %struct.ss* %b, i32 0, i32 0
- %temp1 = load i32, i32* %temp, align 4
+ %temp1 = load i32, ptr %b, align 4
%temp2 = add i32 %temp1, 1
- store i32 %temp2, i32* @dummy
- store i32 %temp2, i32* %X
+ store i32 %temp2, ptr @dummy
+ store i32 %temp2, ptr %X
ret void
}
-define i32 @test(i32* %X) {
+define i32 @test(ptr %X) {
; CHECK-LABEL: define {{[^@]+}}@test
-; CHECK-SAME: (i32* {{[^%]*}} [[X:%.*]]){{[^#]*}} #[[ATTR1:[0-9]+]] {
+; CHECK-SAME: (ptr {{[^%]*}} [[X:%.*]]){{[^#]*}} #[[ATTR1:[0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: tail call {{.*}}void @f(i32 1)
; CHECK-NEXT: ret i32 0
;
entry:
%S = alloca %struct.ss, align 8
- %temp1 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 0
- store i32 1, i32* %temp1, align 8
- %temp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1
- store i64 2, i64* %temp4, align 4
- call void @f( %struct.ss* byval(%struct.ss) align 8 %S, i32* byval(i32) align 4 %X)
+ store i32 1, ptr %S, align 8
+ %temp4 = getelementptr %struct.ss, ptr %S, i32 0, i32 1
+ store i64 2, ptr %temp4, align 4
+ call void @f( ptr byval(%struct.ss) align 8 %S, ptr byval(i32) align 4 %X)
ret i32 0
}
diff --git a/llvm/test/Transforms/PhaseOrdering/deletion-of-loops-that-became-side-effect-free.ll b/llvm/test/Transforms/PhaseOrdering/deletion-of-loops-that-became-side-effect-free.ll
index 7df88d111008c..689f4a9798a75 100644
--- a/llvm/test/Transforms/PhaseOrdering/deletion-of-loops-that-became-side-effect-free.ll
+++ b/llvm/test/Transforms/PhaseOrdering/deletion-of-loops-that-became-side-effect-free.ll
@@ -6,125 +6,118 @@
; All these tests should optimize to a single comparison
; of the original argument with null. There should be no loops.
-%struct.node = type { %struct.node*, i32 }
+%struct.node = type { ptr, i32 }
-define dso_local zeroext i1 @is_not_empty_variant1(%struct.node* %p) {
+define dso_local zeroext i1 @is_not_empty_variant1(ptr %p) {
; ALL-LABEL: @is_not_empty_variant1(
; ALL-NEXT: entry:
-; ALL-NEXT: [[TOBOOL_NOT3_I:%.*]] = icmp ne %struct.node* [[P:%.*]], null
+; ALL-NEXT: [[TOBOOL_NOT3_I:%.*]] = icmp ne ptr [[P:%.*]], null
; ALL-NEXT: ret i1 [[TOBOOL_NOT3_I]]
;
entry:
- %p.addr = alloca %struct.node*, align 8
- store %struct.node* %p, %struct.node** %p.addr, align 8
- %0 = load %struct.node*, %struct.node** %p.addr, align 8
- %call = call i32 @count_nodes_variant1(%struct.node* %0)
+ %p.addr = alloca ptr, align 8
+ store ptr %p, ptr %p.addr, align 8
+ %0 = load ptr, ptr %p.addr, align 8
+ %call = call i32 @count_nodes_variant1(ptr %0)
%cmp = icmp sgt i32 %call, 0
ret i1 %cmp
}
-define internal i32 @count_nodes_variant1(%struct.node* %p) {
+define internal i32 @count_nodes_variant1(ptr %p) {
entry:
- %p.addr = alloca %struct.node*, align 8
+ %p.addr = alloca ptr, align 8
%size = alloca i32, align 4
- store %struct.node* %p, %struct.node** %p.addr, align 8
- %0 = bitcast i32* %size to i8*
- store i32 0, i32* %size, align 4
+ store ptr %p, ptr %p.addr, align 8
+ store i32 0, ptr %size, align 4
br label %while.cond
while.cond:
- %1 = load %struct.node*, %struct.node** %p.addr, align 8
- %tobool = icmp ne %struct.node* %1, null
+ %0 = load ptr, ptr %p.addr, align 8
+ %tobool = icmp ne ptr %0, null
br i1 %tobool, label %while.body, label %while.end
while.body:
- %2 = load %struct.node*, %struct.node** %p.addr, align 8
- %next = getelementptr inbounds %struct.node, %struct.node* %2, i32 0, i32 0
- %3 = load %struct.node*, %struct.node** %next, align 8
- store %struct.node* %3, %struct.node** %p.addr, align 8
- %4 = load i32, i32* %size, align 4
- %inc = add nsw i32 %4, 1
- store i32 %inc, i32* %size, align 4
+ %1 = load ptr, ptr %p.addr, align 8
+ %2 = load ptr, ptr %1, align 8
+ store ptr %2, ptr %p.addr, align 8
+ %3 = load i32, ptr %size, align 4
+ %inc = add nsw i32 %3, 1
+ store i32 %inc, ptr %size, align 4
br label %while.cond, !llvm.loop !0
while.end:
- %5 = load i32, i32* %size, align 4
- %6 = bitcast i32* %size to i8*
- ret i32 %5
+ %4 = load i32, ptr %size, align 4
+ ret i32 %4
}
-define dso_local zeroext i1 @is_not_empty_variant2(%struct.node* %p) {
+define dso_local zeroext i1 @is_not_empty_variant2(ptr %p) {
; ALL-LABEL: @is_not_empty_variant2(
; ALL-NEXT: entry:
-; ALL-NEXT: [[TOBOOL_NOT4_I:%.*]] = icmp ne %struct.node* [[P:%.*]], null
+; ALL-NEXT: [[TOBOOL_NOT4_I:%.*]] = icmp ne ptr [[P:%.*]], null
; ALL-NEXT: ret i1 [[TOBOOL_NOT4_I]]
;
entry:
- %p.addr = alloca %struct.node*, align 8
- store %struct.node* %p, %struct.node** %p.addr, align 8
- %0 = load %struct.node*, %struct.node** %p.addr, align 8
- %call = call i64 @count_nodes_variant2(%struct.node* %0)
+ %p.addr = alloca ptr, align 8
+ store ptr %p, ptr %p.addr, align 8
+ %0 = load ptr, ptr %p.addr, align 8
+ %call = call i64 @count_nodes_variant2(ptr %0)
%cmp = icmp ugt i64 %call, 0
ret i1 %cmp
}
-define internal i64 @count_nodes_variant2(%struct.node* %p) {
+define internal i64 @count_nodes_variant2(ptr %p) {
entry:
- %p.addr = alloca %struct.node*, align 8
+ %p.addr = alloca ptr, align 8
%size = alloca i64, align 8
- store %struct.node* %p, %struct.node** %p.addr, align 8
- %0 = bitcast i64* %size to i8*
- store i64 0, i64* %size, align 8
+ store ptr %p, ptr %p.addr, align 8
+ store i64 0, ptr %size, align 8
br label %while.cond
while.cond:
- %1 = load %struct.node*, %struct.node** %p.addr, align 8
- %tobool = icmp ne %struct.node* %1, null
+ %0 = load ptr, ptr %p.addr, align 8
+ %tobool = icmp ne ptr %0, null
br i1 %tobool, label %while.body, label %while.end
while.body:
- %2 = load %struct.node*, %struct.node** %p.addr, align 8
- %next = getelementptr inbounds %struct.node, %struct.node* %2, i32 0, i32 0
- %3 = load %struct.node*, %struct.node** %next, align 8
- store %struct.node* %3, %struct.node** %p.addr, align 8
- %4 = load i64, i64* %size, align 8
- %inc = add i64 %4, 1
- store i64 %inc, i64* %size, align 8
- %5 = load i64, i64* %size, align 8
- %cmp = icmp ne i64 %5, 0
+ %1 = load ptr, ptr %p.addr, align 8
+ %2 = load ptr, ptr %1, align 8
+ store ptr %2, ptr %p.addr, align 8
+ %3 = load i64, ptr %size, align 8
+ %inc = add i64 %3, 1
+ store i64 %inc, ptr %size, align 8
+ %4 = load i64, ptr %size, align 8
+ %cmp = icmp ne i64 %4, 0
call void @_ZL6assumeb(i1 zeroext %cmp)
br label %while.cond, !llvm.loop !2
while.end:
- %6 = load i64, i64* %size, align 8
- %7 = bitcast i64* %size to i8*
- ret i64 %6
+ %5 = load i64, ptr %size, align 8
+ ret i64 %5
}
-define dso_local zeroext i1 @is_not_empty_variant3(%struct.node* %p) {
+define dso_local zeroext i1 @is_not_empty_variant3(ptr %p) {
; O3-LABEL: @is_not_empty_variant3(
; O3-NEXT: entry:
-; O3-NEXT: [[TOBOOL_NOT4_I:%.*]] = icmp ne %struct.node* [[P:%.*]], null
+; O3-NEXT: [[TOBOOL_NOT4_I:%.*]] = icmp ne ptr [[P:%.*]], null
; O3-NEXT: ret i1 [[TOBOOL_NOT4_I]]
;
; O2-LABEL: @is_not_empty_variant3(
; O2-NEXT: entry:
-; O2-NEXT: [[TOBOOL_NOT4_I:%.*]] = icmp ne %struct.node* [[P:%.*]], null
+; O2-NEXT: [[TOBOOL_NOT4_I:%.*]] = icmp ne ptr [[P:%.*]], null
; O2-NEXT: ret i1 [[TOBOOL_NOT4_I]]
;
; O1-LABEL: @is_not_empty_variant3(
; O1-NEXT: entry:
-; O1-NEXT: [[TOBOOL_NOT4_I:%.*]] = icmp eq %struct.node* [[P:%.*]], null
+; O1-NEXT: [[TOBOOL_NOT4_I:%.*]] = icmp eq ptr [[P:%.*]], null
; O1-NEXT: br i1 [[TOBOOL_NOT4_I]], label [[COUNT_NODES_VARIANT3_EXIT:%.*]], label [[WHILE_BODY_I:%.*]]
; O1: while.body.i:
; O1-NEXT: [[SIZE_06_I:%.*]] = phi i64 [ [[INC_I:%.*]], [[WHILE_BODY_I]] ], [ 0, [[ENTRY:%.*]] ]
-; O1-NEXT: [[P_ADDR_05_I:%.*]] = phi %struct.node* [ [[TMP0:%.*]], [[WHILE_BODY_I]] ], [ [[P]], [[ENTRY]] ]
+; O1-NEXT: [[P_ADDR_05_I:%.*]] = phi ptr [ [[TMP0:%.*]], [[WHILE_BODY_I]] ], [ [[P]], [[ENTRY]] ]
; O1-NEXT: [[CMP_I:%.*]] = icmp ne i64 [[SIZE_06_I]], -1
; O1-NEXT: call void @llvm.assume(i1 [[CMP_I]])
-; O1-NEXT: [[NEXT_I:%.*]] = getelementptr inbounds [[STRUCT_NODE:%.*]], %struct.node* [[P_ADDR_05_I]], i64 0, i32 0
-; O1-NEXT: [[TMP0]] = load %struct.node*, %struct.node** [[NEXT_I]], align 8
+; O1-NEXT: [[TMP0]] = load ptr, ptr [[P_ADDR_05_I]], align 8
; O1-NEXT: [[INC_I]] = add i64 [[SIZE_06_I]], 1
-; O1-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq %struct.node* [[TMP0]], null
+; O1-NEXT: [[TOBOOL_NOT_I:%.*]] = icmp eq ptr [[TMP0]], null
; O1-NEXT: br i1 [[TOBOOL_NOT_I]], label [[COUNT_NODES_VARIANT3_EXIT_LOOPEXIT:%.*]], label [[WHILE_BODY_I]], !llvm.loop [[LOOP0:![0-9]+]]
; O1: count_nodes_variant3.exit.loopexit:
; O1-NEXT: [[PHI_CMP:%.*]] = icmp ne i64 [[INC_I]], 0
@@ -134,53 +127,50 @@ define dso_local zeroext i1 @is_not_empty_variant3(%struct.node* %p) {
; O1-NEXT: ret i1 [[SIZE_0_LCSSA_I]]
;
entry:
- %p.addr = alloca %struct.node*, align 8
- store %struct.node* %p, %struct.node** %p.addr, align 8
- %0 = load %struct.node*, %struct.node** %p.addr, align 8
- %call = call i64 @count_nodes_variant3(%struct.node* %0)
+ %p.addr = alloca ptr, align 8
+ store ptr %p, ptr %p.addr, align 8
+ %0 = load ptr, ptr %p.addr, align 8
+ %call = call i64 @count_nodes_variant3(ptr %0)
%cmp = icmp ugt i64 %call, 0
ret i1 %cmp
}
-define internal i64 @count_nodes_variant3(%struct.node* %p) {
+define internal i64 @count_nodes_variant3(ptr %p) {
entry:
- %p.addr = alloca %struct.node*, align 8
+ %p.addr = alloca ptr, align 8
%size = alloca i64, align 8
- store %struct.node* %p, %struct.node** %p.addr, align 8
- %0 = bitcast i64* %size to i8*
- store i64 0, i64* %size, align 8
+ store ptr %p, ptr %p.addr, align 8
+ store i64 0, ptr %size, align 8
br label %while.cond
while.cond:
- %1 = load %struct.node*, %struct.node** %p.addr, align 8
- %tobool = icmp ne %struct.node* %1, null
+ %0 = load ptr, ptr %p.addr, align 8
+ %tobool = icmp ne ptr %0, null
br i1 %tobool, label %while.body, label %while.end
while.body:
- %2 = load i64, i64* %size, align 8
- %cmp = icmp ne i64 %2, -1
+ %1 = load i64, ptr %size, align 8
+ %cmp = icmp ne i64 %1, -1
call void @_ZL6assumeb(i1 zeroext %cmp)
- %3 = load %struct.node*, %struct.node** %p.addr, align 8
- %next = getelementptr inbounds %struct.node, %struct.node* %3, i32 0, i32 0
- %4 = load %struct.node*, %struct.node** %next, align 8
- store %struct.node* %4, %struct.node** %p.addr, align 8
- %5 = load i64, i64* %size, align 8
- %inc = add i64 %5, 1
- store i64 %inc, i64* %size, align 8
+ %2 = load ptr, ptr %p.addr, align 8
+ %3 = load ptr, ptr %2, align 8
+ store ptr %3, ptr %p.addr, align 8
+ %4 = load i64, ptr %size, align 8
+ %inc = add i64 %4, 1
+ store i64 %inc, ptr %size, align 8
br label %while.cond, !llvm.loop !3
while.end:
- %6 = load i64, i64* %size, align 8
- %7 = bitcast i64* %size to i8*
- ret i64 %6
+ %5 = load i64, ptr %size, align 8
+ ret i64 %5
}
define internal void @_ZL6assumeb(i1 zeroext %expression) {
entry:
%expression.addr = alloca i8, align 1
%frombool = zext i1 %expression to i8
- store i8 %frombool, i8* %expression.addr, align 1
- %0 = load i8, i8* %expression.addr, align 1
+ store i8 %frombool, ptr %expression.addr, align 1
+ %0 = load i8, ptr %expression.addr, align 1
%tobool = trunc i8 %0 to i1
call void @llvm.assume(i1 %tobool)
ret void
diff --git a/llvm/test/Transforms/PhaseOrdering/expect.ll b/llvm/test/Transforms/PhaseOrdering/expect.ll
index 3a23785ddff78..a2dfecf96e333 100644
--- a/llvm/test/Transforms/PhaseOrdering/expect.ll
+++ b/llvm/test/Transforms/PhaseOrdering/expect.ll
@@ -6,7 +6,7 @@
; backend can't undo. Expect lowering becomes metadata,
; and passes like SimplifyCFG should respect that.
-define void @PR49336(i32 %delta, i32 %tag_type, i8* %ip) {
+define void @PR49336(i32 %delta, i32 %tag_type, ptr %ip) {
; CHECK-LABEL: @PR49336(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[DELTA:%.*]], 0
@@ -15,7 +15,7 @@ define void @PR49336(i32 %delta, i32 %tag_type, i8* %ip) {
; CHECK-NEXT: [[CMP1_NOT:%.*]] = icmp eq i32 [[TAG_TYPE:%.*]], 0
; CHECK-NEXT: br i1 [[CMP1_NOT]], label [[IF_END3]], label [[IF_THEN2:%.*]]
; CHECK: if.then2:
-; CHECK-NEXT: store i8 42, i8* [[IP:%.*]], align 1
+; CHECK-NEXT: store i8 42, ptr [[IP:%.*]], align 1
; CHECK-NEXT: br label [[IF_END3]]
; CHECK: if.end3:
; CHECK-NEXT: ret void
@@ -23,11 +23,11 @@ define void @PR49336(i32 %delta, i32 %tag_type, i8* %ip) {
entry:
%delta.addr = alloca i32, align 4
%tag_type.addr = alloca i32, align 4
- %ip.addr = alloca i8*, align 8
- store i32 %delta, i32* %delta.addr, align 4
- store i32 %tag_type, i32* %tag_type.addr, align 4
- store i8* %ip, i8** %ip.addr, align 8
- %0 = load i32, i32* %delta.addr, align 4
+ %ip.addr = alloca ptr, align 8
+ store i32 %delta, ptr %delta.addr, align 4
+ store i32 %tag_type, ptr %tag_type.addr, align 4
+ store ptr %ip, ptr %ip.addr, align 8
+ %0 = load i32, ptr %delta.addr, align 4
%cmp = icmp slt i32 %0, 0
%conv = zext i1 %cmp to i64
%expval = call i64 @llvm.expect.i64(i64 %conv, i64 0)
@@ -35,13 +35,13 @@ entry:
br i1 %tobool, label %if.then, label %if.end3
if.then:
- %1 = load i32, i32* %tag_type.addr, align 4
+ %1 = load i32, ptr %tag_type.addr, align 4
%cmp1 = icmp ne i32 %1, 0
br i1 %cmp1, label %if.then2, label %if.end
if.then2:
- %2 = load i8*, i8** %ip.addr, align 8
- store i8 42, i8* %2, align 1
+ %2 = load ptr, ptr %ip.addr, align 8
+ store i8 42, ptr %2, align 1
br label %if.end
if.end:
diff --git a/llvm/test/Transforms/PhaseOrdering/fast-reassociate-gvn.ll b/llvm/test/Transforms/PhaseOrdering/fast-reassociate-gvn.ll
index 11c4d7afbcacb..b8710b5ae1934 100644
--- a/llvm/test/Transforms/PhaseOrdering/fast-reassociate-gvn.ll
+++ b/llvm/test/Transforms/PhaseOrdering/fast-reassociate-gvn.ll
@@ -29,75 +29,75 @@
define void @test3() {
; CHECK-LABEL: @test3(
-; CHECK-NEXT: [[A:%.*]] = load float, float* @fa, align 4
-; CHECK-NEXT: [[B:%.*]] = load float, float* @fb, align 4
-; CHECK-NEXT: [[C:%.*]] = load float, float* @fc, align 4
+; CHECK-NEXT: [[A:%.*]] = load float, ptr @fa, align 4
+; CHECK-NEXT: [[B:%.*]] = load float, ptr @fb, align 4
+; CHECK-NEXT: [[C:%.*]] = load float, ptr @fc, align 4
; CHECK-NEXT: [[T1:%.*]] = fadd fast float [[B]], [[A]]
; CHECK-NEXT: [[T2:%.*]] = fadd fast float [[T1]], [[C]]
-; CHECK-NEXT: store float [[T2]], float* @fe, align 4
-; CHECK-NEXT: store float [[T2]], float* @ff, align 4
+; CHECK-NEXT: store float [[T2]], ptr @fe, align 4
+; CHECK-NEXT: store float [[T2]], ptr @ff, align 4
; CHECK-NEXT: ret void
;
- %A = load float, float* @fa
- %B = load float, float* @fb
- %C = load float, float* @fc
+ %A = load float, ptr @fa
+ %B = load float, ptr @fb
+ %C = load float, ptr @fc
%t1 = fadd fast float %A, %B
%t2 = fadd fast float %t1, %C
%t3 = fadd fast float %A, %C
%t4 = fadd fast float %t3, %B
; e = (a+b)+c;
- store float %t2, float* @fe
+ store float %t2, ptr @fe
; f = (a+c)+b
- store float %t4, float* @ff
+ store float %t4, ptr @ff
ret void
}
define void @test4() {
; CHECK-LABEL: @test4(
-; CHECK-NEXT: [[A:%.*]] = load float, float* @fa, align 4
-; CHECK-NEXT: [[B:%.*]] = load float, float* @fb, align 4
-; CHECK-NEXT: [[C:%.*]] = load float, float* @fc, align 4
+; CHECK-NEXT: [[A:%.*]] = load float, ptr @fa, align 4
+; CHECK-NEXT: [[B:%.*]] = load float, ptr @fb, align 4
+; CHECK-NEXT: [[C:%.*]] = load float, ptr @fc, align 4
; CHECK-NEXT: [[T1:%.*]] = fadd fast float [[B]], [[A]]
; CHECK-NEXT: [[T2:%.*]] = fadd fast float [[T1]], [[C]]
-; CHECK-NEXT: store float [[T2]], float* @fe, align 4
-; CHECK-NEXT: store float [[T2]], float* @ff, align 4
+; CHECK-NEXT: store float [[T2]], ptr @fe, align 4
+; CHECK-NEXT: store float [[T2]], ptr @ff, align 4
; CHECK-NEXT: ret void
;
- %A = load float, float* @fa
- %B = load float, float* @fb
- %C = load float, float* @fc
+ %A = load float, ptr @fa
+ %B = load float, ptr @fb
+ %C = load float, ptr @fc
%t1 = fadd fast float %A, %B
%t2 = fadd fast float %C, %t1
%t3 = fadd fast float %C, %A
%t4 = fadd fast float %t3, %B
; e = c+(a+b)
- store float %t2, float* @fe
+ store float %t2, ptr @fe
; f = (c+a)+b
- store float %t4, float* @ff
+ store float %t4, ptr @ff
ret void
}
define void @test5() {
; CHECK-LABEL: @test5(
-; CHECK-NEXT: [[A:%.*]] = load float, float* @fa, align 4
-; CHECK-NEXT: [[B:%.*]] = load float, float* @fb, align 4
-; CHECK-NEXT: [[C:%.*]] = load float, float* @fc, align 4
+; CHECK-NEXT: [[A:%.*]] = load float, ptr @fa, align 4
+; CHECK-NEXT: [[B:%.*]] = load float, ptr @fb, align 4
+; CHECK-NEXT: [[C:%.*]] = load float, ptr @fc, align 4
; CHECK-NEXT: [[T1:%.*]] = fadd fast float [[B]], [[A]]
; CHECK-NEXT: [[T2:%.*]] = fadd fast float [[T1]], [[C]]
-; CHECK-NEXT: store float [[T2]], float* @fe, align 4
-; CHECK-NEXT: store float [[T2]], float* @ff, align 4
+; CHECK-NEXT: store float [[T2]], ptr @fe, align 4
+; CHECK-NEXT: store float [[T2]], ptr @ff, align 4
; CHECK-NEXT: ret void
;
- %A = load float, float* @fa
- %B = load float, float* @fb
- %C = load float, float* @fc
+ %A = load float, ptr @fa
+ %B = load float, ptr @fb
+ %C = load float, ptr @fc
%t1 = fadd fast float %B, %A
%t2 = fadd fast float %C, %t1
%t3 = fadd fast float %C, %A
%t4 = fadd fast float %t3, %B
; e = c+(b+a)
- store float %t2, float* @fe
+ store float %t2, ptr @fe
; f = (c+a)+b
- store float %t4, float* @ff
+ store float %t4, ptr @ff
ret void
}
diff --git a/llvm/test/Transforms/PhaseOrdering/gdce.ll b/llvm/test/Transforms/PhaseOrdering/gdce.ll
index fa62f92500bd4..30654fe79ec3b 100644
--- a/llvm/test/Transforms/PhaseOrdering/gdce.ll
+++ b/llvm/test/Transforms/PhaseOrdering/gdce.ll
@@ -10,97 +10,94 @@
; CHECK-NOT: _ZN4BaseC2Ev
; CHECK-NOT: _ZN4BaseD0Ev
-%class.Base = type { i32 (...)** }
+%class.Base = type { ptr }
- at _ZTV4Base = linkonce_odr unnamed_addr constant [4 x i8*] [i8* null, i8* bitcast ({ i8*, i8* }* @_ZTI4Base to i8*), i8* bitcast (void (%class.Base*)* @_ZN4BaseD1Ev to i8*), i8* bitcast (void (%class.Base*)* @_ZN4BaseD0Ev to i8*)]
- at _ZTVN10__cxxabiv117__class_type_infoE = external global i8*
+ at _ZTV4Base = linkonce_odr unnamed_addr constant [4 x ptr] [ptr null, ptr @_ZTI4Base, ptr @_ZN4BaseD1Ev, ptr @_ZN4BaseD0Ev]
+ at _ZTVN10__cxxabiv117__class_type_infoE = external global ptr
@_ZTS4Base = linkonce_odr constant [6 x i8] c"4Base\00"
- at _ZTI4Base = linkonce_odr unnamed_addr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv117__class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([6 x i8], [6 x i8]* @_ZTS4Base, i32 0, i32 0) }
+ at _ZTI4Base = linkonce_odr unnamed_addr constant { ptr, ptr } { ptr getelementptr inbounds (ptr, ptr @_ZTVN10__cxxabiv117__class_type_infoE, i64 2), ptr @_ZTS4Base }
define i32 @main() uwtable ssp {
entry:
%retval = alloca i32, align 4
%b = alloca %class.Base, align 8
%cleanup.dest.slot = alloca i32
- store i32 0, i32* %retval
- call void @_ZN4BaseC1Ev(%class.Base* %b)
- store i32 0, i32* %retval
- store i32 1, i32* %cleanup.dest.slot
- call void @_ZN4BaseD1Ev(%class.Base* %b)
- %0 = load i32, i32* %retval
+ store i32 0, ptr %retval
+ call void @_ZN4BaseC1Ev(ptr %b)
+ store i32 0, ptr %retval
+ store i32 1, ptr %cleanup.dest.slot
+ call void @_ZN4BaseD1Ev(ptr %b)
+ %0 = load i32, ptr %retval
ret i32 %0
}
-define linkonce_odr void @_ZN4BaseC1Ev(%class.Base* %this) unnamed_addr uwtable ssp align 2 {
+define linkonce_odr void @_ZN4BaseC1Ev(ptr %this) unnamed_addr uwtable ssp align 2 {
entry:
- %this.addr = alloca %class.Base*, align 8
- store %class.Base* %this, %class.Base** %this.addr, align 8
- %this1 = load %class.Base*, %class.Base** %this.addr
- call void @_ZN4BaseC2Ev(%class.Base* %this1)
+ %this.addr = alloca ptr, align 8
+ store ptr %this, ptr %this.addr, align 8
+ %this1 = load ptr, ptr %this.addr
+ call void @_ZN4BaseC2Ev(ptr %this1)
ret void
}
-define linkonce_odr void @_ZN4BaseD1Ev(%class.Base* %this) unnamed_addr uwtable ssp align 2 {
+define linkonce_odr void @_ZN4BaseD1Ev(ptr %this) unnamed_addr uwtable ssp align 2 {
entry:
- %this.addr = alloca %class.Base*, align 8
- store %class.Base* %this, %class.Base** %this.addr, align 8
- %this1 = load %class.Base*, %class.Base** %this.addr
- call void @_ZN4BaseD2Ev(%class.Base* %this1)
+ %this.addr = alloca ptr, align 8
+ store ptr %this, ptr %this.addr, align 8
+ %this1 = load ptr, ptr %this.addr
+ call void @_ZN4BaseD2Ev(ptr %this1)
ret void
}
-define linkonce_odr void @_ZN4BaseD2Ev(%class.Base* %this) unnamed_addr nounwind uwtable ssp align 2 {
+define linkonce_odr void @_ZN4BaseD2Ev(ptr %this) unnamed_addr nounwind uwtable ssp align 2 {
entry:
- %this.addr = alloca %class.Base*, align 8
- store %class.Base* %this, %class.Base** %this.addr, align 8
- %this1 = load %class.Base*, %class.Base** %this.addr
+ %this.addr = alloca ptr, align 8
+ store ptr %this, ptr %this.addr, align 8
+ %this1 = load ptr, ptr %this.addr
ret void
}
-define linkonce_odr void @_ZN4BaseC2Ev(%class.Base* %this) unnamed_addr nounwind uwtable ssp align 2 {
+define linkonce_odr void @_ZN4BaseC2Ev(ptr %this) unnamed_addr nounwind uwtable ssp align 2 {
entry:
- %this.addr = alloca %class.Base*, align 8
- store %class.Base* %this, %class.Base** %this.addr, align 8
- %this1 = load %class.Base*, %class.Base** %this.addr
- %0 = bitcast %class.Base* %this1 to i8***
- store i8** getelementptr inbounds ([4 x i8*], [4 x i8*]* @_ZTV4Base, i64 0, i64 2), i8*** %0
+ %this.addr = alloca ptr, align 8
+ store ptr %this, ptr %this.addr, align 8
+ %this1 = load ptr, ptr %this.addr
+ store ptr getelementptr inbounds ([4 x ptr], ptr @_ZTV4Base, i64 0, i64 2), ptr %this1
ret void
}
-define linkonce_odr void @_ZN4BaseD0Ev(%class.Base* %this) unnamed_addr uwtable ssp align 2 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+define linkonce_odr void @_ZN4BaseD0Ev(ptr %this) unnamed_addr uwtable ssp align 2 personality ptr @__gxx_personality_v0 {
entry:
- %this.addr = alloca %class.Base*, align 8
- %exn.slot = alloca i8*
+ %this.addr = alloca ptr, align 8
+ %exn.slot = alloca ptr
%ehselector.slot = alloca i32
- store %class.Base* %this, %class.Base** %this.addr, align 8
- %this1 = load %class.Base*, %class.Base** %this.addr
- invoke void @_ZN4BaseD1Ev(%class.Base* %this1)
+ store ptr %this, ptr %this.addr, align 8
+ %this1 = load ptr, ptr %this.addr
+ invoke void @_ZN4BaseD1Ev(ptr %this1)
to label %invoke.cont unwind label %lpad
invoke.cont: ; preds = %entry
- %0 = bitcast %class.Base* %this1 to i8*
- call void @_ZdlPv(i8* %0) nounwind
+ call void @_ZdlPv(ptr %this1) nounwind
ret void
lpad: ; preds = %entry
- %1 = landingpad { i8*, i32 }
+ %0 = landingpad { ptr, i32 }
cleanup
- %2 = extractvalue { i8*, i32 } %1, 0
- store i8* %2, i8** %exn.slot
- %3 = extractvalue { i8*, i32 } %1, 1
- store i32 %3, i32* %ehselector.slot
- %4 = bitcast %class.Base* %this1 to i8*
- call void @_ZdlPv(i8* %4) nounwind
+ %1 = extractvalue { ptr, i32 } %0, 0
+ store ptr %1, ptr %exn.slot
+ %2 = extractvalue { ptr, i32 } %0, 1
+ store i32 %2, ptr %ehselector.slot
+ call void @_ZdlPv(ptr %this1) nounwind
br label %eh.resume
eh.resume: ; preds = %lpad
- %exn = load i8*, i8** %exn.slot
- %sel = load i32, i32* %ehselector.slot
- %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn, 0
- %lpad.val2 = insertvalue { i8*, i32 } %lpad.val, i32 %sel, 1
- resume { i8*, i32 } %lpad.val2
+ %exn = load ptr, ptr %exn.slot
+ %sel = load i32, ptr %ehselector.slot
+ %lpad.val = insertvalue { ptr, i32 } undef, ptr %exn, 0
+ %lpad.val2 = insertvalue { ptr, i32 } %lpad.val, i32 %sel, 1
+ resume { ptr, i32 } %lpad.val2
}
declare i32 @__gxx_personality_v0(...)
-declare void @_ZdlPv(i8*) nounwind
+declare void @_ZdlPv(ptr) nounwind
diff --git a/llvm/test/Transforms/PhaseOrdering/globalaa-retained.ll b/llvm/test/Transforms/PhaseOrdering/globalaa-retained.ll
index 7cb34673f6069..2139542c3d3bc 100644
--- a/llvm/test/Transforms/PhaseOrdering/globalaa-retained.ll
+++ b/llvm/test/Transforms/PhaseOrdering/globalaa-retained.ll
@@ -3,7 +3,7 @@ target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
@v = internal unnamed_addr global i32 0, align 4
- at p = common global i32* null, align 8
+ at p = common global ptr null, align 8
; This test checks that a number of loads and stores are eliminated,
@@ -39,14 +39,14 @@ entry:
; Function Attrs: norecurse nounwind
define void @f(i32 %n) {
entry:
- %0 = load i32, i32* @v, align 4
+ %0 = load i32, ptr @v, align 4
%inc = add nsw i32 %0, 1
- store i32 %inc, i32* @v, align 4
- %1 = load i32*, i32** @p, align 8
- store i32 %n, i32* %1, align 4
- %2 = load i32, i32* @v, align 4
+ store i32 %inc, ptr @v, align 4
+ %1 = load ptr, ptr @p, align 8
+ store i32 %n, ptr %1, align 4
+ %2 = load i32, ptr @v, align 4
%inc1 = add nsw i32 %2, 1
- store i32 %inc1, i32* @v, align 4
+ store i32 %inc1, ptr @v, align 4
ret void
}
@@ -54,10 +54,10 @@ entry:
; which should be prove that globalsAA survives until the optimization
; that can use it to optimize away the duplicate load/stores on
; variable v.
-; CHECK: load i32, i32* @v, align 4
-; CHECK: store i32 {{.*}}, i32* @v, align 4
-; CHECK-NOT: load i32, i32* @v, align 4
-; CHECK-NOT: store i32 {{.*}}, i32* @v, align 4
+; CHECK: load i32, ptr @v, align 4
+; CHECK: store i32 {{.*}}, ptr @v, align 4
+; CHECK-NOT: load i32, ptr @v, align 4
+; CHECK-NOT: store i32 {{.*}}, ptr @v, align 4
; Same as @bar above, in case the functions are processed in reverse order.
define void @bar2() {
diff --git a/llvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll b/llvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll
index f764a59dd8a2f..7fde8ef2914a8 100644
--- a/llvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll
+++ b/llvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll
@@ -9,74 +9,74 @@ target datalayout = "e-p:64:64-p5:32:32-A5"
; heuristics, which are affected by the additional instructions of the
; alignment assumption.
-define internal i1 @callee1(i1 %c, i64* align 8 %ptr) {
- store volatile i64 0, i64* %ptr
+define internal i1 @callee1(i1 %c, ptr align 8 %ptr) {
+ store volatile i64 0, ptr %ptr
ret i1 %c
}
-define void @caller1(i1 %c, i64* align 1 %ptr) {
+define void @caller1(i1 %c, ptr align 1 %ptr) {
; ASSUMPTIONS-OFF-LABEL: @caller1(
; ASSUMPTIONS-OFF-NEXT: br i1 [[C:%.*]], label [[COMMON_RET:%.*]], label [[FALSE2:%.*]]
; ASSUMPTIONS-OFF: common.ret:
; ASSUMPTIONS-OFF-NEXT: [[DOTSINK:%.*]] = phi i64 [ 3, [[FALSE2]] ], [ 2, [[TMP0:%.*]] ]
-; ASSUMPTIONS-OFF-NEXT: store volatile i64 0, i64* [[PTR:%.*]], align 8
-; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
-; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
-; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
-; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
-; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
-; ASSUMPTIONS-OFF-NEXT: store volatile i64 [[DOTSINK]], i64* [[PTR]], align 4
+; ASSUMPTIONS-OFF-NEXT: store volatile i64 0, ptr [[PTR:%.*]], align 8
+; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, ptr [[PTR]], align 4
+; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, ptr [[PTR]], align 4
+; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, ptr [[PTR]], align 4
+; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, ptr [[PTR]], align 4
+; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, ptr [[PTR]], align 4
+; ASSUMPTIONS-OFF-NEXT: store volatile i64 [[DOTSINK]], ptr [[PTR]], align 4
; ASSUMPTIONS-OFF-NEXT: ret void
; ASSUMPTIONS-OFF: false2:
-; ASSUMPTIONS-OFF-NEXT: store volatile i64 1, i64* [[PTR]], align 4
+; ASSUMPTIONS-OFF-NEXT: store volatile i64 1, ptr [[PTR]], align 4
; ASSUMPTIONS-OFF-NEXT: br label [[COMMON_RET]]
;
; ASSUMPTIONS-ON-LABEL: @caller1(
; ASSUMPTIONS-ON-NEXT: br i1 [[C:%.*]], label [[COMMON_RET:%.*]], label [[FALSE2:%.*]]
; ASSUMPTIONS-ON: common.ret:
; ASSUMPTIONS-ON-NEXT: [[DOTSINK:%.*]] = phi i64 [ 3, [[FALSE2]] ], [ 2, [[TMP0:%.*]] ]
-; ASSUMPTIONS-ON-NEXT: call void @llvm.assume(i1 true) [ "align"(i64* [[PTR:%.*]], i64 8) ]
-; ASSUMPTIONS-ON-NEXT: store volatile i64 0, i64* [[PTR]], align 8
-; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
-; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
-; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
-; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
-; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
-; ASSUMPTIONS-ON-NEXT: store volatile i64 [[DOTSINK]], i64* [[PTR]], align 8
+; ASSUMPTIONS-ON-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[PTR:%.*]], i64 8) ]
+; ASSUMPTIONS-ON-NEXT: store volatile i64 0, ptr [[PTR]], align 8
+; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, ptr [[PTR]], align 8
+; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, ptr [[PTR]], align 8
+; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, ptr [[PTR]], align 8
+; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, ptr [[PTR]], align 8
+; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, ptr [[PTR]], align 8
+; ASSUMPTIONS-ON-NEXT: store volatile i64 [[DOTSINK]], ptr [[PTR]], align 8
; ASSUMPTIONS-ON-NEXT: ret void
; ASSUMPTIONS-ON: false2:
-; ASSUMPTIONS-ON-NEXT: store volatile i64 1, i64* [[PTR]], align 4
+; ASSUMPTIONS-ON-NEXT: store volatile i64 1, ptr [[PTR]], align 4
; ASSUMPTIONS-ON-NEXT: br label [[COMMON_RET]]
;
br i1 %c, label %true1, label %false1
true1:
- %c2 = call i1 @callee1(i1 %c, i64* %ptr)
- store volatile i64 -1, i64* %ptr
- store volatile i64 -1, i64* %ptr
- store volatile i64 -1, i64* %ptr
- store volatile i64 -1, i64* %ptr
- store volatile i64 -1, i64* %ptr
+ %c2 = call i1 @callee1(i1 %c, ptr %ptr)
+ store volatile i64 -1, ptr %ptr
+ store volatile i64 -1, ptr %ptr
+ store volatile i64 -1, ptr %ptr
+ store volatile i64 -1, ptr %ptr
+ store volatile i64 -1, ptr %ptr
br i1 %c2, label %true2, label %false2
false1:
- store volatile i64 1, i64* %ptr
+ store volatile i64 1, ptr %ptr
br label %true1
true2:
- store volatile i64 2, i64* %ptr
+ store volatile i64 2, ptr %ptr
ret void
false2:
- store volatile i64 3, i64* %ptr
+ store volatile i64 3, ptr %ptr
ret void
}
; This test checks that alignment assumptions do not prevent SROA.
; See PR45763.
-define internal void @callee2(i64* noalias sret(i64) align 32 %arg) {
- store i64 0, i64* %arg, align 8
+define internal void @callee2(ptr noalias sret(i64) align 32 %arg) {
+ store i64 0, ptr %arg, align 8
ret void
}
@@ -85,7 +85,7 @@ define amdgpu_kernel void @caller2() {
; CHECK-NEXT: ret void
;
%alloca = alloca i64, align 8, addrspace(5)
- %cast = addrspacecast i64 addrspace(5)* %alloca to i64*
- call void @callee2(i64* sret(i64) align 32 %cast)
+ %cast = addrspacecast ptr addrspace(5) %alloca to ptr
+ call void @callee2(ptr sret(i64) align 32 %cast)
ret void
}
diff --git a/llvm/test/Transforms/PhaseOrdering/instcombine-sroa-inttoptr.ll b/llvm/test/Transforms/PhaseOrdering/instcombine-sroa-inttoptr.ll
index 886bde2686bd9..ba6c36abd24a1 100644
--- a/llvm/test/Transforms/PhaseOrdering/instcombine-sroa-inttoptr.ll
+++ b/llvm/test/Transforms/PhaseOrdering/instcombine-sroa-inttoptr.ll
@@ -45,121 +45,100 @@
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
-%0 = type { i32*, i32, i32, i32 }
+%0 = type { ptr, i32, i32, i32 }
-define dso_local void @_Z3gen1S(%0* noalias sret(%0) align 8 %arg, %0* byval(%0) align 8 %arg1) {
+define dso_local void @_Z3gen1S(ptr noalias sret(%0) align 8 %arg, ptr byval(%0) align 8 %arg1) {
; CHECK-LABEL: @_Z3gen1S(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = getelementptr inbounds [[TMP0:%.*]], %0* [[ARG1:%.*]], i64 0, i32 0
-; CHECK-NEXT: [[I2:%.*]] = load i32*, i32** [[I]], align 8
-; CHECK-NEXT: [[I3:%.*]] = getelementptr inbounds [[TMP0]], %0* [[ARG:%.*]], i64 0, i32 0
-; CHECK-NEXT: store i32* [[I2]], i32** [[I3]], align 8
+; CHECK-NEXT: [[I2:%.*]] = load ptr, ptr [[ARG1:%.*]], align 8
+; CHECK-NEXT: store ptr [[I2]], ptr [[ARG:%.*]], align 8
; CHECK-NEXT: ret void
;
bb:
- %i = getelementptr inbounds %0, %0* %arg1, i32 0, i32 0
- %i2 = load i32*, i32** %i, align 8
- %i3 = getelementptr inbounds %0, %0* %arg, i32 0, i32 0
- store i32* %i2, i32** %i3, align 8
+ %i2 = load ptr, ptr %arg1, align 8
+ store ptr %i2, ptr %arg, align 8
ret void
}
-define dso_local i32* @_Z3foo1S(%0* byval(%0) align 8 %arg) {
+define dso_local ptr @_Z3foo1S(ptr byval(%0) align 8 %arg) {
; CHECK-LABEL: @_Z3foo1S(
; CHECK-NEXT: bb:
; CHECK-NEXT: [[I2:%.*]] = alloca [[TMP0:%.*]], align 8
-; CHECK-NEXT: [[I1_SROA_0_0_I5_SROA_IDX:%.*]] = getelementptr inbounds [[TMP0]], %0* [[ARG:%.*]], i64 0, i32 0
-; CHECK-NEXT: [[I1_SROA_0_0_COPYLOAD:%.*]] = load i32*, i32** [[I1_SROA_0_0_I5_SROA_IDX]], align 8
-; CHECK-NEXT: [[I_SROA_0_0_I6_SROA_IDX:%.*]] = getelementptr inbounds [[TMP0]], %0* [[I2]], i64 0, i32 0
-; CHECK-NEXT: store i32* [[I1_SROA_0_0_COPYLOAD]], i32** [[I_SROA_0_0_I6_SROA_IDX]], align 8
-; CHECK-NEXT: tail call void @_Z7escape01S(%0* nonnull byval([[TMP0]]) align 8 [[I2]])
-; CHECK-NEXT: ret i32* [[I1_SROA_0_0_COPYLOAD]]
+; CHECK-NEXT: [[I1_SROA_0_0_COPYLOAD:%.*]] = load ptr, ptr [[ARG:%.*]], align 8
+; CHECK-NEXT: store ptr [[I1_SROA_0_0_COPYLOAD]], ptr [[I2]], align 8
+; CHECK-NEXT: tail call void @_Z7escape01S(ptr nonnull byval([[TMP0]]) align 8 [[I2]])
+; CHECK-NEXT: ret ptr [[I1_SROA_0_0_COPYLOAD]]
;
bb:
%i = alloca %0, align 8
%i1 = alloca %0, align 8
%i2 = alloca %0, align 8
- %i3 = bitcast %0* %i to i8*
- call void @llvm.lifetime.start.p0i8(i64 24, i8* %i3)
- %i4 = bitcast %0* %i1 to i8*
- %i5 = bitcast %0* %arg to i8*
- call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %i4, i8* align 8 %i5, i64 24, i1 false)
- call void @_Z3gen1S(%0* sret(%0) align 8 %i, %0* byval(%0) align 8 %i1)
- %i6 = bitcast %0* %i2 to i8*
- %i7 = bitcast %0* %i to i8*
- call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %i6, i8* align 8 %i7, i64 24, i1 false)
- call void @_Z7escape01S(%0* byval(%0) align 8 %i2)
- %i8 = getelementptr inbounds %0, %0* %i, i32 0, i32 0
- %i9 = load i32*, i32** %i8, align 8
- %i10 = bitcast %0* %i to i8*
- call void @llvm.lifetime.end.p0i8(i64 24, i8* %i10)
- ret i32* %i9
+ call void @llvm.lifetime.start.p0(i64 24, ptr %i)
+ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %i1, ptr align 8 %arg, i64 24, i1 false)
+ call void @_Z3gen1S(ptr sret(%0) align 8 %i, ptr byval(%0) align 8 %i1)
+ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %i2, ptr align 8 %i, i64 24, i1 false)
+ call void @_Z7escape01S(ptr byval(%0) align 8 %i2)
+ %i9 = load ptr, ptr %i, align 8
+ call void @llvm.lifetime.end.p0(i64 24, ptr %i)
+ ret ptr %i9
}
-declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
-declare void @llvm.memcpy.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64, i1 immarg)
+declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg)
-declare dso_local void @_Z7escape01S(%0* byval(%0) align 8)
+declare dso_local void @_Z7escape01S(ptr byval(%0) align 8)
-declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)
-define dso_local i32* @_Z3bar1S(%0* byval(%0) align 8 %arg) {
+define dso_local ptr @_Z3bar1S(ptr byval(%0) align 8 %arg) {
; CHECK-LABEL: @_Z3bar1S(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I1_SROA_0_0_I4_SROA_IDX:%.*]] = getelementptr inbounds [[TMP0:%.*]], %0* [[ARG:%.*]], i64 0, i32 0
-; CHECK-NEXT: [[I1_SROA_0_0_COPYLOAD:%.*]] = load i32*, i32** [[I1_SROA_0_0_I4_SROA_IDX]], align 8
+; CHECK-NEXT: [[I1_SROA_0_0_COPYLOAD:%.*]] = load ptr, ptr [[ARG:%.*]], align 8
; CHECK-NEXT: [[I5:%.*]] = tail call i32 @_Z4condv()
; CHECK-NEXT: [[I6_NOT:%.*]] = icmp eq i32 [[I5]], 0
; CHECK-NEXT: br i1 [[I6_NOT]], label [[BB10:%.*]], label [[BB7:%.*]]
; CHECK: bb7:
; CHECK-NEXT: tail call void @_Z5sync0v()
-; CHECK-NEXT: tail call void @_Z7escape0Pi(i32* [[I1_SROA_0_0_COPYLOAD]])
+; CHECK-NEXT: tail call void @_Z7escape0Pi(ptr [[I1_SROA_0_0_COPYLOAD]])
; CHECK-NEXT: br label [[BB13:%.*]]
; CHECK: bb10:
; CHECK-NEXT: tail call void @_Z5sync1v()
-; CHECK-NEXT: tail call void @_Z7escape1Pi(i32* [[I1_SROA_0_0_COPYLOAD]])
+; CHECK-NEXT: tail call void @_Z7escape1Pi(ptr [[I1_SROA_0_0_COPYLOAD]])
; CHECK-NEXT: br label [[BB13]]
; CHECK: bb13:
-; CHECK-NEXT: ret i32* [[I1_SROA_0_0_COPYLOAD]]
+; CHECK-NEXT: ret ptr [[I1_SROA_0_0_COPYLOAD]]
;
bb:
%i = alloca %0, align 8
%i1 = alloca %0, align 8
- %i2 = bitcast %0* %i to i8*
- call void @llvm.lifetime.start.p0i8(i64 24, i8* %i2)
- %i3 = bitcast %0* %i1 to i8*
- %i4 = bitcast %0* %arg to i8*
- call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %i3, i8* align 8 %i4, i64 24, i1 false)
- call void @_Z3gen1S(%0* sret(%0) align 8 %i, %0* byval(%0) align 8 %i1)
+ call void @llvm.lifetime.start.p0(i64 24, ptr %i)
+ call void @llvm.memcpy.p0.p0.i64(ptr align 8 %i1, ptr align 8 %arg, i64 24, i1 false)
+ call void @_Z3gen1S(ptr sret(%0) align 8 %i, ptr byval(%0) align 8 %i1)
%i5 = call i32 @_Z4condv()
%i6 = icmp ne i32 %i5, 0
br i1 %i6, label %bb7, label %bb10
bb7:
call void @_Z5sync0v()
- %i8 = getelementptr inbounds %0, %0* %i, i32 0, i32 0
- %i9 = load i32*, i32** %i8, align 8
- call void @_Z7escape0Pi(i32* %i9)
+ %i9 = load ptr, ptr %i, align 8
+ call void @_Z7escape0Pi(ptr %i9)
br label %bb13
bb10:
call void @_Z5sync1v()
- %i11 = getelementptr inbounds %0, %0* %i, i32 0, i32 0
- %i12 = load i32*, i32** %i11, align 8
- call void @_Z7escape1Pi(i32* %i12)
+ %i12 = load ptr, ptr %i, align 8
+ call void @_Z7escape1Pi(ptr %i12)
br label %bb13
bb13:
- %i14 = getelementptr inbounds %0, %0* %i, i32 0, i32 0
- %i15 = load i32*, i32** %i14, align 8
- %i16 = bitcast %0* %i to i8*
- call void @llvm.lifetime.end.p0i8(i64 24, i8* %i16)
- ret i32* %i15
+ %i15 = load ptr, ptr %i, align 8
+ call void @llvm.lifetime.end.p0(i64 24, ptr %i)
+ ret ptr %i15
}
declare dso_local i32 @_Z4condv()
declare dso_local void @_Z5sync0v()
-declare dso_local void @_Z7escape0Pi(i32*)
+declare dso_local void @_Z7escape0Pi(ptr)
declare dso_local void @_Z5sync1v()
-declare dso_local void @_Z7escape1Pi(i32*)
+declare dso_local void @_Z7escape1Pi(ptr)
diff --git a/llvm/test/Transforms/PhaseOrdering/lifetime-sanitizer.ll b/llvm/test/Transforms/PhaseOrdering/lifetime-sanitizer.ll
index f0dea312fd1b6..5f4d389265a86 100644
--- a/llvm/test/Transforms/PhaseOrdering/lifetime-sanitizer.ll
+++ b/llvm/test/Transforms/PhaseOrdering/lifetime-sanitizer.ll
@@ -7,21 +7,21 @@
; RUN: opt < %s -passes='default<O2>' -S | FileCheck %s
; RUN: opt < %s -passes='default<O3>' -S | FileCheck %s
-declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture)
-declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture)
-declare void @foo(i8* nocapture)
+declare void @llvm.lifetime.start.p0(i64, ptr nocapture)
+declare void @llvm.lifetime.end.p0(i64, ptr nocapture)
+declare void @foo(ptr nocapture)
define void @asan() sanitize_address {
entry:
; CHECK-LABEL: @asan(
%text = alloca i8, align 1
- call void @llvm.lifetime.start.p0i8(i64 1, i8* %text)
- call void @llvm.lifetime.end.p0i8(i64 1, i8* %text)
+ call void @llvm.lifetime.start.p0(i64 1, ptr %text)
+ call void @llvm.lifetime.end.p0(i64 1, ptr %text)
; CHECK: call void @llvm.lifetime.start
; CHECK-NEXT: call void @llvm.lifetime.end
- call void @foo(i8* %text) ; Keep alloca alive
+ call void @foo(ptr %text) ; Keep alloca alive
ret void
}
@@ -31,12 +31,12 @@ entry:
; CHECK-LABEL: @hwasan(
%text = alloca i8, align 1
- call void @llvm.lifetime.start.p0i8(i64 1, i8* %text)
- call void @llvm.lifetime.end.p0i8(i64 1, i8* %text)
+ call void @llvm.lifetime.start.p0(i64 1, ptr %text)
+ call void @llvm.lifetime.end.p0(i64 1, ptr %text)
; CHECK: call void @llvm.lifetime.start
; CHECK-NEXT: call void @llvm.lifetime.end
- call void @foo(i8* %text) ; Keep alloca alive
+ call void @foo(ptr %text) ; Keep alloca alive
ret void
}
@@ -46,12 +46,12 @@ entry:
; CHECK-LABEL: @msan(
%text = alloca i8, align 1
- call void @llvm.lifetime.start.p0i8(i64 1, i8* %text)
- call void @llvm.lifetime.end.p0i8(i64 1, i8* %text)
+ call void @llvm.lifetime.start.p0(i64 1, ptr %text)
+ call void @llvm.lifetime.end.p0(i64 1, ptr %text)
; CHECK: call void @llvm.lifetime.start
; CHECK-NEXT: call void @llvm.lifetime.end
- call void @foo(i8* %text) ; Keep alloca alive
+ call void @foo(ptr %text) ; Keep alloca alive
ret void
}
@@ -61,11 +61,11 @@ entry:
; CHECK-LABEL: @no_asan(
%text = alloca i8, align 1
- call void @llvm.lifetime.start.p0i8(i64 1, i8* %text)
- call void @llvm.lifetime.end.p0i8(i64 1, i8* %text)
+ call void @llvm.lifetime.start.p0(i64 1, ptr %text)
+ call void @llvm.lifetime.end.p0(i64 1, ptr %text)
; CHECK-NO: call void @llvm.lifetime
- call void @foo(i8* %text) ; Keep alloca alive
+ call void @foo(ptr %text) ; Keep alloca alive
ret void
}
diff --git a/llvm/test/Transforms/PhaseOrdering/loop-rotation-vs-common-code-hoisting.ll b/llvm/test/Transforms/PhaseOrdering/loop-rotation-vs-common-code-hoisting.ll
index efd617526ef66..b5bba73e05f83 100644
--- a/llvm/test/Transforms/PhaseOrdering/loop-rotation-vs-common-code-hoisting.ll
+++ b/llvm/test/Transforms/PhaseOrdering/loop-rotation-vs-common-code-hoisting.ll
@@ -38,8 +38,8 @@ declare void @f0()
declare void @f1()
declare void @f2()
-declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
-declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)
define void @_Z4loopi(i32 %width) {
; HOIST-LABEL: @_Z4loopi(
@@ -91,8 +91,8 @@ define void @_Z4loopi(i32 %width) {
entry:
%width.addr = alloca i32, align 4
%i = alloca i32, align 4
- store i32 %width, i32* %width.addr, align 4
- %i1 = load i32, i32* %width.addr, align 4
+ store i32 %width, ptr %width.addr, align 4
+ %i1 = load i32, ptr %width.addr, align 4
%cmp = icmp slt i32 %i1, 1
br i1 %cmp, label %if.then, label %if.end
@@ -100,21 +100,19 @@ if.then:
br label %return
if.end:
- %i2 = bitcast i32* %i to i8*
- call void @llvm.lifetime.start.p0i8(i64 4, i8* %i2)
- store i32 0, i32* %i, align 4
+ call void @llvm.lifetime.start.p0(i64 4, ptr %i)
+ store i32 0, ptr %i, align 4
br label %for.cond
for.cond:
- %i3 = load i32, i32* %i, align 4
- %i4 = load i32, i32* %width.addr, align 4
+ %i3 = load i32, ptr %i, align 4
+ %i4 = load i32, ptr %width.addr, align 4
%sub = sub nsw i32 %i4, 1
%cmp1 = icmp slt i32 %i3, %sub
br i1 %cmp1, label %for.body, label %for.cond.cleanup
for.cond.cleanup:
- %i5 = bitcast i32* %i to i8*
- call void @llvm.lifetime.end.p0i8(i64 4, i8* %i5)
+ call void @llvm.lifetime.end.p0(i64 4, ptr %i)
br label %for.end
for.body:
@@ -123,9 +121,9 @@ for.body:
br label %for.inc
for.inc:
- %i6 = load i32, i32* %i, align 4
+ %i6 = load i32, ptr %i, align 4
%inc = add nsw i32 %i6, 1
- store i32 %inc, i32* %i, align 4
+ store i32 %inc, ptr %i, align 4
br label %for.cond
for.end:
diff --git a/llvm/test/Transforms/PhaseOrdering/lto-licm.ll b/llvm/test/Transforms/PhaseOrdering/lto-licm.ll
index f804b1e8c32ff..8c080acaae61c 100644
--- a/llvm/test/Transforms/PhaseOrdering/lto-licm.ll
+++ b/llvm/test/Transforms/PhaseOrdering/lto-licm.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes='lto<O3>' -S < %s | FileCheck %s
-define void @hoist_fdiv(float* %a, float %b) {
+define void @hoist_fdiv(ptr %a, float %b) {
; CHECK-LABEL: @hoist_fdiv(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_COND:%.*]]
@@ -11,10 +11,10 @@ define void @hoist_fdiv(float* %a, float %b) {
; CHECK-NEXT: br i1 [[CMP_NOT]], label [[FOR_END:%.*]], label [[FOR_INC]]
; CHECK: for.inc:
; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[I_0]] to i64
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[A:%.*]], i64 [[IDXPROM]]
-; CHECK-NEXT: [[TMP0:%.*]] = load float, float* [[ARRAYIDX]], align 4
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[IDXPROM]]
+; CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = fdiv fast float [[TMP0]], [[B:%.*]]
-; CHECK-NEXT: store float [[TMP1]], float* [[ARRAYIDX]], align 4
+; CHECK-NEXT: store float [[TMP1]], ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_0]], 1
; CHECK-NEXT: br label [[FOR_COND]]
; CHECK: for.end:
@@ -33,10 +33,10 @@ for.cond.cleanup:
for.body:
%idxprom = sext i32 %i.0 to i64
- %arrayidx = getelementptr inbounds float, float* %a, i64 %idxprom
- %0 = load float, float* %arrayidx, align 4
+ %arrayidx = getelementptr inbounds float, ptr %a, i64 %idxprom
+ %0 = load float, ptr %arrayidx, align 4
%div = fdiv fast float %0, %b
- store float %div, float* %arrayidx, align 4
+ store float %div, ptr %arrayidx, align 4
br label %for.inc
for.inc:
diff --git a/llvm/test/Transforms/PhaseOrdering/openmp-opt-module.ll b/llvm/test/Transforms/PhaseOrdering/openmp-opt-module.ll
index 24272b3aea32c..3014f5bc9921a 100644
--- a/llvm/test/Transforms/PhaseOrdering/openmp-opt-module.ll
+++ b/llvm/test/Transforms/PhaseOrdering/openmp-opt-module.ll
@@ -1,40 +1,38 @@
; RUN: opt -passes='default<O2>' -pass-remarks-missed=openmp-opt < %s 2>&1 | FileCheck %s --check-prefix=MODULE
target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64"
-%struct.ident_t = type { i32, i32, i32, i32, i8* }
+%struct.ident_t = type { i32, i32, i32, i32, ptr }
@.str = private unnamed_addr constant [13 x i8] c"Alloc Shared\00", align 1
- at S = external local_unnamed_addr global i8*
+ at S = external local_unnamed_addr global ptr
; MODULE: remark: openmp_opt_module.c:5:7: Found thread data sharing on the GPU. Expect degraded performance due to data globalization.
define void @foo() {
entry:
- %i = call i32 @__kmpc_target_init(%struct.ident_t* null, i1 false, i1 true, i1 true)
- %x = call i8* @__kmpc_alloc_shared(i64 4), !dbg !10
- %x_on_stack = bitcast i8* %x to i32*
- %0 = bitcast i32* %x_on_stack to i8*
- call void @use(i8* %0)
- call void @__kmpc_free_shared(i8* %x)
- call void @__kmpc_target_deinit(%struct.ident_t* null, i1 false, i1 true)
+ %i = call i32 @__kmpc_target_init(ptr null, i1 false, i1 true, i1 true)
+ %x = call ptr @__kmpc_alloc_shared(i64 4), !dbg !10
+ call void @use(ptr %x)
+ call void @__kmpc_free_shared(ptr %x)
+ call void @__kmpc_target_deinit(ptr null, i1 false, i1 true)
ret void
}
-declare void @use(i8* %0)
+declare void @use(ptr %x)
-define weak i8* @__kmpc_alloc_shared(i64 %DataSize) {
+define weak ptr @__kmpc_alloc_shared(i64 %DataSize) {
entry:
- %call = call i8* @_Z10SafeMallocmPKc(i64 %DataSize, i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i64 0, i64 0)) #11
- ret i8* %call
+ %call = call ptr @_Z10SafeMallocmPKc(i64 %DataSize, ptr @.str) #11
+ ret ptr %call
}
; Function Attrs: convergent nounwind mustprogress
-declare i8* @_Z10SafeMallocmPKc(i64 %size, i8* nocapture readnone %msg)
+declare ptr @_Z10SafeMallocmPKc(i64 %size, ptr nocapture readnone %msg)
-declare void @__kmpc_free_shared(i8*)
-declare i32 @__kmpc_target_init(%struct.ident_t*, i1, i1 %use_generic_state_machine, i1)
-declare void @__kmpc_target_deinit(%struct.ident_t*, i1, i1)
+declare void @__kmpc_free_shared(ptr)
+declare i32 @__kmpc_target_init(ptr, i1, i1 %use_generic_state_machine, i1)
+declare void @__kmpc_target_deinit(ptr, i1, i1)
!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4, !5, !6}
@@ -47,7 +45,7 @@ declare void @__kmpc_target_deinit(%struct.ident_t*, i1, i1)
!4 = !{i32 1, !"wchar_size", i32 4}
!5 = !{i32 7, !"openmp", i32 50}
!6 = !{i32 7, !"openmp-device", i32 50}
-!7 = !{void ()* @foo, !"kernel", i32 1}
+!7 = !{ptr @foo, !"kernel", i32 1}
!8 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !9, scopeLine: 1, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2)
!9 = !DISubroutineType(types: !2)
!10 = !DILocation(line: 5, column: 7, scope: !8)
diff --git a/llvm/test/Transforms/PhaseOrdering/pr32544.ll b/llvm/test/Transforms/PhaseOrdering/pr32544.ll
index d0ade17b0a8e7..186954fd22aaf 100644
--- a/llvm/test/Transforms/PhaseOrdering/pr32544.ll
+++ b/llvm/test/Transforms/PhaseOrdering/pr32544.ll
@@ -2,16 +2,16 @@
; RUN: opt -O3 -S < %s | FileCheck %s
; RUN: opt -passes='default<O3>' -S < %s | FileCheck %s
-define void @foo(i1 %which, i32 %a, i32 %b, i64 *%result) {
+define void @foo(i1 %which, i32 %a, i32 %b, ptr %result) {
; CHECK-LABEL: @foo(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = sub i32 0, [[B:%.*]]
; CHECK-NEXT: [[Z_V_P:%.*]] = select i1 [[WHICH:%.*]], i32 [[B]], i32 [[TMP0]]
; CHECK-NEXT: [[Z_V:%.*]] = add i32 [[Z_V_P]], [[A:%.*]]
; CHECK-NEXT: [[Z:%.*]] = zext i32 [[Z_V]] to i64
-; CHECK-NEXT: [[C:%.*]] = load i64, i64* [[RESULT:%.*]], align 4
+; CHECK-NEXT: [[C:%.*]] = load i64, ptr [[RESULT:%.*]], align 4
; CHECK-NEXT: [[VALUE:%.*]] = add i64 [[C]], [[Z]]
-; CHECK-NEXT: store i64 [[VALUE]], i64* [[RESULT]], align 4
+; CHECK-NEXT: store i64 [[VALUE]], ptr [[RESULT]], align 4
; CHECK-NEXT: ret void
;
entry:
@@ -26,22 +26,22 @@ delay:
final:
%z = phi i64 [ %x2, %entry ], [ %y2, %delay ]
- %c = load i64, i64* %result
+ %c = load i64, ptr %result
%value = add i64 %z, %c
- store i64 %value, i64* %result
+ store i64 %value, ptr %result
ret void
}
-define void @bar(i1 %which, i32 %a, i32 %b, i64 *%result) {
+define void @bar(i1 %which, i32 %a, i32 %b, ptr %result) {
; CHECK-LABEL: @bar(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = sub i32 0, [[B:%.*]]
; CHECK-NEXT: [[SPEC_SELECT_P:%.*]] = select i1 [[WHICH:%.*]], i32 [[B]], i32 [[TMP0]]
; CHECK-NEXT: [[SPEC_SELECT:%.*]] = add i32 [[SPEC_SELECT_P]], [[A:%.*]]
; CHECK-NEXT: [[Z2:%.*]] = zext i32 [[SPEC_SELECT]] to i64
-; CHECK-NEXT: [[C:%.*]] = load i64, i64* [[RESULT:%.*]], align 4
+; CHECK-NEXT: [[C:%.*]] = load i64, ptr [[RESULT:%.*]], align 4
; CHECK-NEXT: [[VALUE:%.*]] = add i64 [[C]], [[Z2]]
-; CHECK-NEXT: store i64 [[VALUE]], i64* [[RESULT]], align 4
+; CHECK-NEXT: store i64 [[VALUE]], ptr [[RESULT]], align 4
; CHECK-NEXT: ret void
;
entry:
@@ -55,22 +55,22 @@ delay:
final:
%z = phi i32 [ %x, %entry ], [ %y, %delay ]
%z2 = zext i32 %z to i64
- %c = load i64, i64* %result
+ %c = load i64, ptr %result
%value = add i64 %z2, %c
- store i64 %value, i64* %result
+ store i64 %value, ptr %result
ret void
}
-define void @foo_opt(i1 %which, i32 %a, i32 %b, i64* nocapture %result) {
+define void @foo_opt(i1 %which, i32 %a, i32 %b, ptr nocapture %result) {
; CHECK-LABEL: @foo_opt(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = sub i32 0, [[B:%.*]]
; CHECK-NEXT: [[Z_V_P:%.*]] = select i1 [[WHICH:%.*]], i32 [[B]], i32 [[TMP0]]
; CHECK-NEXT: [[Z_V:%.*]] = add i32 [[Z_V_P]], [[A:%.*]]
; CHECK-NEXT: [[Z:%.*]] = zext i32 [[Z_V]] to i64
-; CHECK-NEXT: [[C:%.*]] = load i64, i64* [[RESULT:%.*]], align 4
+; CHECK-NEXT: [[C:%.*]] = load i64, ptr [[RESULT:%.*]], align 4
; CHECK-NEXT: [[VALUE:%.*]] = add i64 [[C]], [[Z]]
-; CHECK-NEXT: store i64 [[VALUE]], i64* [[RESULT]], align 4
+; CHECK-NEXT: store i64 [[VALUE]], ptr [[RESULT]], align 4
; CHECK-NEXT: ret void
;
entry:
@@ -78,8 +78,8 @@ entry:
%z.v.p = select i1 %which, i32 %b, i32 %0
%z.v = add i32 %z.v.p, %a
%z = zext i32 %z.v to i64
- %c = load i64, i64* %result, align 4
+ %c = load i64, ptr %result, align 4
%value = add i64 %c, %z
- store i64 %value, i64* %result, align 4
+ store i64 %value, ptr %result, align 4
ret void
}
diff --git a/llvm/test/Transforms/PhaseOrdering/pr36760.ll b/llvm/test/Transforms/PhaseOrdering/pr36760.ll
index 24876c052b49e..ce250ed3a79a3 100644
--- a/llvm/test/Transforms/PhaseOrdering/pr36760.ll
+++ b/llvm/test/Transforms/PhaseOrdering/pr36760.ll
@@ -10,25 +10,25 @@ define i64 @PR36760(i64 %a) {
entry:
%retval = alloca i64, align 8
%a.addr = alloca i64, align 8
- store i64 %a, i64* %a.addr, align 8
- %0 = load i64, i64* %a.addr, align 8
+ store i64 %a, ptr %a.addr, align 8
+ %0 = load i64, ptr %a.addr, align 8
%cmp = icmp slt i64 %0, 0
br i1 %cmp, label %if.then, label %if.end
if.then:
- store i64 0, i64* %retval, align 8
+ store i64 0, ptr %retval, align 8
br label %return
if.end:
- %1 = load i64, i64* %a.addr, align 8
+ %1 = load i64, ptr %a.addr, align 8
%shr = ashr i64 %1, 63
- %2 = load i64, i64* %a.addr, align 8
+ %2 = load i64, ptr %a.addr, align 8
%xor = xor i64 %shr, %2
- store i64 %xor, i64* %retval, align 8
+ store i64 %xor, ptr %retval, align 8
br label %return
return:
- %3 = load i64, i64* %retval, align 8
+ %3 = load i64, ptr %retval, align 8
ret i64 %3
}
@@ -42,24 +42,24 @@ define i64 @PR36760_2(i64 %a) #0 {
entry:
%retval = alloca i64, align 8
%a.addr = alloca i64, align 8
- store i64 %a, i64* %a.addr, align 8
- %0 = load i64, i64* %a.addr, align 8
+ store i64 %a, ptr %a.addr, align 8
+ %0 = load i64, ptr %a.addr, align 8
%cmp = icmp sge i64 %0, 0
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
- store i64 0, i64* %retval, align 8
+ store i64 0, ptr %retval, align 8
br label %return
if.end: ; preds = %entry
- %1 = load i64, i64* %a.addr, align 8
+ %1 = load i64, ptr %a.addr, align 8
%shr = ashr i64 %1, 63
- %2 = load i64, i64* %a.addr, align 8
+ %2 = load i64, ptr %a.addr, align 8
%xor = xor i64 %shr, %2
- store i64 %xor, i64* %retval, align 8
+ store i64 %xor, ptr %retval, align 8
br label %return
return: ; preds = %if.end, %if.then
- %3 = load i64, i64* %retval, align 8
+ %3 = load i64, ptr %retval, align 8
ret i64 %3
}
diff --git a/llvm/test/Transforms/PhaseOrdering/pr39282.ll b/llvm/test/Transforms/PhaseOrdering/pr39282.ll
index c9f72e008331d..62d96ecdd68c2 100644
--- a/llvm/test/Transforms/PhaseOrdering/pr39282.ll
+++ b/llvm/test/Transforms/PhaseOrdering/pr39282.ll
@@ -1,40 +1,40 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes='default<O2>' -S < %s | FileCheck %s
-define void @copy(i32* noalias %to, i32* noalias %from) {
+define void @copy(ptr noalias %to, ptr noalias %from) {
; CHECK-LABEL: @copy(
-; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[FROM:%.*]], align 4
-; CHECK-NEXT: store i32 [[X]], i32* [[TO:%.*]], align 4
+; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[FROM:%.*]], align 4
+; CHECK-NEXT: store i32 [[X]], ptr [[TO:%.*]], align 4
; CHECK-NEXT: ret void
;
- %x = load i32, i32* %from
- store i32 %x, i32* %to
+ %x = load i32, ptr %from
+ store i32 %x, ptr %to
ret void
}
; Consider that %addr1 = %addr2 + 1, in which case %addr2i and %addr1i are
; noalias within one iteration, but may alias across iterations.
-define void @pr39282(i32* %addr1, i32* %addr2) {
+define void @pr39282(ptr %addr1, ptr %addr2) {
; CHECK-LABEL: @pr39282(
; CHECK-NEXT: start:
; CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl
; CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl
-; CHECK-NEXT: [[X_I:%.*]] = load i32, i32* [[ADDR1:%.*]], align 4, !alias.scope !3, !noalias !0
-; CHECK-NEXT: store i32 [[X_I]], i32* [[ADDR2:%.*]], align 4, !alias.scope !0, !noalias !3
-; CHECK-NEXT: [[ADDR1I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR1]], i64 1
-; CHECK-NEXT: [[ADDR2I_1:%.*]] = getelementptr inbounds i32, i32* [[ADDR2]], i64 1
+; CHECK-NEXT: [[X_I:%.*]] = load i32, ptr [[ADDR1:%.*]], align 4, !alias.scope !3, !noalias !0
+; CHECK-NEXT: store i32 [[X_I]], ptr [[ADDR2:%.*]], align 4, !alias.scope !0, !noalias !3
+; CHECK-NEXT: [[ADDR1I_1:%.*]] = getelementptr inbounds i32, ptr [[ADDR1]], i64 1
+; CHECK-NEXT: [[ADDR2I_1:%.*]] = getelementptr inbounds i32, ptr [[ADDR2]], i64 1
; CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl
; CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl
-; CHECK-NEXT: [[X_I_1:%.*]] = load i32, i32* [[ADDR1I_1]], align 4, !alias.scope !7, !noalias !5
-; CHECK-NEXT: store i32 [[X_I_1]], i32* [[ADDR2I_1]], align 4, !alias.scope !5, !noalias !7
+; CHECK-NEXT: [[X_I_1:%.*]] = load i32, ptr [[ADDR1I_1]], align 4, !alias.scope !7, !noalias !5
+; CHECK-NEXT: store i32 [[X_I_1]], ptr [[ADDR2I_1]], align 4, !alias.scope !5, !noalias !7
; CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl
; CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl
-; CHECK-NEXT: [[X_I_2:%.*]] = load i32, i32* [[ADDR1]], align 4, !alias.scope !11, !noalias !9
-; CHECK-NEXT: store i32 [[X_I_2]], i32* [[ADDR2]], align 4, !alias.scope !9, !noalias !11
+; CHECK-NEXT: [[X_I_2:%.*]] = load i32, ptr [[ADDR1]], align 4, !alias.scope !11, !noalias !9
+; CHECK-NEXT: store i32 [[X_I_2]], ptr [[ADDR2]], align 4, !alias.scope !9, !noalias !11
; CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl
; CHECK-NEXT: call void @llvm.experimental.noalias.scope.decl
-; CHECK-NEXT: [[X_I_3:%.*]] = load i32, i32* [[ADDR1I_1]], align 4, !alias.scope !15, !noalias !13
-; CHECK-NEXT: store i32 [[X_I_3]], i32* [[ADDR2I_1]], align 4, !alias.scope !13, !noalias !15
+; CHECK-NEXT: [[X_I_3:%.*]] = load i32, ptr [[ADDR1I_1]], align 4, !alias.scope !15, !noalias !13
+; CHECK-NEXT: store i32 [[X_I_3]], ptr [[ADDR2I_1]], align 4, !alias.scope !13, !noalias !15
; CHECK-NEXT: ret void
;
start:
@@ -43,9 +43,9 @@ start:
body:
%i = phi i32 [ 0, %start ], [ %i.next, %body ]
%j = and i32 %i, 1
- %addr1i = getelementptr inbounds i32, i32* %addr1, i32 %j
- %addr2i = getelementptr inbounds i32, i32* %addr2, i32 %j
- call void @copy(i32* %addr2i, i32* %addr1i)
+ %addr1i = getelementptr inbounds i32, ptr %addr1, i32 %j
+ %addr2i = getelementptr inbounds i32, ptr %addr2, i32 %j
+ call void @copy(ptr %addr2i, ptr %addr1i)
%i.next = add i32 %i, 1
%cmp = icmp slt i32 %i.next, 4
br i1 %cmp, label %body, label %end
diff --git a/llvm/test/Transforms/PhaseOrdering/pr40750.ll b/llvm/test/Transforms/PhaseOrdering/pr40750.ll
index 398f9636fd74d..daca49bf9a0c4 100644
--- a/llvm/test/Transforms/PhaseOrdering/pr40750.ll
+++ b/llvm/test/Transforms/PhaseOrdering/pr40750.ll
@@ -3,19 +3,17 @@
%struct.test = type { i8, [3 x i8] }
-define i32 @get(%struct.test* nocapture readonly %arg) {
+define i32 @get(ptr nocapture readonly %arg) {
; CHECK-LABEL: @get(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I:%.*]] = getelementptr inbounds [[STRUCT_TEST:%.*]], %struct.test* [[ARG:%.*]], i64 0, i32 0
-; CHECK-NEXT: [[I1:%.*]] = load i8, i8* [[I]], align 4
+; CHECK-NEXT: [[I1:%.*]] = load i8, ptr [[ARG:%.*]], align 4
; CHECK-NEXT: [[TMP0:%.*]] = and i8 [[I1]], 3
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i8 [[TMP0]], 0
; CHECK-NEXT: [[I9:%.*]] = zext i1 [[TMP1]] to i32
; CHECK-NEXT: ret i32 [[I9]]
;
bb:
- %i = getelementptr inbounds %struct.test, %struct.test* %arg, i64 0, i32 0
- %i1 = load i8, i8* %i, align 4
+ %i1 = load i8, ptr %arg, align 4
%i2 = and i8 %i1, 1
%i3 = icmp eq i8 %i2, 0
br i1 %i3, label %bb4, label %bb8
diff --git a/llvm/test/Transforms/PhaseOrdering/pr45682.ll b/llvm/test/Transforms/PhaseOrdering/pr45682.ll
index 564f86061034a..22305806a19c1 100644
--- a/llvm/test/Transforms/PhaseOrdering/pr45682.ll
+++ b/llvm/test/Transforms/PhaseOrdering/pr45682.ll
@@ -12,16 +12,16 @@ define void @PR45682(i32 %x, i32 %y) {
entry:
%x.addr = alloca i32, align 4
%y.addr = alloca i32, align 4
- store i32 %x, i32* %x.addr, align 4
- store i32 %y, i32* %y.addr, align 4
- %0 = load i32, i32* %y.addr, align 4
+ store i32 %x, ptr %x.addr, align 4
+ store i32 %y, ptr %y.addr, align 4
+ %0 = load i32, ptr %y.addr, align 4
%cmp = icmp sgt i32 %0, 0
call void @llvm.assume(i1 %cmp)
- %1 = load i32, i32* %y.addr, align 4
- %2 = load i32, i32* %x.addr, align 4
+ %1 = load i32, ptr %y.addr, align 4
+ %2 = load i32, ptr %x.addr, align 4
%add = add nsw i32 %2, %1
- store i32 %add, i32* %x.addr, align 4
- %3 = load i32, i32* %x.addr, align 4
+ store i32 %add, ptr %x.addr, align 4
+ %3 = load i32, ptr %x.addr, align 4
%cmp1 = icmp eq i32 %3, -2147483648
br i1 %cmp1, label %if.then, label %if.end
diff --git a/llvm/test/Transforms/PhaseOrdering/reassociate-after-unroll.ll b/llvm/test/Transforms/PhaseOrdering/reassociate-after-unroll.ll
index e0d2711a684a2..48280505fb0ac 100644
--- a/llvm/test/Transforms/PhaseOrdering/reassociate-after-unroll.ll
+++ b/llvm/test/Transforms/PhaseOrdering/reassociate-after-unroll.ll
@@ -16,37 +16,37 @@ entry:
%k = alloca i32, align 4
%g = alloca i64, align 8
%i = alloca i64, align 8
- store i64 %blah, i64* %blah.addr, align 8
- store i64 %limit, i64* %limit.addr, align 8
- store i32 1, i32* %k, align 4
- store i64 0, i64* %i, align 8
+ store i64 %blah, ptr %blah.addr, align 8
+ store i64 %limit, ptr %limit.addr, align 8
+ store i32 1, ptr %k, align 4
+ store i64 0, ptr %i, align 8
br label %for.cond
for.cond:
- %0 = load i64, i64* %i, align 8
- %1 = load i64, i64* %limit.addr, align 8
+ %0 = load i64, ptr %i, align 8
+ %1 = load i64, ptr %limit.addr, align 8
%cmp = icmp ult i64 %0, %1
br i1 %cmp, label %for.body, label %for.cond.cleanup
for.cond.cleanup:
- %2 = load i64, i64* %g, align 8
+ %2 = load i64, ptr %g, align 8
ret i64 %2
for.body:
- %3 = load i64, i64* %blah.addr, align 8
- %4 = load i32, i32* %k, align 4
+ %3 = load i64, ptr %blah.addr, align 8
+ %4 = load i32, ptr %k, align 4
%conv = zext i32 %4 to i64
%and = and i64 %conv, %3
%conv1 = trunc i64 %and to i32
- store i32 %conv1, i32* %k, align 4
- %5 = load i32, i32* %k, align 4
+ store i32 %conv1, ptr %k, align 4
+ %5 = load i32, ptr %k, align 4
%conv2 = zext i32 %5 to i64
- %6 = load i64, i64* %g, align 8
+ %6 = load i64, ptr %g, align 8
%add = add i64 %6, %conv2
- store i64 %add, i64* %g, align 8
- %7 = load i64, i64* %i, align 8
+ store i64 %add, ptr %g, align 8
+ %7 = load i64, ptr %i, align 8
%inc = add i64 %7, 1
- store i64 %inc, i64* %i, align 8
+ store i64 %inc, ptr %i, align 8
br label %for.cond
}
diff --git a/llvm/test/Transforms/PhaseOrdering/recompute-globalsaa.ll b/llvm/test/Transforms/PhaseOrdering/recompute-globalsaa.ll
index f4290c64a773a..3f5ea81349583 100644
--- a/llvm/test/Transforms/PhaseOrdering/recompute-globalsaa.ll
+++ b/llvm/test/Transforms/PhaseOrdering/recompute-globalsaa.ll
@@ -1,50 +1,44 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes='default<O2>' -S < %s | FileCheck %s
@a = internal global i32 0, align 4
- at c = internal global i32** @b, align 8
- at b = internal global i32* null, align 8
- at e = internal global i32* @d, align 8
+ at c = internal global ptr @b, align 8
+ at b = internal global ptr null, align 8
+ at e = internal global ptr @d, align 8
@d = internal global i32 0, align 4
define i32 @main() {
; CHECK-LABEL: @main(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32*, i32** @e, align 8
-; CHECK-NEXT: store i32 0, i32* [[TMP0]], align 4
-; CHECK-NEXT: store i32* null, i32** @e, align 8
+; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr @e, align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP0]], align 4
+; CHECK-NEXT: store ptr null, ptr @e, align 8
; CHECK-NEXT: ret i32 0
;
entry:
- %h = alloca i32*, align 8
- %i = alloca i32*, align 8
- %j = alloca i32*, align 8
- %0 = bitcast i32** %h to i8*
- store i32* @a, i32** %h, align 8
- %1 = bitcast i32** %i to i8*
- %2 = bitcast i32** %j to i8*
- store i32* @a, i32** %j, align 8
- %3 = load i32*, i32** %j, align 8
- store i32 1, i32* %3, align 4
- store i32* @a, i32** %i, align 8
- %4 = load i32*, i32** %i, align 8
- %5 = load i32**, i32*** @c, align 8
- store i32* %4, i32** %5, align 8
- %6 = load i32*, i32** %h, align 8
- %call = call i32* @bar(i32* %6)
- %7 = bitcast i32** %j to i8*
- %8 = bitcast i32** %i to i8*
- %9 = bitcast i32** %h to i8*
+ %h = alloca ptr, align 8
+ %i = alloca ptr, align 8
+ %j = alloca ptr, align 8
+ store ptr @a, ptr %h, align 8
+ store ptr @a, ptr %j, align 8
+ %0 = load ptr, ptr %j, align 8
+ store i32 1, ptr %0, align 4
+ store ptr @a, ptr %i, align 8
+ %1 = load ptr, ptr %i, align 8
+ %2 = load ptr, ptr @c, align 8
+ store ptr %1, ptr %2, align 8
+ %3 = load ptr, ptr %h, align 8
+ %call = call ptr @bar(ptr %3)
ret i32 0
}
-define internal i32* @bar(i32* %g) {
+define internal ptr @bar(ptr %g) {
entry:
- %g.addr = alloca i32*, align 8
- store i32* %g, i32** %g.addr, align 8
- %0 = load i32*, i32** @e, align 8
- store i32 0, i32* %0, align 4
- %1 = load i32*, i32** %g.addr, align 8
- %2 = load i32, i32* %1, align 4
+ %g.addr = alloca ptr, align 8
+ store ptr %g, ptr %g.addr, align 8
+ %0 = load ptr, ptr @e, align 8
+ store i32 0, ptr %0, align 4
+ %1 = load ptr, ptr %g.addr, align 8
+ %2 = load i32, ptr %1, align 4
%tobool = icmp ne i32 %2, 0
br i1 %tobool, label %if.end, label %if.then
@@ -53,9 +47,9 @@ if.then: ; preds = %entry
br label %if.end
if.end: ; preds = %if.then, %entry
- store i32* null, i32** @e, align 8
- %3 = load i32*, i32** @b, align 8
- ret i32* %3
+ store ptr null, ptr @e, align 8
+ %3 = load ptr, ptr @b, align 8
+ ret ptr %3
}
declare void @foo()
diff --git a/llvm/test/Transforms/PhaseOrdering/scev-custom-dl.ll b/llvm/test/Transforms/PhaseOrdering/scev-custom-dl.ll
index 9f3fadc7650ec..05f0651857f2b 100644
--- a/llvm/test/Transforms/PhaseOrdering/scev-custom-dl.ll
+++ b/llvm/test/Transforms/PhaseOrdering/scev-custom-dl.ll
@@ -11,22 +11,22 @@ target datalayout = "e-m:m-p:40:64:64:32-i32:32-i16:16-i8:8-n32"
; The loop body contains two increments by %div.
; Make sure that 2*%div is recognizable, and not expressed as a bit mask of %d.
; CHECK: --> {%p,+,(8 * (%d /u 4))}
-define void @test1(i32 %d, i32* %p) nounwind uwtable ssp {
+define void @test1(i32 %d, ptr %p) nounwind uwtable ssp {
entry:
%div = udiv i32 %d, 4
br label %for.cond
for.cond: ; preds = %for.inc, %entry
- %p.addr.0 = phi i32* [ %p, %entry ], [ %add.ptr1, %for.inc ]
+ %p.addr.0 = phi ptr [ %p, %entry ], [ %add.ptr1, %for.inc ]
%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
%cmp = icmp ne i32 %i.0, 64
br i1 %cmp, label %for.body, label %for.end
for.body: ; preds = %for.cond
- store i32 0, i32* %p.addr.0, align 4
- %add.ptr = getelementptr inbounds i32, i32* %p.addr.0, i32 %div
- store i32 1, i32* %add.ptr, align 4
- %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 %div
+ store i32 0, ptr %p.addr.0, align 4
+ %add.ptr = getelementptr inbounds i32, ptr %p.addr.0, i32 %div
+ store i32 1, ptr %add.ptr, align 4
+ %add.ptr1 = getelementptr inbounds i32, ptr %add.ptr, i32 %div
br label %for.inc
for.inc: ; preds = %for.body
@@ -40,22 +40,22 @@ for.end: ; preds = %for.cond
; CHECK: test1a
; Same thing as test1, but it is even more tempting to fold 2 * (%d /u 2)
; CHECK: --> {%p,+,(8 * (%d /u 2))}
-define void @test1a(i32 %d, i32* %p) nounwind uwtable ssp {
+define void @test1a(i32 %d, ptr %p) nounwind uwtable ssp {
entry:
%div = udiv i32 %d, 2
br label %for.cond
for.cond: ; preds = %for.inc, %entry
- %p.addr.0 = phi i32* [ %p, %entry ], [ %add.ptr1, %for.inc ]
+ %p.addr.0 = phi ptr [ %p, %entry ], [ %add.ptr1, %for.inc ]
%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
%cmp = icmp ne i32 %i.0, 64
br i1 %cmp, label %for.body, label %for.end
for.body: ; preds = %for.cond
- store i32 0, i32* %p.addr.0, align 4
- %add.ptr = getelementptr inbounds i32, i32* %p.addr.0, i32 %div
- store i32 1, i32* %add.ptr, align 4
- %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 %div
+ store i32 0, ptr %p.addr.0, align 4
+ %add.ptr = getelementptr inbounds i32, ptr %p.addr.0, i32 %div
+ store i32 1, ptr %add.ptr, align 4
+ %add.ptr1 = getelementptr inbounds i32, ptr %add.ptr, i32 %div
br label %for.inc
for.inc: ; preds = %for.body
@@ -66,7 +66,7 @@ for.end: ; preds = %for.cond
ret void
}
- at array = weak global [101 x i32] zeroinitializer, align 32 ; <[100 x i32]*> [#uses=1]
+ at array = weak global [101 x i32] zeroinitializer, align 32 ; <ptr> [#uses=1]
; CHECK: Loop %bb: backedge-taken count is 100
@@ -76,8 +76,8 @@ entry:
bb: ; preds = %bb, %entry
%i.01.0 = phi i32 [ 100, %entry ], [ %tmp4, %bb ] ; <i32> [#uses=2]
- %tmp1 = getelementptr [101 x i32], [101 x i32]* @array, i32 0, i32 %i.01.0 ; <i32*> [#uses=1]
- store i32 %x, i32* %tmp1
+ %tmp1 = getelementptr [101 x i32], ptr @array, i32 0, i32 %i.01.0 ; <ptr> [#uses=1]
+ store i32 %x, ptr %tmp1
%tmp4 = add i32 %i.01.0, -1 ; <i32> [#uses=2]
%tmp7 = icmp sgt i32 %tmp4, -1 ; <i1> [#uses=1]
br i1 %tmp7, label %bb, label %return
@@ -86,17 +86,17 @@ return: ; preds = %bb
ret void
}
-define i32 @test_loop_idiom_recogize(i32 %x, i32 %y, i32* %lam, i32* %alp) nounwind {
+define i32 @test_loop_idiom_recogize(i32 %x, i32 %y, ptr %lam, ptr %alp) nounwind {
bb1.thread:
br label %bb1
bb1: ; preds = %bb1, %bb1.thread
%indvar = phi i32 [ 0, %bb1.thread ], [ %indvar.next, %bb1 ] ; <i32> [#uses=4]
%i.0.reg2mem.0 = sub i32 255, %indvar ; <i32> [#uses=2]
- %0 = getelementptr i32, i32* %alp, i32 %i.0.reg2mem.0 ; <i32*> [#uses=1]
- %1 = load i32, i32* %0, align 4 ; <i32> [#uses=1]
- %2 = getelementptr i32, i32* %lam, i32 %i.0.reg2mem.0 ; <i32*> [#uses=1]
- store i32 %1, i32* %2, align 4
+ %0 = getelementptr i32, ptr %alp, i32 %i.0.reg2mem.0 ; <ptr> [#uses=1]
+ %1 = load i32, ptr %0, align 4 ; <i32> [#uses=1]
+ %2 = getelementptr i32, ptr %lam, i32 %i.0.reg2mem.0 ; <ptr> [#uses=1]
+ store i32 %1, ptr %2, align 4
%3 = sub i32 254, %indvar ; <i32> [#uses=1]
%4 = icmp slt i32 %3, 0 ; <i1> [#uses=1]
%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=1]
@@ -117,18 +117,18 @@ declare void @llvm.experimental.guard(i1, ...)
; CHECK: Loop %loop: Unpredictable constant max backedge-taken count.
define void @test_range_ref1(i8 %t) {
entry:
- %t.ptr = inttoptr i8 %t to i8*
- %p.42 = inttoptr i8 42 to i8*
- %cmp1 = icmp slt i8* %t.ptr, %p.42
+ %t.ptr = inttoptr i8 %t to ptr
+ %p.42 = inttoptr i8 42 to ptr
+ %cmp1 = icmp slt ptr %t.ptr, %p.42
call void(i1, ...) @llvm.experimental.guard(i1 %cmp1) [ "deopt"() ]
br label %loop
loop:
- %idx = phi i8* [ %t.ptr, %entry ], [ %snext, %loop ]
- %snext = getelementptr inbounds i8, i8* %idx, i64 1
- %c = icmp slt i8* %idx, %p.42
+ %idx = phi ptr [ %t.ptr, %entry ], [ %snext, %loop ]
+ %snext = getelementptr inbounds i8, ptr %idx, i64 1
+ %c = icmp slt ptr %idx, %p.42
call void @use(i1 %c)
- %be = icmp slt i8* %snext, %p.42
+ %be = icmp slt ptr %snext, %p.42
br i1 %be, label %loop, label %exit
exit:
diff --git a/llvm/test/Transforms/PhaseOrdering/scev.ll b/llvm/test/Transforms/PhaseOrdering/scev.ll
index 3a789cff7f4ca..e259bc202ce31 100644
--- a/llvm/test/Transforms/PhaseOrdering/scev.ll
+++ b/llvm/test/Transforms/PhaseOrdering/scev.ll
@@ -8,22 +8,22 @@
; The loop body contains two increments by %div.
; Make sure that 2*%div is recognizable, and not expressed as a bit mask of %d.
; CHECK: --> {%p,+,(8 * (%d /u 4))}
-define void @test1(i64 %d, i32* %p) nounwind uwtable ssp {
+define void @test1(i64 %d, ptr %p) nounwind uwtable ssp {
entry:
%div = udiv i64 %d, 4
br label %for.cond
for.cond: ; preds = %for.inc, %entry
- %p.addr.0 = phi i32* [ %p, %entry ], [ %add.ptr1, %for.inc ]
+ %p.addr.0 = phi ptr [ %p, %entry ], [ %add.ptr1, %for.inc ]
%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
%cmp = icmp ne i32 %i.0, 64
br i1 %cmp, label %for.body, label %for.end
for.body: ; preds = %for.cond
- store i32 0, i32* %p.addr.0, align 4
- %add.ptr = getelementptr inbounds i32, i32* %p.addr.0, i64 %div
- store i32 1, i32* %add.ptr, align 4
- %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i64 %div
+ store i32 0, ptr %p.addr.0, align 4
+ %add.ptr = getelementptr inbounds i32, ptr %p.addr.0, i64 %div
+ store i32 1, ptr %add.ptr, align 4
+ %add.ptr1 = getelementptr inbounds i32, ptr %add.ptr, i64 %div
br label %for.inc
for.inc: ; preds = %for.body
@@ -37,22 +37,22 @@ for.end: ; preds = %for.cond
; CHECK: test1a
; Same thing as test1, but it is even more tempting to fold 2 * (%d /u 2)
; CHECK: --> {%p,+,(8 * (%d /u 2))}
-define void @test1a(i64 %d, i32* %p) nounwind uwtable ssp {
+define void @test1a(i64 %d, ptr %p) nounwind uwtable ssp {
entry:
%div = udiv i64 %d, 2
br label %for.cond
for.cond: ; preds = %for.inc, %entry
- %p.addr.0 = phi i32* [ %p, %entry ], [ %add.ptr1, %for.inc ]
+ %p.addr.0 = phi ptr [ %p, %entry ], [ %add.ptr1, %for.inc ]
%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
%cmp = icmp ne i32 %i.0, 64
br i1 %cmp, label %for.body, label %for.end
for.body: ; preds = %for.cond
- store i32 0, i32* %p.addr.0, align 4
- %add.ptr = getelementptr inbounds i32, i32* %p.addr.0, i64 %div
- store i32 1, i32* %add.ptr, align 4
- %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i64 %div
+ store i32 0, ptr %p.addr.0, align 4
+ %add.ptr = getelementptr inbounds i32, ptr %p.addr.0, i64 %div
+ store i32 1, ptr %add.ptr, align 4
+ %add.ptr1 = getelementptr inbounds i32, ptr %add.ptr, i64 %div
br label %for.inc
for.inc: ; preds = %for.body
diff --git a/llvm/test/Transforms/PhaseOrdering/simplifycfg-options.ll b/llvm/test/Transforms/PhaseOrdering/simplifycfg-options.ll
index 062b343c3717e..9231726b0a7bd 100644
--- a/llvm/test/Transforms/PhaseOrdering/simplifycfg-options.ll
+++ b/llvm/test/Transforms/PhaseOrdering/simplifycfg-options.ll
@@ -5,25 +5,25 @@
; Don't simplify unconditional branches from empty blocks in simplifyCFG
; until late in the pipeline because it can destroy canonical loop structure.
-define i1 @PR33605(i32 %a, i32 %b, i32* %c) {
+define i1 @PR33605(i32 %a, i32 %b, ptr %c) {
; CHECK-LABEL: @PR33605(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[OR:%.*]] = or i32 [[B:%.*]], [[A:%.*]]
-; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[C:%.*]], i64 1
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[C:%.*]], i64 1
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[OR]], [[TMP0]]
; CHECK-NEXT: br i1 [[CMP]], label [[IF_END:%.*]], label [[IF_THEN:%.*]]
; CHECK: if.then:
-; CHECK-NEXT: store i32 [[OR]], i32* [[ARRAYIDX]], align 4
+; CHECK-NEXT: store i32 [[OR]], ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: tail call void @foo()
; CHECK-NEXT: br label [[IF_END]]
; CHECK: if.end:
; CHECK-NEXT: [[TMP1:%.*]] = xor i1 [[CMP]], true
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[C]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[C]], align 4
; CHECK-NEXT: [[CMP_1:%.*]] = icmp eq i32 [[OR]], [[TMP2]]
; CHECK-NEXT: br i1 [[CMP_1]], label [[IF_END_1:%.*]], label [[IF_THEN_1:%.*]]
; CHECK: if.then.1:
-; CHECK-NEXT: store i32 [[OR]], i32* [[C]], align 4
+; CHECK-NEXT: store i32 [[OR]], ptr [[C]], align 4
; CHECK-NEXT: tail call void @foo()
; CHECK-NEXT: br label [[IF_END_1]]
; CHECK: if.end.1:
@@ -47,13 +47,13 @@ for.cond.cleanup:
for.body:
%or = or i32 %a, %b
%idxprom = sext i32 %dec to i64
- %arrayidx = getelementptr inbounds i32, i32* %c, i64 %idxprom
- %0 = load i32, i32* %arrayidx, align 4
+ %arrayidx = getelementptr inbounds i32, ptr %c, i64 %idxprom
+ %0 = load i32, ptr %arrayidx, align 4
%cmp = icmp eq i32 %or, %0
br i1 %cmp, label %if.end, label %if.then
if.then:
- store i32 %or, i32* %arrayidx, align 4
+ store i32 %or, ptr %arrayidx, align 4
call void @foo()
br label %if.end
@@ -68,33 +68,33 @@ declare void @foo()
; We should have a select of doubles, not a select of double pointers.
; SimplifyCFG should not flatten this before early-cse has a chance to eliminate redundant ops.
-define double @max_of_loads(double* %x, double* %y, i64 %i) {
+define double @max_of_loads(ptr %x, ptr %y, i64 %i) {
; CHECK-LABEL: @max_of_loads(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[XI_PTR:%.*]] = getelementptr double, double* [[X:%.*]], i64 [[I:%.*]]
-; CHECK-NEXT: [[YI_PTR:%.*]] = getelementptr double, double* [[Y:%.*]], i64 [[I]]
-; CHECK-NEXT: [[XI:%.*]] = load double, double* [[XI_PTR]], align 8
-; CHECK-NEXT: [[YI:%.*]] = load double, double* [[YI_PTR]], align 8
+; CHECK-NEXT: [[XI_PTR:%.*]] = getelementptr double, ptr [[X:%.*]], i64 [[I:%.*]]
+; CHECK-NEXT: [[YI_PTR:%.*]] = getelementptr double, ptr [[Y:%.*]], i64 [[I]]
+; CHECK-NEXT: [[XI:%.*]] = load double, ptr [[XI_PTR]], align 8
+; CHECK-NEXT: [[YI:%.*]] = load double, ptr [[YI_PTR]], align 8
; CHECK-NEXT: [[CMP:%.*]] = fcmp ogt double [[XI]], [[YI]]
; CHECK-NEXT: [[XI_YI:%.*]] = select i1 [[CMP]], double [[XI]], double [[YI]]
; CHECK-NEXT: ret double [[XI_YI]]
;
entry:
- %xi_ptr = getelementptr double, double* %x, i64 %i
- %yi_ptr = getelementptr double, double* %y, i64 %i
- %xi = load double, double* %xi_ptr
- %yi = load double, double* %yi_ptr
+ %xi_ptr = getelementptr double, ptr %x, i64 %i
+ %yi_ptr = getelementptr double, ptr %y, i64 %i
+ %xi = load double, ptr %xi_ptr
+ %yi = load double, ptr %yi_ptr
%cmp = fcmp ogt double %xi, %yi
br i1 %cmp, label %if, label %else
if:
- %xi_ptr_again = getelementptr double, double* %x, i64 %i
- %xi_again = load double, double* %xi_ptr_again
+ %xi_ptr_again = getelementptr double, ptr %x, i64 %i
+ %xi_again = load double, ptr %xi_ptr_again
br label %end
else:
- %yi_ptr_again = getelementptr double, double* %y, i64 %i
- %yi_again = load double, double* %yi_ptr_again
+ %yi_ptr_again = getelementptr double, ptr %y, i64 %i
+ %yi_again = load double, ptr %yi_ptr_again
br label %end
end:
diff --git a/llvm/test/Transforms/PhaseOrdering/two-shifts-by-sext.ll b/llvm/test/Transforms/PhaseOrdering/two-shifts-by-sext.ll
index d8908118317fb..801150bcc3028 100644
--- a/llvm/test/Transforms/PhaseOrdering/two-shifts-by-sext.ll
+++ b/llvm/test/Transforms/PhaseOrdering/two-shifts-by-sext.ll
@@ -36,13 +36,13 @@ define i32 @two_shifts_by_sext(i32 %val, i8 signext %len) {
;
%val.addr = alloca i32, align 4
%len.addr = alloca i8, align 1
- store i32 %val, i32* %val.addr, align 4
- store i8 %len, i8* %len.addr, align 1
- %val.reloaded = load i32, i32* %val.addr, align 4
- %len.reloaded.0 = load i8, i8* %len.addr, align 1
+ store i32 %val, ptr %val.addr, align 4
+ store i8 %len, ptr %len.addr, align 1
+ %val.reloaded = load i32, ptr %val.addr, align 4
+ %len.reloaded.0 = load i8, ptr %len.addr, align 1
%conv = sext i8 %len.reloaded.0 to i32
%shl = shl i32 %val.reloaded, %conv
- %len.reloaded.1 = load i8, i8* %len.addr, align 1
+ %len.reloaded.1 = load i8, ptr %len.addr, align 1
%conv1 = sext i8 %len.reloaded.1 to i32
%shr = ashr i32 %shl, %conv1
ret i32 %shr
@@ -58,15 +58,15 @@ define i32 @two_shifts_by_same_sext(i32 %val, i8 signext %len) {
%val.addr = alloca i32, align 4
%len.addr = alloca i8, align 1
%wide_len = alloca i32, align 4
- store i32 %val, i32* %val.addr, align 4
- store i8 %len, i8* %len.addr, align 1
- %len.reloaded.0 = load i8, i8* %len.addr, align 1
+ store i32 %val, ptr %val.addr, align 4
+ store i8 %len, ptr %len.addr, align 1
+ %len.reloaded.0 = load i8, ptr %len.addr, align 1
%conv = sext i8 %len.reloaded.0 to i32
- store i32 %conv, i32* %wide_len, align 4
- %val.reloaded = load i32, i32* %val.addr, align 4
- %len.reloaded.1 = load i32, i32* %wide_len, align 4
+ store i32 %conv, ptr %wide_len, align 4
+ %val.reloaded = load i32, ptr %val.addr, align 4
+ %len.reloaded.1 = load i32, ptr %wide_len, align 4
%shl = shl i32 %val.reloaded, %len.reloaded.1
- %len.reloaded.2 = load i32, i32* %wide_len, align 4
+ %len.reloaded.2 = load i32, ptr %wide_len, align 4
%shr = ashr i32 %shl, %len.reloaded.2
ret i32 %shr
}
@@ -81,16 +81,16 @@ define i32 @two_shifts_by_sext_with_extra_use(i32 %val, i8 signext %len) {
;
%val.addr = alloca i32, align 4
%len.addr = alloca i8, align 1
- store i32 %val, i32* %val.addr, align 4
- store i8 %len, i8* %len.addr, align 1
- %len.reloaded.0 = load i8, i8* %len.addr, align 1
+ store i32 %val, ptr %val.addr, align 4
+ store i8 %len, ptr %len.addr, align 1
+ %len.reloaded.0 = load i8, ptr %len.addr, align 1
%conv = sext i8 %len.reloaded.0 to i32
call void @use_int32(i32 %conv)
- %val.reloaded = load i32, i32* %val.addr, align 4
- %len.reloaded.1 = load i8, i8* %len.addr, align 1
+ %val.reloaded = load i32, ptr %val.addr, align 4
+ %len.reloaded.1 = load i8, ptr %len.addr, align 1
%conv1 = sext i8 %len.reloaded.1 to i32
%shl = shl i32 %val.reloaded, %conv1
- %len.reloaded.2 = load i8, i8* %len.addr, align 1
+ %len.reloaded.2 = load i8, ptr %len.addr, align 1
%conv2 = sext i8 %len.reloaded.2 to i32
%shr = ashr i32 %shl, %conv2
ret i32 %shr
@@ -109,17 +109,17 @@ define i32 @two_shifts_by_same_sext_with_extra_use(i32 %val, i8 signext %len) {
%val.addr = alloca i32, align 4
%len.addr = alloca i8, align 1
%wide_len = alloca i32, align 4
- store i32 %val, i32* %val.addr, align 4
- store i8 %len, i8* %len.addr, align 1
- %len.reloaded.0 = load i8, i8* %len.addr, align 1
+ store i32 %val, ptr %val.addr, align 4
+ store i8 %len, ptr %len.addr, align 1
+ %len.reloaded.0 = load i8, ptr %len.addr, align 1
%conv = sext i8 %len.reloaded.0 to i32
- store i32 %conv, i32* %wide_len, align 4
- %val.reloaded = load i32, i32* %wide_len, align 4
+ store i32 %conv, ptr %wide_len, align 4
+ %val.reloaded = load i32, ptr %wide_len, align 4
call void @use_int32(i32 %val.reloaded)
- %len.reloaded.1 = load i32, i32* %val.addr, align 4
- %len.reloaded.2 = load i32, i32* %wide_len, align 4
+ %len.reloaded.1 = load i32, ptr %val.addr, align 4
+ %len.reloaded.2 = load i32, ptr %wide_len, align 4
%shl = shl i32 %len.reloaded.1, %len.reloaded.2
- %wide_len.reloaded = load i32, i32* %wide_len, align 4
+ %wide_len.reloaded = load i32, ptr %wide_len, align 4
%shr = ashr i32 %shl, %wide_len.reloaded
ret i32 %shr
}
diff --git a/llvm/test/Transforms/PhaseOrdering/vector-select.ll b/llvm/test/Transforms/PhaseOrdering/vector-select.ll
index 7f4f7189e8154..1bdd135c4cb21 100644
--- a/llvm/test/Transforms/PhaseOrdering/vector-select.ll
+++ b/llvm/test/Transforms/PhaseOrdering/vector-select.ll
@@ -14,65 +14,46 @@ define <3 x float> @PR52631(<3 x float> %a, <3 x float> %b, <3 x i32> %c) {
%mask = alloca <3 x i32>, align 16
%res = alloca <3 x i32>, align 16
%extractVec = shufflevector <3 x float> %a, <3 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
- %storetmp = bitcast <3 x float>* %a.addr to <4 x float>*
- store <4 x float> %extractVec, <4 x float>* %storetmp, align 16
+ store <4 x float> %extractVec, ptr %a.addr, align 16
%extractVec1 = shufflevector <3 x float> %b, <3 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
- %storetmp2 = bitcast <3 x float>* %b.addr to <4 x float>*
- store <4 x float> %extractVec1, <4 x float>* %storetmp2, align 16
+ store <4 x float> %extractVec1, ptr %b.addr, align 16
%extractVec3 = shufflevector <3 x i32> %c, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
- %storetmp4 = bitcast <3 x i32>* %c.addr to <4 x i32>*
- store <4 x i32> %extractVec3, <4 x i32>* %storetmp4, align 16
- %t0 = bitcast <3 x i32>* %zero to i8*
- call void @llvm.lifetime.start.p0i8(i64 16, i8* %t0) #2
- %storetmp5 = bitcast <3 x i32>* %zero to <4 x i32>*
- store <4 x i32> <i32 0, i32 0, i32 0, i32 undef>, <4 x i32>* %storetmp5, align 16
- %t1 = bitcast <3 x i32>* %mask to i8*
- call void @llvm.lifetime.start.p0i8(i64 16, i8* %t1) #2
- %castToVec4 = bitcast <3 x i32>* %zero to <4 x i32>*
- %loadVec4 = load <4 x i32>, <4 x i32>* %castToVec4, align 16
+ store <4 x i32> %extractVec3, ptr %c.addr, align 16
+ call void @llvm.lifetime.start.p0(i64 16, ptr %zero) #2
+ store <4 x i32> <i32 0, i32 0, i32 0, i32 undef>, ptr %zero, align 16
+ call void @llvm.lifetime.start.p0(i64 16, ptr %mask) #2
+ %loadVec4 = load <4 x i32>, ptr %zero, align 16
%extractVec6 = shufflevector <4 x i32> %loadVec4, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
- %castToVec47 = bitcast <3 x i32>* %c.addr to <4 x i32>*
- %loadVec48 = load <4 x i32>, <4 x i32>* %castToVec47, align 16
+ %loadVec48 = load <4 x i32>, ptr %c.addr, align 16
%extractVec9 = shufflevector <4 x i32> %loadVec48, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
%cmp = icmp sgt <3 x i32> %extractVec6, %extractVec9
%sext = sext <3 x i1> %cmp to <3 x i32>
%extractVec10 = shufflevector <3 x i32> %sext, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
- %storetmp11 = bitcast <3 x i32>* %mask to <4 x i32>*
- store <4 x i32> %extractVec10, <4 x i32>* %storetmp11, align 16
- %t2 = bitcast <3 x i32>* %res to i8*
- call void @llvm.lifetime.start.p0i8(i64 16, i8* %t2) #2
- %castToVec412 = bitcast <3 x i32>* %mask to <4 x i32>*
- %loadVec413 = load <4 x i32>, <4 x i32>* %castToVec412, align 16
+ store <4 x i32> %extractVec10, ptr %mask, align 16
+ call void @llvm.lifetime.start.p0(i64 16, ptr %res) #2
+ %loadVec413 = load <4 x i32>, ptr %mask, align 16
%extractVec14 = shufflevector <4 x i32> %loadVec413, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
- %castToVec415 = bitcast <3 x float>* %b.addr to <4 x float>*
- %loadVec416 = load <4 x float>, <4 x float>* %castToVec415, align 16
+ %loadVec416 = load <4 x float>, ptr %b.addr, align 16
%extractVec17 = shufflevector <4 x float> %loadVec416, <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2>
%astype = bitcast <3 x float> %extractVec17 to <3 x i32>
%and = and <3 x i32> %extractVec14, %astype
%extractVec18 = shufflevector <3 x i32> %and, <3 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
- %storetmp19 = bitcast <3 x i32>* %res to <4 x i32>*
- store <4 x i32> %extractVec18, <4 x i32>* %storetmp19, align 16
- %castToVec420 = bitcast <3 x i32>* %mask to <4 x i32>*
- %loadVec421 = load <4 x i32>, <4 x i32>* %castToVec420, align 16
+ store <4 x i32> %extractVec18, ptr %res, align 16
+ %loadVec421 = load <4 x i32>, ptr %mask, align 16
%extractVec22 = shufflevector <4 x i32> %loadVec421, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
%cmp23 = icmp eq <3 x i32> %extractVec22, zeroinitializer
%sext24 = sext <3 x i1> %cmp23 to <3 x i32>
- %castToVec425 = bitcast <3 x float>* %a.addr to <4 x float>*
- %loadVec426 = load <4 x float>, <4 x float>* %castToVec425, align 16
+ %loadVec426 = load <4 x float>, ptr %a.addr, align 16
%extractVec27 = shufflevector <4 x float> %loadVec426, <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2>
%astype28 = bitcast <3 x float> %extractVec27 to <3 x i32>
%and29 = and <3 x i32> %sext24, %astype28
- %castToVec430 = bitcast <3 x i32>* %res to <4 x i32>*
- %loadVec431 = load <4 x i32>, <4 x i32>* %castToVec430, align 16
+ %loadVec431 = load <4 x i32>, ptr %res, align 16
%extractVec32 = shufflevector <4 x i32> %loadVec431, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
%or = or <3 x i32> %and29, %extractVec32
%astype33 = bitcast <3 x i32> %or to <3 x float>
- %t3 = bitcast <3 x i32>* %res to i8*
- call void @llvm.lifetime.end.p0i8(i64 16, i8* %t3) #2
- %t4 = bitcast <3 x i32>* %mask to i8*
- call void @llvm.lifetime.end.p0i8(i64 16, i8* %t4) #2
- %t5 = bitcast <3 x i32>* %zero to i8*
- call void @llvm.lifetime.end.p0i8(i64 16, i8* %t5) #2
+ call void @llvm.lifetime.end.p0(i64 16, ptr %res) #2
+ call void @llvm.lifetime.end.p0(i64 16, ptr %mask) #2
+ call void @llvm.lifetime.end.p0(i64 16, ptr %zero) #2
ret <3 x float> %astype33
}
@@ -131,5 +112,5 @@ for.end:
ret <4 x i32> %min.addr.0
}
-declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1
-declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1
+declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1
+declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1
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