[PATCH] D138740: [RISCV] Teach getRegAllocationHints about compressible SRAI/SRLI.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 478037.
craig.topper added a comment.

clang-format


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138740/new/

https://reviews.llvm.org/D138740

Files:
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/test/CodeGen/RISCV/aext-to-sext.ll
  llvm/test/CodeGen/RISCV/atomic-signext.ll
  llvm/test/CodeGen/RISCV/calling-conv-half.ll
  llvm/test/CodeGen/RISCV/copysign-casts.ll
  llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
  llvm/test/CodeGen/RISCV/div-pow2.ll
  llvm/test/CodeGen/RISCV/float-arith.ll
  llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
  llvm/test/CodeGen/RISCV/half-arith.ll
  llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll
  llvm/test/CodeGen/RISCV/rv32zbb.ll
  llvm/test/CodeGen/RISCV/rv32zbkb.ll
  llvm/test/CodeGen/RISCV/rv64zbkb.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll
  llvm/test/CodeGen/RISCV/select-constant-xor.ll
  llvm/test/CodeGen/RISCV/select.ll
  llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/RISCV/xaluo.ll

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