[PATCH] D138542: [InstSimplify] Use dominate condtion to simplify instructions
chenglin.bi via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 25 09:03:47 PST 2022
bcl5980 added a comment.
In D138542#3951118 <https://reviews.llvm.org/D138542#3951118>, @spatel wrote:
> I made a small adjustment to pass the MaxRecurse through to div/rem as well.
>
> There doesn't appear to be any real cost even if we include and/or in the opcodes now:
> https://llvm-compile-time-tracker.com/compare.php?from=27b861a1fd271459e8109418f79293732770bc04&to=7b84f6922df17d6609cffa5c6d6d7ea2083341b8&stat=instructions:u
>
> See the pair of commits ending with:
> https://github.com/llvm/llvm-project/commit/7b84f6922df17d6609cffa5c6d6d7ea2083341b8
So how do you think the patch now? Do we need to add `and`/`or` in this patch? Or do we need to find a way to work on CVP/SCCP?
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https://reviews.llvm.org/D138542/new/
https://reviews.llvm.org/D138542
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