[PATCH] D138570: [AArch64] Add patterns for SVE predicated add/sub and mov combine

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added a comment.

In D138570#3949484 <https://reviews.llvm.org/D138570#3949484>, @NicolaLancellotti wrote:

> I addressed the comments, if you agree, I'll proceed to revert the "Canonicalize ZERO_EXTEND to VSELECT" patch and land this patch.

Yes, I'm happy with that.



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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:3134-3136
 } // End HasSVEorSME
 
+let Predicates = [HasSVEorSME] in {
----------------
It looks like you can merge these together.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:3151-3152
+
+  def : Pat<(nxv16i8 (sub ZPR:$op, (sext (nxv16i1 PPR:$pred)))),
+            (SUB_ZPmZ_B PPR:$pred, ZPR:$op, (DUP_ZI_B 255, 0))>;
+  def : Pat<(nxv8i16 (sub ZPR:$op, (sext (nxv8i1 PPR:$pred)))),
----------------
Presumably you'll need `zext` variants of these patterns before reverting you're previous patch?

Perhaps it's worth canonicalising the constant just in case there are multiple instances of these operations.  By which I mean:
```
add ZPR:$op, (sext ($pred)) -> SUB $op, $pred, DUP(1)
add ZPR:$op, (zext ($pred)) -> ADD $op, $pred, DUP(1)
sub ZPR:$op, (sext ($pred)) -> ADD $op, $pred, DUP(1)
sub ZPR:$op, (zext ($pred)) -> SUB $op, $pred, DUP(1)
```



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Comment at: llvm/test/CodeGen/AArch64/predicated-add-sub.ll:17
 ; CHECK-NEXT:    ret
   %v = icmp ugt <vscale x 8 x i8> %a0, %a1
   %extend = zext <vscale x 8 x i1> %v to <vscale x 8 x i8>
----------------
I know these are existing tests but is there a reason we don't just pass `<vscale x 8 x i1> %v` into the function?


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