[PATCH] D137547: [AArch64][SVE] Use PTRUE instruction for get_active_lane_mask intrinsic if the range is appropriate for predicator constant

Paul Walker via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Nov 25 02:46:40 PST 2022


paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:4758-4759
+      unsigned ElementSize = 128 / Op.getValueType().getVectorMinNumElements();
+      unsigned NumActiveElems =
+          Op.getConstantOperandVal(2) - Op.getConstantOperandVal(1);
+      Optional<unsigned> PredPattern =
----------------
dtemirbulatov wrote:
> paulwalker-arm wrote:
> > paulwalker-arm wrote:
> > > This doesn't look correct because `while` can take 64-bit operation. This code can truncate the result in such a way that a ptrue might incorrectly look like a viable replacement.
> > Sorry I meant "while can take 64-bit operands".
> ok, as whilelo operands are i32, I think we have to zero extend those operands to unsigned by cast<ConstantSDNode>(Op)->getZExtValue().
whilelo operands are not restricted to i32, which can be seen by looking at IntrinsicsAArch64.td.  Although the definition suggests any integer type is allowed, that's just a deficiency of how the td file is parsed.  Realistically these intrinsics only accept either i32 or i64 operands, which are tested by sve-intrinsics-while.ll.

Perhaps you can keep things as APInt up until the comparison, at which point you know an unsigned will be big enough to hold the length.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137547/new/

https://reviews.llvm.org/D137547



More information about the llvm-commits mailing list