[PATCH] D137504: [PowerPC] Implement 64-bit ELFv2 Calling Convention in TableGen (for integers/floats/vectors in registers)

[Amy Kwan via Phabricator via llvm-commits]

amyk updated this revision to Diff 477859.
amyk added a comment.

Rebase patch. I also sync'd with Kai offline and the current implementation using a `static const MCPhysReg` array and keeping `ELF64NumArgGPRs` is OK to keep.

@nemanjai Whenever you get the chance, are you able to take a look at this patch?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137504/new/

https://reviews.llvm.org/D137504

Files:
  llvm/lib/Target/PowerPC/PPCCallingConv.cpp
  llvm/lib/Target/PowerPC/PPCCallingConv.h
  llvm/lib/Target/PowerPC/PPCCallingConv.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-fp128.ll
  llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-mixed-types.ll
  llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-scalar.ll
  llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-vectors.ll
  llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D137504.477859.patch
Type: text/x-patch
Size: 42175 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221125/2abc9857/attachment.bin>