[llvm] 15e4146 - [LSR] precommit test for D138636; NFC

[via llvm-commits]

Author: chenglin.bi
Date: 2022-11-25T13:46:51+08:00
New Revision: 15e41467f0db426693e0af40ce72e18e71bf4e9c

URL: https://github.com/llvm/llvm-project/commit/15e41467f0db426693e0af40ce72e18e71bf4e9c
DIFF: https://github.com/llvm/llvm-project/commit/15e41467f0db426693e0af40ce72e18e71bf4e9c.diff

LOG: [LSR] precommit test for D138636; NFC

Added: 
    llvm/test/Transforms/LoopStrengthReduce/AArch64/pr53625.ll
    llvm/test/Transforms/LoopStrengthReduce/ivincs-hoist.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/LoopStrengthReduce/AArch64/pr53625.ll b/llvm/test/Transforms/LoopStrengthReduce/AArch64/pr53625.ll
new file mode 100644
index 000000000000..515de763b672
--- /dev/null
+++ b/llvm/test/Transforms/LoopStrengthReduce/AArch64/pr53625.ll
@@ -0,0 +1,52 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
+
+target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
+
+; we need to generate post index load for this case
+define i32 @test(i32 %c, ptr %a, ptr %b) {
+; CHECK-LABEL: test:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cmp w0, #1
+; CHECK-NEXT:    b.lt .LBB0_4
+; CHECK-NEXT:  // %bb.1: // %for.body.preheader
+; CHECK-NEXT:    mov w8, w0
+; CHECK-NEXT:  .LBB0_2: // %for.body
+; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    ldr w9, [x1]
+; CHECK-NEXT:    cbnz w9, .LBB0_5
+; CHECK-NEXT:  // %bb.3: // %for.cond
+; CHECK-NEXT:    // in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT:    add x1, x1, #4
+; CHECK-NEXT:    subs x8, x8, #1
+; CHECK-NEXT:    b.ne .LBB0_2
+; CHECK-NEXT:  .LBB0_4:
+; CHECK-NEXT:    mov w0, wzr
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB0_5:
+; CHECK-NEXT:    mov w0, #1
+; CHECK-NEXT:    ret
+entry:
+  %cmp13 = icmp sgt i32 %c, 0
+  br i1 %cmp13, label %for.body.preheader, label %return
+
+for.body.preheader:                               ; preds = %entry
+  %wide.trip.count = zext i32 %c to i64
+  br label %for.body
+
+for.cond:                                         ; preds = %for.body
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
+  br i1 %exitcond.not, label %return, label %for.body
+
+for.body:                                         ; preds = %for.body.preheader, %for.cond
+  %indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.cond ]
+  %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
+  %val = load i32, ptr %arrayidx, align 4
+  %tobool3.not = icmp eq i32 %val, 0
+  br i1 %tobool3.not, label %for.cond, label %return
+
+return:                                           ; preds = %for.cond, %for.body, %entry
+  %retval.1 = phi i32 [ 0, %entry ], [ 0, %for.cond ], [ 1, %for.body ]
+  ret i32 %retval.1
+}

diff  --git a/llvm/test/Transforms/LoopStrengthReduce/ivincs-hoist.ll b/llvm/test/Transforms/LoopStrengthReduce/ivincs-hoist.ll
new file mode 100644
index 000000000000..2a52388d267a
--- /dev/null
+++ b/llvm/test/Transforms/LoopStrengthReduce/ivincs-hoist.ll
@@ -0,0 +1,55 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -loop-reduce -S < %s | FileCheck %s
+
+target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
+
+define i32 @test(i32 %c, ptr %a, ptr %b) {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP13:%.*]] = icmp sgt i32 [[C:%.*]], 0
+; CHECK-NEXT:    br i1 [[CMP13]], label [[FOR_BODY_PREHEADER:%.*]], label [[RETURN:%.*]]
+; CHECK:       for.body.preheader:
+; CHECK-NEXT:    [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[C]] to i64
+; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
+; CHECK:       for.cond:
+; CHECK-NEXT:    [[UGLYGEP:%.*]] = getelementptr i8, ptr [[LSR_IV:%.*]], i64 4
+; CHECK-NEXT:    [[LSR_IV_NEXT:%.*]] = add nsw i64 [[LSR_IV1:%.*]], -1
+; CHECK-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[LSR_IV_NEXT]], 0
+; CHECK-NEXT:    br i1 [[EXITCOND_NOT]], label [[RETURN_LOOPEXIT:%.*]], label [[FOR_BODY]]
+; CHECK:       for.body:
+; CHECK-NEXT:    [[LSR_IV1]] = phi i64 [ [[LSR_IV_NEXT]], [[FOR_COND:%.*]] ], [ [[WIDE_TRIP_COUNT]], [[FOR_BODY_PREHEADER]] ]
+; CHECK-NEXT:    [[LSR_IV]] = phi ptr [ [[UGLYGEP]], [[FOR_COND]] ], [ [[A:%.*]], [[FOR_BODY_PREHEADER]] ]
+; CHECK-NEXT:    [[VAL:%.*]] = load i32, ptr [[LSR_IV]], align 4
+; CHECK-NEXT:    [[TOBOOL3_NOT:%.*]] = icmp eq i32 [[VAL]], 0
+; CHECK-NEXT:    br i1 [[TOBOOL3_NOT]], label [[FOR_COND]], label [[RETURN_LOOPEXIT]]
+; CHECK:       return.loopexit:
+; CHECK-NEXT:    [[RETVAL_1_PH:%.*]] = phi i32 [ 1, [[FOR_BODY]] ], [ 0, [[FOR_COND]] ]
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       return:
+; CHECK-NEXT:    [[RETVAL_1:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[RETVAL_1_PH]], [[RETURN_LOOPEXIT]] ]
+; CHECK-NEXT:    ret i32 [[RETVAL_1]]
+;
+entry:
+  %cmp13 = icmp sgt i32 %c, 0
+  br i1 %cmp13, label %for.body.preheader, label %return
+
+for.body.preheader:                               ; preds = %entry
+  %wide.trip.count = zext i32 %c to i64
+  br label %for.body
+
+for.cond:                                         ; preds = %for.body
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
+  br i1 %exitcond.not, label %return, label %for.body
+
+for.body:                                         ; preds = %for.body.preheader, %for.cond
+  %indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.cond ]
+  %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv
+  %val = load i32, ptr %arrayidx, align 4
+  %tobool3.not = icmp eq i32 %val, 0
+  br i1 %tobool3.not, label %for.cond, label %return
+
+return:                                           ; preds = %for.cond, %for.body, %entry
+  %retval.1 = phi i32 [ 0, %entry ], [ 0, %for.cond ], [ 1, %for.body ]
+  ret i32 %retval.1
+}