[llvm] b0d4045 - [AArch64] Add support for v8.9-A/v9.4-A Debug and PMU extensions
Lucas Prates via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 24 08:15:17 PST 2022
Author: Lucas Prates
Date: 2022-11-24T16:15:11Z
New Revision: b0d4045dabef871c8ba81ff804916f78d734541b
URL: https://github.com/llvm/llvm-project/commit/b0d4045dabef871c8ba81ff804916f78d734541b
DIFF: https://github.com/llvm/llvm-project/commit/b0d4045dabef871c8ba81ff804916f78d734541b.diff
LOG: [AArch64] Add support for v8.9-A/v9.4-A Debug and PMU extensions
This adds support for the 2022 Debug and PMU extensions that are part of
the v8.9-A and v9.4-A architecture versions. This includes:
* New archtecture extension for the v9.4-A Instrumentation Extension
(FEAT_ITE), including 'trcit' instruction and system registers
* New system registers for:
* 2022 Debug features (FEAT_Debugv8p9)
* 2022 Performance Monitors Extension features (FEAT_PMUv3p9)
* PMU Snapshot extension (FEAT_PMUv3_SS)
* PMU Fixed-function instruction counter (FEAT_PMUv3_ICNTR)
* System Performance Monitors Extension (FEAT_SPMU)
* Synchornous-exception-based event profiling (FEAT_SEBEP)
* Fine Grained Traps Extension (FEAT_FGT2)
* SPE Data Source filtering (FEAT_SPE_FDS)
More information on the new extensions can be found on:
* https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022
* https://developer.arm.com/downloads/-/exploration-tools
Changes by Son Tuan Vu, Sam Elliott and me.
Reviewed By: tmatheson
Differential Revision: https://reviews.llvm.org/D138556
Added:
llvm/test/MC/AArch64/armv8.9a-debug-pmu-error.s
llvm/test/MC/AArch64/armv8.9a-debug-pmu.s
llvm/test/MC/Disassembler/AArch64/armv8.9a-debug-pmu.txt
Modified:
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64SystemOperands.td
llvm/test/MC/AArch64/armv8.6a-fgt.s
llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 9b25e98f10cbe..35583cd959bd9 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -507,6 +507,10 @@ def FeatureNoBTIAtReturnTwice : SubtargetFeature<"no-bti-at-return-twice",
def FeatureMEC : SubtargetFeature<"mec", "HasMEC",
"true", "Enable Memory Encryption Contexts Extension", [FeatureRME]>;
+def FeatureITE : SubtargetFeature<"ite", "HasITE",
+ "true", "Enable Armv9.4-A Instrumentation Extension FEAT_ITE", [FeatureETE,
+ FeatureTRBE]>;
+
//===----------------------------------------------------------------------===//
// Architectures.
//
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 28bfcbda2d28e..5cb42e7161e43 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -11758,6 +11758,23 @@ multiclass ComparisonOp<bit isUnsigned, bit isMin, string asm,
!not(isUnsigned) : simm8_64b), asm, OpNode>;
}
+//----------------------------------------------------------------------------
+// 2022 Armv8.9/Armv9.4 Extensions
+//----------------------------------------------------------------------------
+
+//---
+// Instrumentation Extension (FEAT_ITE)
+//---
+
+let Predicates = [HasITE] in
+def TRCIT : RtSystemI<0b0, (outs), (ins GPR64:$Rt), "trcit", "\t$Rt"> {
+ let Inst{20-19} = 0b01;
+ let Inst{18-16} = 0b011;
+ let Inst{15-12} = 0b0111;
+ let Inst{11-8} = 0b0010;
+ let Inst{7-5} = 0b111;
+}
+
//----------------------------------------------------------------------------
// Allow the size specifier tokens to be upper case, not just lower.
def : TokenAlias<".4B", ".4b">; // Add dot product
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index e5050f2105153..e6d6f5635e22a 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -232,6 +232,8 @@ def HasHBC : Predicate<"Subtarget->hasHBC()">,
AssemblerPredicateWithAll<(all_of FeatureHBC), "hbc">;
def HasMOPS : Predicate<"Subtarget->hasMOPS()">,
AssemblerPredicateWithAll<(all_of FeatureMOPS), "mops">;
+def HasITE : Predicate<"Subtarget->hasITE()">,
+ AssemblerPredicateWithAll<(all_of FeatureITE), "ite">;
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 6beb51007a39c..988926113e61a 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -866,7 +866,7 @@ def : WOSysReg<"ICC_SGI0R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b111>;
// Read-write regs
//===----------------------
-// Op0 Op1 CRn CRm Op2
+// Op0 Op1 CRn CRm Op2
def : RWSysReg<"OSDTRRX_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b010>;
def : RWSysReg<"OSDTRTX_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b010>;
def : RWSysReg<"TEECR32_EL1", 0b10, 0b010, 0b0000, 0b0000, 0b000>;
@@ -875,70 +875,15 @@ def : RWSysReg<"MDSCR_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b010>;
def : RWSysReg<"DBGDTR_EL0", 0b10, 0b011, 0b0000, 0b0100, 0b000>;
def : RWSysReg<"OSECCR_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b010>;
def : RWSysReg<"DBGVCR32_EL2", 0b10, 0b100, 0b0000, 0b0111, 0b000>;
-def : RWSysReg<"DBGBVR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b100>;
-def : RWSysReg<"DBGBVR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b100>;
-def : RWSysReg<"DBGBVR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b100>;
-def : RWSysReg<"DBGBVR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b100>;
-def : RWSysReg<"DBGBVR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b100>;
-def : RWSysReg<"DBGBVR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b100>;
-def : RWSysReg<"DBGBVR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b100>;
-def : RWSysReg<"DBGBVR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b100>;
-def : RWSysReg<"DBGBVR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b100>;
-def : RWSysReg<"DBGBVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b100>;
-def : RWSysReg<"DBGBVR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b100>;
-def : RWSysReg<"DBGBVR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b100>;
-def : RWSysReg<"DBGBVR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b100>;
-def : RWSysReg<"DBGBVR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b100>;
-def : RWSysReg<"DBGBVR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b100>;
-def : RWSysReg<"DBGBVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b100>;
-def : RWSysReg<"DBGBCR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b101>;
-def : RWSysReg<"DBGBCR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b101>;
-def : RWSysReg<"DBGBCR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b101>;
-def : RWSysReg<"DBGBCR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b101>;
-def : RWSysReg<"DBGBCR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b101>;
-def : RWSysReg<"DBGBCR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b101>;
-def : RWSysReg<"DBGBCR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b101>;
-def : RWSysReg<"DBGBCR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b101>;
-def : RWSysReg<"DBGBCR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b101>;
-def : RWSysReg<"DBGBCR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b101>;
-def : RWSysReg<"DBGBCR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b101>;
-def : RWSysReg<"DBGBCR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b101>;
-def : RWSysReg<"DBGBCR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b101>;
-def : RWSysReg<"DBGBCR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b101>;
-def : RWSysReg<"DBGBCR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b101>;
-def : RWSysReg<"DBGBCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b101>;
-def : RWSysReg<"DBGWVR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b110>;
-def : RWSysReg<"DBGWVR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b110>;
-def : RWSysReg<"DBGWVR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b110>;
-def : RWSysReg<"DBGWVR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b110>;
-def : RWSysReg<"DBGWVR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b110>;
-def : RWSysReg<"DBGWVR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b110>;
-def : RWSysReg<"DBGWVR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b110>;
-def : RWSysReg<"DBGWVR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b110>;
-def : RWSysReg<"DBGWVR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b110>;
-def : RWSysReg<"DBGWVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b110>;
-def : RWSysReg<"DBGWVR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b110>;
-def : RWSysReg<"DBGWVR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b110>;
-def : RWSysReg<"DBGWVR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b110>;
-def : RWSysReg<"DBGWVR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b110>;
-def : RWSysReg<"DBGWVR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b110>;
-def : RWSysReg<"DBGWVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b110>;
-def : RWSysReg<"DBGWCR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b111>;
-def : RWSysReg<"DBGWCR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b111>;
-def : RWSysReg<"DBGWCR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b111>;
-def : RWSysReg<"DBGWCR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b111>;
-def : RWSysReg<"DBGWCR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b111>;
-def : RWSysReg<"DBGWCR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b111>;
-def : RWSysReg<"DBGWCR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b111>;
-def : RWSysReg<"DBGWCR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b111>;
-def : RWSysReg<"DBGWCR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b111>;
-def : RWSysReg<"DBGWCR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b111>;
-def : RWSysReg<"DBGWCR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b111>;
-def : RWSysReg<"DBGWCR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b111>;
-def : RWSysReg<"DBGWCR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b111>;
-def : RWSysReg<"DBGWCR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b111>;
-def : RWSysReg<"DBGWCR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b111>;
-def : RWSysReg<"DBGWCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b111>;
+foreach n = 0-15 in {
+ defvar nb = !cast<bits<4>>(n);
+ // Op0 Op1 CRn CRm Op2
+ def : RWSysReg<"DBGBVR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b100>;
+ def : RWSysReg<"DBGBCR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b101>;
+ def : RWSysReg<"DBGWVR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b110>;
+ def : RWSysReg<"DBGWCR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b111>;
+}
+// Op0 Op1 CRn CRm Op2
def : RWSysReg<"TEEHBR32_EL1", 0b10, 0b010, 0b0001, 0b0000, 0b000>;
def : RWSysReg<"OSDLR_EL1", 0b10, 0b000, 0b0001, 0b0011, 0b100>;
def : RWSysReg<"DBGPRCR_EL1", 0b10, 0b000, 0b0001, 0b0100, 0b100>;
@@ -1706,6 +1651,13 @@ def : RWSysReg<"HFGWTR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b101>;
def : RWSysReg<"HFGITR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b110>;
def : RWSysReg<"HDFGRTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b100>;
def : RWSysReg<"HDFGWTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b101>;
+
+// v8.9a/v9.4a additions to Fine Grained Traps (FEAT_FGT2)
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"HDFGRTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b000>;
+def : RWSysReg<"HDFGWTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b001>;
+def : RWSysReg<"HFGRTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b010>;
+def : RWSysReg<"HFGWTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b011>;
}
// v8.6a Enhanced Counter Virtualization
@@ -1770,3 +1722,80 @@ def : RWSysReg<"TPIDR2_EL0", 0b11, 0b011, 0b1101, 0b0000, 0b101>;
let Requires = [{ {AArch64::FeatureMPAM, AArch64::FeatureSME} }] in {
def : RWSysReg<"MPAMSM_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b011>;
} // HasMPAM, HasSME
+
+// v8.9a/9.4a new Debug feature (FEAT_DEBUGv8p9)
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"MDSELR_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b010>;
+
+// v8.9a/9.4a new Performance Monitors Extension (FEAT_PMUv3p9)
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"PMUACR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b100>;
+
+// v8.9a/9.4a PMU Snapshot Extension (FEAT_PMUv3_SS)
+// Op0 Op1 CRn CRm Op2
+def : ROSysReg<"PMCCNTSVR_EL1", 0b10, 0b000, 0b1110, 0b1011, 0b111>;
+def : ROSysReg<"PMICNTSVR_EL1", 0b10, 0b000, 0b1110, 0b1100, 0b000>;
+def : RWSysReg<"PMSSCR_EL1", 0b11, 0b000, 0b1001, 0b1101, 0b011>;
+foreach n = 0-30 in {
+ defvar nb = !cast<bits<5>>(n);
+ def : ROSysReg<"PMEVCNTSVR"#n#"_EL1", 0b10, 0b000, 0b1110, {0b10,nb{4-3}}, nb{2-0}>;
+}
+
+// v8.9a/v9.4a PMUv3 Fixed-function instruction counter (FEAT_PMUv3_ICNTR)
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"PMICNTR_EL0", 0b11, 0b011, 0b1001, 0b0100, 0b000>;
+def : RWSysReg<"PMICFILTR_EL0", 0b11, 0b011, 0b1001, 0b0110, 0b000>;
+
+// v8.9a/v9.4a PMUv3 Performance Monitors Zero with Mask (FEAT_PMUv3p9/FEAT_PMUv3_ICNTR)
+// Op0 Op1 CRn CRm Op2
+def : WOSysReg<"PMZR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b100>;
+
+// v8.9a/9.4a Synchronous-Exception-Based Event Profiling extension (FEAT_SEBEP)
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"PMECR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b101>;
+def : RWSysReg<"PMIAR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b111>;
+
+// v8.9a/9.4a System Performance Monitors Extension (FEAT_SPMU)
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"SPMACCESSR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b011>;
+def : RWSysReg<"SPMACCESSR_EL12", 0b10, 0b101, 0b1001, 0b1101, 0b011>;
+def : RWSysReg<"SPMACCESSR_EL2", 0b10, 0b100, 0b1001, 0b1101, 0b011>;
+def : RWSysReg<"SPMACCESSR_EL3", 0b10, 0b110, 0b1001, 0b1101, 0b011>;
+def : RWSysReg<"SPMCNTENCLR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b010>;
+def : RWSysReg<"SPMCNTENSET_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b001>;
+def : RWSysReg<"SPMCR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b000>;
+def : ROSysReg<"SPMDEVAFF_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b110>;
+def : ROSysReg<"SPMDEVARCH_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b101>;
+foreach n = 0-15 in {
+ defvar nb = !cast<bits<4>>(n);
+ // Op0 Op1 CRn CRm Op2
+ def : RWSysReg<"SPMEVCNTR"#n#"_EL0", 0b10, 0b011, 0b1110, {0b000,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"SPMEVFILT2R"#n#"_EL0", 0b10, 0b011, 0b1110, {0b011,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"SPMEVFILTR"#n#"_EL0", 0b10, 0b011, 0b1110, {0b010,nb{3}}, nb{2-0}>;
+ def : RWSysReg<"SPMEVTYPER"#n#"_EL0", 0b10, 0b011, 0b1110, {0b001,nb{3}}, nb{2-0}>;
+}
+// Op0 Op1 CRn CRm Op2
+def : ROSysReg<"SPMIIDR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b100>;
+def : RWSysReg<"SPMINTENCLR_EL1", 0b10, 0b000, 0b1001, 0b1110, 0b010>;
+def : RWSysReg<"SPMINTENSET_EL1", 0b10, 0b000, 0b1001, 0b1110, 0b001>;
+def : RWSysReg<"SPMOVSCLR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b011>;
+def : RWSysReg<"SPMOVSSET_EL0", 0b10, 0b011, 0b1001, 0b1110, 0b011>;
+def : RWSysReg<"SPMSELR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b101>;
+def : ROSysReg<"SPMCGCR0_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b000>;
+def : ROSysReg<"SPMCGCR1_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b001>;
+def : ROSysReg<"SPMCFGR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b111>;
+def : RWSysReg<"SPMROOTCR_EL3", 0b10, 0b110, 0b1001, 0b1110, 0b111>;
+def : RWSysReg<"SPMSCR_EL1", 0b10, 0b111, 0b1001, 0b1110, 0b111>;
+
+// v8.9a/9.4a Instrumentation Extension (FEAT_ITE)
+// Op0 Op1 CRn CRm Op2
+let Requires = [{ {AArch64::FeatureITE} }] in {
+def : RWSysReg<"TRCITEEDCR", 0b10, 0b001, 0b0000, 0b0010, 0b001>;
+def : RWSysReg<"TRCITECR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b011>;
+def : RWSysReg<"TRCITECR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b011>;
+def : RWSysReg<"TRCITECR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b011>;
+}
+
+// v8.9a/9.4a SPE Data Source Filtering (FEAT_SPE_FDS)
+// Op0 Op1 CRn CRm Op2
+def : RWSysReg<"PMSDSFR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b100>;
diff --git a/llvm/test/MC/AArch64/armv8.6a-fgt.s b/llvm/test/MC/AArch64/armv8.6a-fgt.s
index d5b4f0f2e3350..599d543b6d92a 100644
--- a/llvm/test/MC/AArch64/armv8.6a-fgt.s
+++ b/llvm/test/MC/AArch64/armv8.6a-fgt.s
@@ -33,3 +33,31 @@ mrs x10, HDFGWTR_EL2
// NOFGT: error: expected readable system register
// NOFGT: error: expected readable system register
// NOFGT: error: expected readable system register
+
+
+mrs x3, HDFGRTR2_EL2
+mrs x3, HDFGWTR2_EL2
+mrs x3, HFGRTR2_EL2
+mrs x3, HFGWTR2_EL2
+// CHECK: mrs x3, HDFGRTR2_EL2 // encoding: [0x03,0x31,0x3c,0xd5]
+// CHECK: mrs x3, HDFGWTR2_EL2 // encoding: [0x23,0x31,0x3c,0xd5]
+// CHECK: mrs x3, HFGRTR2_EL2 // encoding: [0x43,0x31,0x3c,0xd5]
+// CHECK: mrs x3, HFGWTR2_EL2 // encoding: [0x63,0x31,0x3c,0xd5]
+// NOFGT: error: expected readable system register
+// NOFGT: error: expected readable system register
+// NOFGT: error: expected readable system register
+// NOFGT: error: expected readable system register
+
+
+msr HDFGRTR2_EL2, x3
+msr HDFGWTR2_EL2, x3
+msr HFGRTR2_EL2, x3
+msr HFGWTR2_EL2, x3
+// CHECK: msr HDFGRTR2_EL2, x3 // encoding: [0x03,0x31,0x1c,0xd5]
+// CHECK: msr HDFGWTR2_EL2, x3 // encoding: [0x23,0x31,0x1c,0xd5]
+// CHECK: msr HFGRTR2_EL2, x3 // encoding: [0x43,0x31,0x1c,0xd5]
+// CHECK: msr HFGWTR2_EL2, x3 // encoding: [0x63,0x31,0x1c,0xd5]
+// NOFGT: error: expected writable system register
+// NOFGT: error: expected writable system register
+// NOFGT: error: expected writable system register
+// NOFGT: error: expected writable system register
diff --git a/llvm/test/MC/AArch64/armv8.9a-debug-pmu-error.s b/llvm/test/MC/AArch64/armv8.9a-debug-pmu-error.s
new file mode 100644
index 0000000000000..ddb5fe8396b4b
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv8.9a-debug-pmu-error.s
@@ -0,0 +1,9 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ite < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.8a -mattr=+ite < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.9a -mattr=+ite < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.3a -mattr=+ite < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.4a -mattr=+ite < %s 2>&1 | FileCheck %s
+
+// FEAT_PMUv3p9/FEAT_PMUV3_ICNTR - PMZR_EL0 is write-only
+ mrs x3, PMZR_EL0
+// CHECK: [[@LINE-1]]:21: error: expected readable system register
diff --git a/llvm/test/MC/AArch64/armv8.9a-debug-pmu.s b/llvm/test/MC/AArch64/armv8.9a-debug-pmu.s
new file mode 100644
index 0000000000000..0b74905c27fb6
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv8.9a-debug-pmu.s
@@ -0,0 +1,485 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ite < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.8a -mattr=+ite < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.9a -mattr=+ite < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.3a -mattr=+ite < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.4a -mattr=+ite < %s | FileCheck %s
+
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ITE %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.8a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ITE %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.9a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ITE %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.3a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ITE %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.4a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ITE %s
+
+// FEAT_DEBUGv8p9
+ mrs x3, MDSELR_EL1
+// CHECK: mrs x3, MDSELR_EL1 // encoding: [0x43,0x04,0x30,0xd5]
+ msr MDSELR_EL1, x1
+// CHECK: msr MDSELR_EL1, x1 // encoding: [0x41,0x04,0x10,0xd5]
+
+// FEAT_PMUv3p9
+ mrs x3, PMUACR_EL1
+// CHECK: mrs x3, PMUACR_EL1 // encoding: [0x83,0x9e,0x38,0xd5]
+ msr PMUACR_EL1, x1
+// CHECK: msr PMUACR_EL1, x1 // encoding: [0x81,0x9e,0x18,0xd5]
+
+// FEAT_PMUv3_SS
+ mrs x3, PMCCNTSVR_EL1
+// CHECK: mrs x3, PMCCNTSVR_EL1 // encoding: [0xe3,0xeb,0x30,0xd5]
+ mrs x3, PMICNTSVR_EL1
+// CHECK: mrs x3, PMICNTSVR_EL1 // encoding: [0x03,0xec,0x30,0xd5]
+ mrs x3, PMSSCR_EL1
+// CHECK: mrs x3, PMSSCR_EL1 // encoding: [0x63,0x9d,0x38,0xd5]
+ msr PMSSCR_EL1, x1
+// CHECK: msr PMSSCR_EL1, x1 // encoding: [0x61,0x9d,0x18,0xd5]
+ mrs x3, PMEVCNTSVR0_EL1
+// CHECK: mrs x3, PMEVCNTSVR0_EL1 // encoding: [0x03,0xe8,0x30,0xd5]
+ mrs x3, PMEVCNTSVR1_EL1
+// CHECK: mrs x3, PMEVCNTSVR1_EL1 // encoding: [0x23,0xe8,0x30,0xd5]
+ mrs x3, PMEVCNTSVR2_EL1
+// CHECK: mrs x3, PMEVCNTSVR2_EL1 // encoding: [0x43,0xe8,0x30,0xd5]
+ mrs x3, PMEVCNTSVR3_EL1
+// CHECK: mrs x3, PMEVCNTSVR3_EL1 // encoding: [0x63,0xe8,0x30,0xd5]
+ mrs x3, PMEVCNTSVR4_EL1
+// CHECK: mrs x3, PMEVCNTSVR4_EL1 // encoding: [0x83,0xe8,0x30,0xd5]
+ mrs x3, PMEVCNTSVR5_EL1
+// CHECK: mrs x3, PMEVCNTSVR5_EL1 // encoding: [0xa3,0xe8,0x30,0xd5]
+ mrs x3, PMEVCNTSVR6_EL1
+// CHECK: mrs x3, PMEVCNTSVR6_EL1 // encoding: [0xc3,0xe8,0x30,0xd5]
+ mrs x3, PMEVCNTSVR7_EL1
+// CHECK: mrs x3, PMEVCNTSVR7_EL1 // encoding: [0xe3,0xe8,0x30,0xd5]
+ mrs x3, PMEVCNTSVR8_EL1
+// CHECK: mrs x3, PMEVCNTSVR8_EL1 // encoding: [0x03,0xe9,0x30,0xd5]
+ mrs x3, PMEVCNTSVR9_EL1
+// CHECK: mrs x3, PMEVCNTSVR9_EL1 // encoding: [0x23,0xe9,0x30,0xd5]
+ mrs x3, PMEVCNTSVR10_EL1
+// CHECK: mrs x3, PMEVCNTSVR10_EL1 // encoding: [0x43,0xe9,0x30,0xd5]
+ mrs x3, PMEVCNTSVR11_EL1
+// CHECK: mrs x3, PMEVCNTSVR11_EL1 // encoding: [0x63,0xe9,0x30,0xd5]
+ mrs x3, PMEVCNTSVR12_EL1
+// CHECK: mrs x3, PMEVCNTSVR12_EL1 // encoding: [0x83,0xe9,0x30,0xd5]
+ mrs x3, PMEVCNTSVR13_EL1
+// CHECK: mrs x3, PMEVCNTSVR13_EL1 // encoding: [0xa3,0xe9,0x30,0xd5]
+ mrs x3, PMEVCNTSVR14_EL1
+// CHECK: mrs x3, PMEVCNTSVR14_EL1 // encoding: [0xc3,0xe9,0x30,0xd5]
+ mrs x3, PMEVCNTSVR15_EL1
+// CHECK: mrs x3, PMEVCNTSVR15_EL1 // encoding: [0xe3,0xe9,0x30,0xd5]
+ mrs x3, PMEVCNTSVR16_EL1
+// CHECK: mrs x3, PMEVCNTSVR16_EL1 // encoding: [0x03,0xea,0x30,0xd5]
+ mrs x3, PMEVCNTSVR17_EL1
+// CHECK: mrs x3, PMEVCNTSVR17_EL1 // encoding: [0x23,0xea,0x30,0xd5]
+ mrs x3, PMEVCNTSVR18_EL1
+// CHECK: mrs x3, PMEVCNTSVR18_EL1 // encoding: [0x43,0xea,0x30,0xd5]
+ mrs x3, PMEVCNTSVR19_EL1
+// CHECK: mrs x3, PMEVCNTSVR19_EL1 // encoding: [0x63,0xea,0x30,0xd5]
+ mrs x3, PMEVCNTSVR20_EL1
+// CHECK: mrs x3, PMEVCNTSVR20_EL1 // encoding: [0x83,0xea,0x30,0xd5]
+ mrs x3, PMEVCNTSVR21_EL1
+// CHECK: mrs x3, PMEVCNTSVR21_EL1 // encoding: [0xa3,0xea,0x30,0xd5]
+ mrs x3, PMEVCNTSVR22_EL1
+// CHECK: mrs x3, PMEVCNTSVR22_EL1 // encoding: [0xc3,0xea,0x30,0xd5]
+ mrs x3, PMEVCNTSVR23_EL1
+// CHECK: mrs x3, PMEVCNTSVR23_EL1 // encoding: [0xe3,0xea,0x30,0xd5]
+ mrs x3, PMEVCNTSVR24_EL1
+// CHECK: mrs x3, PMEVCNTSVR24_EL1 // encoding: [0x03,0xeb,0x30,0xd5]
+ mrs x3, PMEVCNTSVR25_EL1
+// CHECK: mrs x3, PMEVCNTSVR25_EL1 // encoding: [0x23,0xeb,0x30,0xd5]
+ mrs x3, PMEVCNTSVR26_EL1
+// CHECK: mrs x3, PMEVCNTSVR26_EL1 // encoding: [0x43,0xeb,0x30,0xd5]
+ mrs x3, PMEVCNTSVR27_EL1
+// CHECK: mrs x3, PMEVCNTSVR27_EL1 // encoding: [0x63,0xeb,0x30,0xd5]
+ mrs x3, PMEVCNTSVR28_EL1
+// CHECK: mrs x3, PMEVCNTSVR28_EL1 // encoding: [0x83,0xeb,0x30,0xd5]
+ mrs x3, PMEVCNTSVR29_EL1
+// CHECK: mrs x3, PMEVCNTSVR29_EL1 // encoding: [0xa3,0xeb,0x30,0xd5]
+ mrs x3, PMEVCNTSVR30_EL1
+// CHECK: mrs x3, PMEVCNTSVR30_EL1 // encoding: [0xc3,0xeb,0x30,0xd5]
+
+// FEAT_PMUv3_ICNTR
+ mrs x3, PMICNTR_EL0
+// CHECK: mrs x3, PMICNTR_EL0 // encoding: [0x03,0x94,0x3b,0xd5]
+ msr PMICNTR_EL0, x3
+// CHECK: msr PMICNTR_EL0, x3 // encoding: [0x03,0x94,0x1b,0xd5]
+ mrs x3, PMICFILTR_EL0
+// CHECK: mrs x3, PMICFILTR_EL0 // encoding: [0x03,0x96,0x3b,0xd5]
+ msr PMICFILTR_EL0, x3
+// CHECK: msr PMICFILTR_EL0, x3 // encoding: [0x03,0x96,0x1b,0xd5]
+
+// FEAT_PMUv3p9/FEAT_PMUV3_ICNTR
+ msr PMZR_EL0, x3
+// CHECK: msr PMZR_EL0, x3 // encoding: [0x83,0x9d,0x1b,0xd5]
+
+// FEAT_SEBEP
+ mrs x3, PMECR_EL1
+// CHECK: mrs x3, PMECR_EL1 // encoding: [0xa3,0x9e,0x38,0xd5]
+ msr PMECR_EL1, x1
+// CHECK: msr PMECR_EL1, x1 // encoding: [0xa1,0x9e,0x18,0xd5]
+ mrs x3, PMIAR_EL1
+// CHECK: mrs x3, PMIAR_EL1 // encoding: [0xe3,0x9e,0x38,0xd5]
+ msr PMIAR_EL1, x1
+// CHECK: msr PMIAR_EL1, x1 // encoding: [0xe1,0x9e,0x18,0xd5]
+
+// FEAT_SPMU
+ mrs x3, SPMACCESSR_EL1
+// CHECK: mrs x3, SPMACCESSR_EL1 // encoding: [0x63,0x9d,0x30,0xd5]
+ msr SPMACCESSR_EL1, x1
+// CHECK: msr SPMACCESSR_EL1, x1 // encoding: [0x61,0x9d,0x10,0xd5]
+ mrs x3, SPMACCESSR_EL12
+// CHECK: mrs x3, SPMACCESSR_EL12 // encoding: [0x63,0x9d,0x35,0xd5]
+ msr SPMACCESSR_EL12, x1
+// CHECK: msr SPMACCESSR_EL12, x1 // encoding: [0x61,0x9d,0x15,0xd5]
+ mrs x3, SPMACCESSR_EL2
+// CHECK: mrs x3, SPMACCESSR_EL2 // encoding: [0x63,0x9d,0x34,0xd5]
+ msr SPMACCESSR_EL2, x1
+// CHECK: msr SPMACCESSR_EL2, x1 // encoding: [0x61,0x9d,0x14,0xd5]
+ mrs x3, SPMACCESSR_EL3
+// CHECK: mrs x3, SPMACCESSR_EL3 // encoding: [0x63,0x9d,0x36,0xd5]
+ msr SPMACCESSR_EL3, x1
+// CHECK: msr SPMACCESSR_EL3, x1 // encoding: [0x61,0x9d,0x16,0xd5]
+ mrs x3, SPMCNTENCLR_EL0
+// CHECK: mrs x3, SPMCNTENCLR_EL0 // encoding: [0x43,0x9c,0x33,0xd5]
+ msr SPMCNTENCLR_EL0, x1
+// CHECK: msr SPMCNTENCLR_EL0, x1 // encoding: [0x41,0x9c,0x13,0xd5]
+ mrs x3, SPMCNTENSET_EL0
+// CHECK: mrs x3, SPMCNTENSET_EL0 // encoding: [0x23,0x9c,0x33,0xd5]
+ msr SPMCNTENSET_EL0, x1
+// CHECK: msr SPMCNTENSET_EL0, x1 // encoding: [0x21,0x9c,0x13,0xd5]
+ mrs x3, SPMCR_EL0
+// CHECK: mrs x3, SPMCR_EL0 // encoding: [0x03,0x9c,0x33,0xd5]
+ msr SPMCR_EL0, x1
+// CHECK: msr SPMCR_EL0, x1 // encoding: [0x01,0x9c,0x13,0xd5]
+ mrs x3, SPMDEVAFF_EL1
+// CHECK: mrs x3, SPMDEVAFF_EL1 // encoding: [0xc3,0x9d,0x30,0xd5]
+ mrs x3, SPMDEVARCH_EL1
+// CHECK: mrs x3, SPMDEVARCH_EL1 // encoding: [0xa3,0x9d,0x30,0xd5]
+
+ mrs x3, SPMEVCNTR0_EL0
+// CHECK: mrs x3, SPMEVCNTR0_EL0 // encoding: [0x03,0xe0,0x33,0xd5]
+ msr SPMEVCNTR0_EL0, x1
+// CHECK: msr SPMEVCNTR0_EL0, x1 // encoding: [0x01,0xe0,0x13,0xd5]
+ mrs x3, SPMEVCNTR1_EL0
+// CHECK: mrs x3, SPMEVCNTR1_EL0 // encoding: [0x23,0xe0,0x33,0xd5]
+ msr SPMEVCNTR1_EL0, x1
+// CHECK: msr SPMEVCNTR1_EL0, x1 // encoding: [0x21,0xe0,0x13,0xd5]
+ mrs x3, SPMEVCNTR2_EL0
+// CHECK: mrs x3, SPMEVCNTR2_EL0 // encoding: [0x43,0xe0,0x33,0xd5]
+ msr SPMEVCNTR2_EL0, x1
+// CHECK: msr SPMEVCNTR2_EL0, x1 // encoding: [0x41,0xe0,0x13,0xd5]
+ mrs x3, SPMEVCNTR3_EL0
+// CHECK: mrs x3, SPMEVCNTR3_EL0 // encoding: [0x63,0xe0,0x33,0xd5]
+ msr SPMEVCNTR3_EL0, x1
+// CHECK: msr SPMEVCNTR3_EL0, x1 // encoding: [0x61,0xe0,0x13,0xd5]
+ mrs x3, SPMEVCNTR4_EL0
+// CHECK: mrs x3, SPMEVCNTR4_EL0 // encoding: [0x83,0xe0,0x33,0xd5]
+ msr SPMEVCNTR4_EL0, x1
+// CHECK: msr SPMEVCNTR4_EL0, x1 // encoding: [0x81,0xe0,0x13,0xd5]
+ mrs x3, SPMEVCNTR5_EL0
+// CHECK: mrs x3, SPMEVCNTR5_EL0 // encoding: [0xa3,0xe0,0x33,0xd5]
+ msr SPMEVCNTR5_EL0, x1
+// CHECK: msr SPMEVCNTR5_EL0, x1 // encoding: [0xa1,0xe0,0x13,0xd5]
+ mrs x3, SPMEVCNTR6_EL0
+// CHECK: mrs x3, SPMEVCNTR6_EL0 // encoding: [0xc3,0xe0,0x33,0xd5]
+ msr SPMEVCNTR6_EL0, x1
+// CHECK: msr SPMEVCNTR6_EL0, x1 // encoding: [0xc1,0xe0,0x13,0xd5]
+ mrs x3, SPMEVCNTR7_EL0
+// CHECK: mrs x3, SPMEVCNTR7_EL0 // encoding: [0xe3,0xe0,0x33,0xd5]
+ msr SPMEVCNTR7_EL0, x1
+// CHECK: msr SPMEVCNTR7_EL0, x1 // encoding: [0xe1,0xe0,0x13,0xd5]
+ mrs x3, SPMEVCNTR8_EL0
+// CHECK: mrs x3, SPMEVCNTR8_EL0 // encoding: [0x03,0xe1,0x33,0xd5]
+ msr SPMEVCNTR8_EL0, x1
+// CHECK: msr SPMEVCNTR8_EL0, x1 // encoding: [0x01,0xe1,0x13,0xd5]
+ mrs x3, SPMEVCNTR9_EL0
+// CHECK: mrs x3, SPMEVCNTR9_EL0 // encoding: [0x23,0xe1,0x33,0xd5]
+ msr SPMEVCNTR9_EL0, x1
+// CHECK: msr SPMEVCNTR9_EL0, x1 // encoding: [0x21,0xe1,0x13,0xd5]
+ mrs x3, SPMEVCNTR10_EL0
+// CHECK: mrs x3, SPMEVCNTR10_EL0 // encoding: [0x43,0xe1,0x33,0xd5]
+ msr SPMEVCNTR10_EL0, x1
+// CHECK: msr SPMEVCNTR10_EL0, x1 // encoding: [0x41,0xe1,0x13,0xd5]
+ mrs x3, SPMEVCNTR11_EL0
+// CHECK: mrs x3, SPMEVCNTR11_EL0 // encoding: [0x63,0xe1,0x33,0xd5]
+ msr SPMEVCNTR11_EL0, x1
+// CHECK: msr SPMEVCNTR11_EL0, x1 // encoding: [0x61,0xe1,0x13,0xd5]
+ mrs x3, SPMEVCNTR12_EL0
+// CHECK: mrs x3, SPMEVCNTR12_EL0 // encoding: [0x83,0xe1,0x33,0xd5]
+ msr SPMEVCNTR12_EL0, x1
+// CHECK: msr SPMEVCNTR12_EL0, x1 // encoding: [0x81,0xe1,0x13,0xd5]
+ mrs x3, SPMEVCNTR13_EL0
+// CHECK: mrs x3, SPMEVCNTR13_EL0 // encoding: [0xa3,0xe1,0x33,0xd5]
+ msr SPMEVCNTR13_EL0, x1
+// CHECK: msr SPMEVCNTR13_EL0, x1 // encoding: [0xa1,0xe1,0x13,0xd5]
+ mrs x3, SPMEVCNTR14_EL0
+// CHECK: mrs x3, SPMEVCNTR14_EL0 // encoding: [0xc3,0xe1,0x33,0xd5]
+ msr SPMEVCNTR14_EL0, x1
+// CHECK: msr SPMEVCNTR14_EL0, x1 // encoding: [0xc1,0xe1,0x13,0xd5]
+ mrs x3, SPMEVCNTR15_EL0
+// CHECK: mrs x3, SPMEVCNTR15_EL0 // encoding: [0xe3,0xe1,0x33,0xd5]
+ msr SPMEVCNTR15_EL0, x1
+// CHECK: msr SPMEVCNTR15_EL0, x1 // encoding: [0xe1,0xe1,0x13,0xd5]
+
+ mrs x3, SPMEVFILT2R0_EL0
+// CHECK: mrs x3, SPMEVFILT2R0_EL0 // encoding: [0x03,0xe6,0x33,0xd5]
+ msr SPMEVFILT2R0_EL0, x1
+// CHECK: msr SPMEVFILT2R0_EL0, x1 // encoding: [0x01,0xe6,0x13,0xd5]
+ mrs x3, SPMEVFILT2R1_EL0
+// CHECK: mrs x3, SPMEVFILT2R1_EL0 // encoding: [0x23,0xe6,0x33,0xd5]
+ msr SPMEVFILT2R1_EL0, x1
+// CHECK: msr SPMEVFILT2R1_EL0, x1 // encoding: [0x21,0xe6,0x13,0xd5]
+ mrs x3, SPMEVFILT2R2_EL0
+// CHECK: mrs x3, SPMEVFILT2R2_EL0 // encoding: [0x43,0xe6,0x33,0xd5]
+ msr SPMEVFILT2R2_EL0, x1
+// CHECK: msr SPMEVFILT2R2_EL0, x1 // encoding: [0x41,0xe6,0x13,0xd5]
+ mrs x3, SPMEVFILT2R3_EL0
+// CHECK: mrs x3, SPMEVFILT2R3_EL0 // encoding: [0x63,0xe6,0x33,0xd5]
+ msr SPMEVFILT2R3_EL0, x1
+// CHECK: msr SPMEVFILT2R3_EL0, x1 // encoding: [0x61,0xe6,0x13,0xd5]
+ mrs x3, SPMEVFILT2R4_EL0
+// CHECK: mrs x3, SPMEVFILT2R4_EL0 // encoding: [0x83,0xe6,0x33,0xd5]
+ msr SPMEVFILT2R4_EL0, x1
+// CHECK: msr SPMEVFILT2R4_EL0, x1 // encoding: [0x81,0xe6,0x13,0xd5]
+ mrs x3, SPMEVFILT2R5_EL0
+// CHECK: mrs x3, SPMEVFILT2R5_EL0 // encoding: [0xa3,0xe6,0x33,0xd5]
+ msr SPMEVFILT2R5_EL0, x1
+// CHECK: msr SPMEVFILT2R5_EL0, x1 // encoding: [0xa1,0xe6,0x13,0xd5]
+ mrs x3, SPMEVFILT2R6_EL0
+// CHECK: mrs x3, SPMEVFILT2R6_EL0 // encoding: [0xc3,0xe6,0x33,0xd5]
+ msr SPMEVFILT2R6_EL0, x1
+// CHECK: msr SPMEVFILT2R6_EL0, x1 // encoding: [0xc1,0xe6,0x13,0xd5]
+ mrs x3, SPMEVFILT2R7_EL0
+// CHECK: mrs x3, SPMEVFILT2R7_EL0 // encoding: [0xe3,0xe6,0x33,0xd5]
+ msr SPMEVFILT2R7_EL0, x1
+// CHECK: msr SPMEVFILT2R7_EL0, x1 // encoding: [0xe1,0xe6,0x13,0xd5]
+ mrs x3, SPMEVFILT2R8_EL0
+// CHECK: mrs x3, SPMEVFILT2R8_EL0 // encoding: [0x03,0xe7,0x33,0xd5]
+ msr SPMEVFILT2R8_EL0, x1
+// CHECK: msr SPMEVFILT2R8_EL0, x1 // encoding: [0x01,0xe7,0x13,0xd5]
+ mrs x3, SPMEVFILT2R9_EL0
+// CHECK: mrs x3, SPMEVFILT2R9_EL0 // encoding: [0x23,0xe7,0x33,0xd5]
+ msr SPMEVFILT2R9_EL0, x1
+// CHECK: msr SPMEVFILT2R9_EL0, x1 // encoding: [0x21,0xe7,0x13,0xd5]
+ mrs x3, SPMEVFILT2R10_EL0
+// CHECK: mrs x3, SPMEVFILT2R10_EL0 // encoding: [0x43,0xe7,0x33,0xd5]
+ msr SPMEVFILT2R10_EL0, x1
+// CHECK: msr SPMEVFILT2R10_EL0, x1 // encoding: [0x41,0xe7,0x13,0xd5]
+ mrs x3, SPMEVFILT2R11_EL0
+// CHECK: mrs x3, SPMEVFILT2R11_EL0 // encoding: [0x63,0xe7,0x33,0xd5]
+ msr SPMEVFILT2R11_EL0, x1
+// CHECK: msr SPMEVFILT2R11_EL0, x1 // encoding: [0x61,0xe7,0x13,0xd5]
+ mrs x3, SPMEVFILT2R12_EL0
+// CHECK: mrs x3, SPMEVFILT2R12_EL0 // encoding: [0x83,0xe7,0x33,0xd5]
+ msr SPMEVFILT2R12_EL0, x1
+// CHECK: msr SPMEVFILT2R12_EL0, x1 // encoding: [0x81,0xe7,0x13,0xd5]
+ mrs x3, SPMEVFILT2R13_EL0
+// CHECK: mrs x3, SPMEVFILT2R13_EL0 // encoding: [0xa3,0xe7,0x33,0xd5]
+ msr SPMEVFILT2R13_EL0, x1
+// CHECK: msr SPMEVFILT2R13_EL0, x1 // encoding: [0xa1,0xe7,0x13,0xd5]
+ mrs x3, SPMEVFILT2R14_EL0
+// CHECK: mrs x3, SPMEVFILT2R14_EL0 // encoding: [0xc3,0xe7,0x33,0xd5]
+ msr SPMEVFILT2R14_EL0, x1
+// CHECK: msr SPMEVFILT2R14_EL0, x1 // encoding: [0xc1,0xe7,0x13,0xd5]
+ mrs x3, SPMEVFILT2R15_EL0
+// CHECK: mrs x3, SPMEVFILT2R15_EL0 // encoding: [0xe3,0xe7,0x33,0xd5]
+ msr SPMEVFILT2R15_EL0, x1
+// CHECK: msr SPMEVFILT2R15_EL0, x1 // encoding: [0xe1,0xe7,0x13,0xd5]
+
+ mrs x3, SPMEVFILTR0_EL0
+// CHECK: mrs x3, SPMEVFILTR0_EL0 // encoding: [0x03,0xe4,0x33,0xd5]
+ msr SPMEVFILTR0_EL0, x1
+// CHECK: msr SPMEVFILTR0_EL0, x1 // encoding: [0x01,0xe4,0x13,0xd5]
+ mrs x3, SPMEVFILTR1_EL0
+// CHECK: mrs x3, SPMEVFILTR1_EL0 // encoding: [0x23,0xe4,0x33,0xd5]
+ msr SPMEVFILTR1_EL0, x1
+// CHECK: msr SPMEVFILTR1_EL0, x1 // encoding: [0x21,0xe4,0x13,0xd5]
+ mrs x3, SPMEVFILTR2_EL0
+// CHECK: mrs x3, SPMEVFILTR2_EL0 // encoding: [0x43,0xe4,0x33,0xd5]
+ msr SPMEVFILTR2_EL0, x1
+// CHECK: msr SPMEVFILTR2_EL0, x1 // encoding: [0x41,0xe4,0x13,0xd5]
+ mrs x3, SPMEVFILTR3_EL0
+// CHECK: mrs x3, SPMEVFILTR3_EL0 // encoding: [0x63,0xe4,0x33,0xd5]
+ msr SPMEVFILTR3_EL0, x1
+// CHECK: msr SPMEVFILTR3_EL0, x1 // encoding: [0x61,0xe4,0x13,0xd5]
+ mrs x3, SPMEVFILTR4_EL0
+// CHECK: mrs x3, SPMEVFILTR4_EL0 // encoding: [0x83,0xe4,0x33,0xd5]
+ msr SPMEVFILTR4_EL0, x1
+// CHECK: msr SPMEVFILTR4_EL0, x1 // encoding: [0x81,0xe4,0x13,0xd5]
+ mrs x3, SPMEVFILTR5_EL0
+// CHECK: mrs x3, SPMEVFILTR5_EL0 // encoding: [0xa3,0xe4,0x33,0xd5]
+ msr SPMEVFILTR5_EL0, x1
+// CHECK: msr SPMEVFILTR5_EL0, x1 // encoding: [0xa1,0xe4,0x13,0xd5]
+ mrs x3, SPMEVFILTR6_EL0
+// CHECK: mrs x3, SPMEVFILTR6_EL0 // encoding: [0xc3,0xe4,0x33,0xd5]
+ msr SPMEVFILTR6_EL0, x1
+// CHECK: msr SPMEVFILTR6_EL0, x1 // encoding: [0xc1,0xe4,0x13,0xd5]
+ mrs x3, SPMEVFILTR7_EL0
+// CHECK: mrs x3, SPMEVFILTR7_EL0 // encoding: [0xe3,0xe4,0x33,0xd5]
+ msr SPMEVFILTR7_EL0, x1
+// CHECK: msr SPMEVFILTR7_EL0, x1 // encoding: [0xe1,0xe4,0x13,0xd5]
+ mrs x3, SPMEVFILTR8_EL0
+// CHECK: mrs x3, SPMEVFILTR8_EL0 // encoding: [0x03,0xe5,0x33,0xd5]
+ msr SPMEVFILTR8_EL0, x1
+// CHECK: msr SPMEVFILTR8_EL0, x1 // encoding: [0x01,0xe5,0x13,0xd5]
+ mrs x3, SPMEVFILTR9_EL0
+// CHECK: mrs x3, SPMEVFILTR9_EL0 // encoding: [0x23,0xe5,0x33,0xd5]
+ msr SPMEVFILTR9_EL0, x1
+// CHECK: msr SPMEVFILTR9_EL0, x1 // encoding: [0x21,0xe5,0x13,0xd5]
+ mrs x3, SPMEVFILTR10_EL0
+// CHECK: mrs x3, SPMEVFILTR10_EL0 // encoding: [0x43,0xe5,0x33,0xd5]
+ msr SPMEVFILTR10_EL0, x1
+// CHECK: msr SPMEVFILTR10_EL0, x1 // encoding: [0x41,0xe5,0x13,0xd5]
+ mrs x3, SPMEVFILTR11_EL0
+// CHECK: mrs x3, SPMEVFILTR11_EL0 // encoding: [0x63,0xe5,0x33,0xd5]
+ msr SPMEVFILTR11_EL0, x1
+// CHECK: msr SPMEVFILTR11_EL0, x1 // encoding: [0x61,0xe5,0x13,0xd5]
+ mrs x3, SPMEVFILTR12_EL0
+// CHECK: mrs x3, SPMEVFILTR12_EL0 // encoding: [0x83,0xe5,0x33,0xd5]
+ msr SPMEVFILTR12_EL0, x1
+// CHECK: msr SPMEVFILTR12_EL0, x1 // encoding: [0x81,0xe5,0x13,0xd5]
+ mrs x3, SPMEVFILTR13_EL0
+// CHECK: mrs x3, SPMEVFILTR13_EL0 // encoding: [0xa3,0xe5,0x33,0xd5]
+ msr SPMEVFILTR13_EL0, x1
+// CHECK: msr SPMEVFILTR13_EL0, x1 // encoding: [0xa1,0xe5,0x13,0xd5]
+ mrs x3, SPMEVFILTR14_EL0
+// CHECK: mrs x3, SPMEVFILTR14_EL0 // encoding: [0xc3,0xe5,0x33,0xd5]
+ msr SPMEVFILTR14_EL0, x1
+// CHECK: msr SPMEVFILTR14_EL0, x1 // encoding: [0xc1,0xe5,0x13,0xd5]
+ mrs x3, SPMEVFILTR15_EL0
+// CHECK: mrs x3, SPMEVFILTR15_EL0 // encoding: [0xe3,0xe5,0x33,0xd5]
+ msr SPMEVFILTR15_EL0, x1
+// CHECK: msr SPMEVFILTR15_EL0, x1 // encoding: [0xe1,0xe5,0x13,0xd5]
+
+ mrs x3, SPMEVTYPER0_EL0
+// CHECK: mrs x3, SPMEVTYPER0_EL0 // encoding: [0x03,0xe2,0x33,0xd5]
+ msr SPMEVTYPER0_EL0, x1
+// CHECK: msr SPMEVTYPER0_EL0, x1 // encoding: [0x01,0xe2,0x13,0xd5]
+ mrs x3, SPMEVTYPER1_EL0
+// CHECK: mrs x3, SPMEVTYPER1_EL0 // encoding: [0x23,0xe2,0x33,0xd5]
+ msr SPMEVTYPER1_EL0, x1
+// CHECK: msr SPMEVTYPER1_EL0, x1 // encoding: [0x21,0xe2,0x13,0xd5]
+ mrs x3, SPMEVTYPER2_EL0
+// CHECK: mrs x3, SPMEVTYPER2_EL0 // encoding: [0x43,0xe2,0x33,0xd5]
+ msr SPMEVTYPER2_EL0, x1
+// CHECK: msr SPMEVTYPER2_EL0, x1 // encoding: [0x41,0xe2,0x13,0xd5]
+ mrs x3, SPMEVTYPER3_EL0
+// CHECK: mrs x3, SPMEVTYPER3_EL0 // encoding: [0x63,0xe2,0x33,0xd5]
+ msr SPMEVTYPER3_EL0, x1
+// CHECK: msr SPMEVTYPER3_EL0, x1 // encoding: [0x61,0xe2,0x13,0xd5]
+ mrs x3, SPMEVTYPER4_EL0
+// CHECK: mrs x3, SPMEVTYPER4_EL0 // encoding: [0x83,0xe2,0x33,0xd5]
+ msr SPMEVTYPER4_EL0, x1
+// CHECK: msr SPMEVTYPER4_EL0, x1 // encoding: [0x81,0xe2,0x13,0xd5]
+ mrs x3, SPMEVTYPER5_EL0
+// CHECK: mrs x3, SPMEVTYPER5_EL0 // encoding: [0xa3,0xe2,0x33,0xd5]
+ msr SPMEVTYPER5_EL0, x1
+// CHECK: msr SPMEVTYPER5_EL0, x1 // encoding: [0xa1,0xe2,0x13,0xd5]
+ mrs x3, SPMEVTYPER6_EL0
+// CHECK: mrs x3, SPMEVTYPER6_EL0 // encoding: [0xc3,0xe2,0x33,0xd5]
+ msr SPMEVTYPER6_EL0, x1
+// CHECK: msr SPMEVTYPER6_EL0, x1 // encoding: [0xc1,0xe2,0x13,0xd5]
+ mrs x3, SPMEVTYPER7_EL0
+// CHECK: mrs x3, SPMEVTYPER7_EL0 // encoding: [0xe3,0xe2,0x33,0xd5]
+ msr SPMEVTYPER7_EL0, x1
+// CHECK: msr SPMEVTYPER7_EL0, x1 // encoding: [0xe1,0xe2,0x13,0xd5]
+ mrs x3, SPMEVTYPER8_EL0
+// CHECK: mrs x3, SPMEVTYPER8_EL0 // encoding: [0x03,0xe3,0x33,0xd5]
+ msr SPMEVTYPER8_EL0, x1
+// CHECK: msr SPMEVTYPER8_EL0, x1 // encoding: [0x01,0xe3,0x13,0xd5]
+ mrs x3, SPMEVTYPER9_EL0
+// CHECK: mrs x3, SPMEVTYPER9_EL0 // encoding: [0x23,0xe3,0x33,0xd5]
+ msr SPMEVTYPER9_EL0, x1
+// CHECK: msr SPMEVTYPER9_EL0, x1 // encoding: [0x21,0xe3,0x13,0xd5]
+ mrs x3, SPMEVTYPER10_EL0
+// CHECK: mrs x3, SPMEVTYPER10_EL0 // encoding: [0x43,0xe3,0x33,0xd5]
+ msr SPMEVTYPER10_EL0, x1
+// CHECK: msr SPMEVTYPER10_EL0, x1 // encoding: [0x41,0xe3,0x13,0xd5]
+ mrs x3, SPMEVTYPER11_EL0
+// CHECK: mrs x3, SPMEVTYPER11_EL0 // encoding: [0x63,0xe3,0x33,0xd5]
+ msr SPMEVTYPER11_EL0, x1
+// CHECK: msr SPMEVTYPER11_EL0, x1 // encoding: [0x61,0xe3,0x13,0xd5]
+ mrs x3, SPMEVTYPER12_EL0
+// CHECK: mrs x3, SPMEVTYPER12_EL0 // encoding: [0x83,0xe3,0x33,0xd5]
+ msr SPMEVTYPER12_EL0, x1
+// CHECK: msr SPMEVTYPER12_EL0, x1 // encoding: [0x81,0xe3,0x13,0xd5]
+ mrs x3, SPMEVTYPER13_EL0
+// CHECK: mrs x3, SPMEVTYPER13_EL0 // encoding: [0xa3,0xe3,0x33,0xd5]
+ msr SPMEVTYPER13_EL0, x1
+// CHECK: msr SPMEVTYPER13_EL0, x1 // encoding: [0xa1,0xe3,0x13,0xd5]
+ mrs x3, SPMEVTYPER14_EL0
+// CHECK: mrs x3, SPMEVTYPER14_EL0 // encoding: [0xc3,0xe3,0x33,0xd5]
+ msr SPMEVTYPER14_EL0, x1
+// CHECK: msr SPMEVTYPER14_EL0, x1 // encoding: [0xc1,0xe3,0x13,0xd5]
+ mrs x3, SPMEVTYPER15_EL0
+// CHECK: mrs x3, SPMEVTYPER15_EL0 // encoding: [0xe3,0xe3,0x33,0xd5]
+ msr SPMEVTYPER15_EL0, x1
+// CHECK: msr SPMEVTYPER15_EL0, x1 // encoding: [0xe1,0xe3,0x13,0xd5]
+
+ mrs x3, SPMIIDR_EL1
+// CHECK: mrs x3, SPMIIDR_EL1 // encoding: [0x83,0x9d,0x30,0xd5]
+ mrs x3, SPMINTENCLR_EL1
+// CHECK: mrs x3, SPMINTENCLR_EL1 // encoding: [0x43,0x9e,0x30,0xd5]
+ msr SPMINTENCLR_EL1, x1
+// CHECK: msr SPMINTENCLR_EL1, x1 // encoding: [0x41,0x9e,0x10,0xd5]
+ mrs x3, SPMINTENSET_EL1
+// CHECK: mrs x3, SPMINTENSET_EL1 // encoding: [0x23,0x9e,0x30,0xd5]
+ msr SPMINTENSET_EL1, x1
+// CHECK: msr SPMINTENSET_EL1, x1 // encoding: [0x21,0x9e,0x10,0xd5]
+ mrs x3, SPMOVSCLR_EL0
+// CHECK: mrs x3, SPMOVSCLR_EL0 // encoding: [0x63,0x9c,0x33,0xd5]
+ msr SPMOVSCLR_EL0, x1
+// CHECK: msr SPMOVSCLR_EL0, x1 // encoding: [0x61,0x9c,0x13,0xd5]
+ mrs x3, SPMOVSSET_EL0
+// CHECK: mrs x3, SPMOVSSET_EL0 // encoding: [0x63,0x9e,0x33,0xd5]
+ msr SPMOVSSET_EL0, x1
+// CHECK: msr SPMOVSSET_EL0, x1 // encoding: [0x61,0x9e,0x13,0xd5]
+ mrs x3, SPMSELR_EL0
+// CHECK: mrs x3, SPMSELR_EL0 // encoding: [0xa3,0x9c,0x33,0xd5]
+ msr SPMSELR_EL0, x1
+// CHECK: msr SPMSELR_EL0, x1 // encoding: [0xa1,0x9c,0x13,0xd5]
+ mrs x3, SPMCGCR0_EL1
+// CHECK: mrs x3, SPMCGCR0_EL1 // encoding: [0x03,0x9d,0x30,0xd5]
+ mrs x3, SPMCGCR1_EL1
+// CHECK: mrs x3, SPMCGCR1_EL1 // encoding: [0x23,0x9d,0x30,0xd5]
+ mrs x3, SPMCFGR_EL1
+// CHECK: mrs x3, SPMCFGR_EL1 // encoding: [0xe3,0x9d,0x30,0xd5]
+ mrs x3, SPMROOTCR_EL3
+// CHECK: mrs x3, SPMROOTCR_EL3 // encoding: [0xe3,0x9e,0x36,0xd5]
+ msr SPMROOTCR_EL3, x3
+// CHECK: msr SPMROOTCR_EL3, x3 // encoding: [0xe3,0x9e,0x16,0xd5]
+ mrs x3, SPMSCR_EL1
+// CHECK: mrs x3, SPMSCR_EL1 // encoding: [0xe3,0x9e,0x37,0xd5]
+ msr SPMSCR_EL1, x3
+// CHECK: msr SPMSCR_EL1, x3 // encoding: [0xe3,0x9e,0x17,0xd5]
+
+// FEAT_ITE
+ mrs x3, TRCITEEDCR
+// CHECK: mrs x3, TRCITEEDCR // encoding: [0x23,0x02,0x31,0xd5]
+// ERROR-NO-ITE: [[@LINE-2]]:21: error: expected readable system register
+ msr TRCITEEDCR, x3
+// CHECK: msr TRCITEEDCR, x3 // encoding: [0x23,0x02,0x11,0xd5]
+// ERROR-NO-ITE: [[@LINE-2]]:17: error: expected writable system register
+ mrs x3, TRCITECR_EL1
+// CHECK: mrs x3, TRCITECR_EL1 // encoding: [0x63,0x12,0x38,0xd5]
+// ERROR-NO-ITE: [[@LINE-2]]:21: error: expected readable system register
+ msr TRCITECR_EL1, x1
+// CHECK: msr TRCITECR_EL1, x1 // encoding: [0x61,0x12,0x18,0xd5]
+// ERROR-NO-ITE: [[@LINE-2]]:17: error: expected writable system register or pstate
+ mrs x3, TRCITECR_EL12
+// CHECK: mrs x3, TRCITECR_EL12 // encoding: [0x63,0x12,0x3d,0xd5]
+// ERROR-NO-ITE: [[@LINE-2]]:21: error: expected readable system register
+ msr TRCITECR_EL12, x1
+// CHECK: msr TRCITECR_EL12, x1 // encoding: [0x61,0x12,0x1d,0xd5]
+// ERROR-NO-ITE: [[@LINE-2]]:17: error: expected writable system register or pstate
+ mrs x3, TRCITECR_EL2
+// CHECK: mrs x3, TRCITECR_EL2 // encoding: [0x63,0x12,0x3c,0xd5]
+// ERROR-NO-ITE: [[@LINE-2]]:21: error: expected readable system register
+ msr TRCITECR_EL2, x1
+// CHECK: msr TRCITECR_EL2, x1 // encoding: [0x61,0x12,0x1c,0xd5]
+// ERROR-NO-ITE: [[@LINE-2]]:17: error: expected writable system register or pstate
+ trcit x1
+// CHECK: trcit x1 // encoding: [0xe1,0x72,0x0b,0xd5]
+// ERROR-NO-ITE: [[@LINE-2]]:13: error: instruction requires: ite
+
+// FEAT_SPE_FDS
+ mrs x3, PMSDSFR_EL1
+// CHECK: mrs x3, PMSDSFR_EL1 // encoding: [0x83,0x9a,0x38,0xd5]
+ msr PMSDSFR_EL1, x3
+// CHECK: msr PMSDSFR_EL1, x3 // encoding: [0x83,0x9a,0x18,0xd5]
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt b/llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt
index 39c017dbf0946..93d4a7b7d146c 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt
@@ -34,3 +34,30 @@
# NOFGT: mrs x0, S3_4_C1_C1_6
# NOFGT: mrs x0, S3_4_C3_C1_4
# NOFGT: mrs x0, S3_4_C3_C1_5
+
+[0x03,0x31,0x3c,0xd5]
+[0x23,0x31,0x3c,0xd5]
+[0x43,0x31,0x3c,0xd5]
+[0x63,0x31,0x3c,0xd5]
+# CHECK: mrs x3, HDFGRTR2_EL2
+# CHECK: mrs x3, HDFGWTR2_EL2
+# CHECK: mrs x3, HFGRTR2_EL2
+# CHECK: mrs x3, HFGWTR2_EL2
+# NOFGT: mrs x3, S3_4_C3_C1_0
+# NOFGT: mrs x3, S3_4_C3_C1_1
+# NOFGT: mrs x3, S3_4_C3_C1_2
+# NOFGT: mrs x3, S3_4_C3_C1_3
+
+
+[0x03,0x31,0x1c,0xd5]
+[0x23,0x31,0x1c,0xd5]
+[0x43,0x31,0x1c,0xd5]
+[0x63,0x31,0x1c,0xd5]
+# CHECK: msr HDFGRTR2_EL2, x3
+# CHECK: msr HDFGWTR2_EL2, x3
+# CHECK: msr HFGRTR2_EL2, x3
+# CHECK: msr HFGWTR2_EL2, x3
+# NOFGT: msr S3_4_C3_C1_0, x3
+# NOFGT: msr S3_4_C3_C1_1, x3
+# NOFGT: msr S3_4_C3_C1_2, x3
+# NOFGT: msr S3_4_C3_C1_3, x3
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.9a-debug-pmu.txt b/llvm/test/MC/Disassembler/AArch64/armv8.9a-debug-pmu.txt
new file mode 100644
index 0000000000000..ff898fec0c92f
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.9a-debug-pmu.txt
@@ -0,0 +1,730 @@
+# RUN: llvm-mc -triple=aarch64 -mattr=+ite -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.8a -mattr=+ite -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v9.3a -mattr=+ite -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.9a -mattr=+ite -disassemble %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v9.4a -mattr=+ite -disassemble %s | FileCheck %s
+
+# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck %s --check-prefix=ERROR-NO-ITE
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.8a -disassemble %s | FileCheck %s --check-prefix=ERROR-NO-ITE
+# RUN: llvm-mc -triple=aarch64 -mattr=+v9.3a -disassemble %s | FileCheck %s --check-prefix=ERROR-NO-ITE
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.9a -disassemble %s | FileCheck %s --check-prefix=ERROR-NO-ITE
+# RUN: llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble %s | FileCheck %s --check-prefix=ERROR-NO-ITE
+
+[0x83,0x00,0x30,0xd5]
+# CHECK: mrs x3, DBGBVR0_EL1
+[0x81,0x00,0x10,0xd5]
+# CHECK: msr DBGBVR0_EL1, x1
+[0x83,0x01,0x30,0xd5]
+# CHECK: mrs x3, DBGBVR1_EL1
+[0x81,0x01,0x10,0xd5]
+# CHECK: msr DBGBVR1_EL1, x1
+[0x83,0x02,0x30,0xd5]
+# CHECK: mrs x3, DBGBVR2_EL1
+[0x81,0x02,0x10,0xd5]
+# CHECK: msr DBGBVR2_EL1, x1
+[0x83,0x03,0x30,0xd5]
+# CHECK: mrs x3, DBGBVR3_EL1
+[0x81,0x03,0x10,0xd5]
+# CHECK: msr DBGBVR3_EL1, x1
+[0x83,0x04,0x30,0xd5]
+# CHECK: mrs x3, DBGBVR4_EL1
+[0x81,0x04,0x10,0xd5]
+# CHECK: msr DBGBVR4_EL1, x1
+[0x83,0x05,0x30,0xd5]
+# CHECK: mrs x3, DBGBVR5_EL1
+[0x81,0x05,0x10,0xd5]
+# CHECK: msr DBGBVR5_EL1, x1
+[0x83,0x06,0x30,0xd5]
+# CHECK: mrs x3, DBGBVR6_EL1
+[0x81,0x06,0x10,0xd5]
+# CHECK: msr DBGBVR6_EL1, x1
+[0x83,0x07,0x30,0xd5]
+# CHECK: mrs x3, DBGBVR7_EL1
+[0x81,0x07,0x10,0xd5]
+# CHECK: msr DBGBVR7_EL1, x1
+[0x83,0x08,0x30,0xd5]
+# CHECK: mrs x3, DBGBVR8_EL1
+[0x81,0x08,0x10,0xd5]
+# CHECK: msr DBGBVR8_EL1, x1
+[0x83,0x09,0x30,0xd5]
+# CHECK: mrs x3, DBGBVR9_EL1
+[0x81,0x09,0x10,0xd5]
+# CHECK: msr DBGBVR9_EL1, x1
+[0x83,0x0a,0x30,0xd5]
+# CHECK: mrs x3, DBGBVR10_EL1
+[0x81,0x0a,0x10,0xd5]
+# CHECK: msr DBGBVR10_EL1, x1
+[0x83,0x0b,0x30,0xd5]
+# CHECK: mrs x3, DBGBVR11_EL1
+[0x81,0x0b,0x10,0xd5]
+# CHECK: msr DBGBVR11_EL1, x1
+[0x83,0x0c,0x30,0xd5]
+# CHECK: mrs x3, DBGBVR12_EL1
+[0x81,0x0c,0x10,0xd5]
+# CHECK: msr DBGBVR12_EL1, x1
+[0x83,0x0d,0x30,0xd5]
+# CHECK: mrs x3, DBGBVR13_EL1
+[0x81,0x0d,0x10,0xd5]
+# CHECK: msr DBGBVR13_EL1, x1
+[0x83,0x0e,0x30,0xd5]
+# CHECK: mrs x3, DBGBVR14_EL1
+[0x81,0x0e,0x10,0xd5]
+# CHECK: msr DBGBVR14_EL1, x1
+[0x83,0x0f,0x30,0xd5]
+# CHECK: mrs x3, DBGBVR15_EL1
+[0x81,0x0f,0x10,0xd5]
+# CHECK: msr DBGBVR15_EL1, x1
+
+[0xa3,0x00,0x30,0xd5]
+# CHECK: mrs x3, DBGBCR0_EL1
+[0xa1,0x00,0x10,0xd5]
+# CHECK: msr DBGBCR0_EL1, x1
+[0xa3,0x01,0x30,0xd5]
+# CHECK: mrs x3, DBGBCR1_EL1
+[0xa1,0x01,0x10,0xd5]
+# CHECK: msr DBGBCR1_EL1, x1
+[0xa3,0x02,0x30,0xd5]
+# CHECK: mrs x3, DBGBCR2_EL1
+[0xa1,0x02,0x10,0xd5]
+# CHECK: msr DBGBCR2_EL1, x1
+[0xa3,0x03,0x30,0xd5]
+# CHECK: mrs x3, DBGBCR3_EL1
+[0xa1,0x03,0x10,0xd5]
+# CHECK: msr DBGBCR3_EL1, x1
+[0xa3,0x04,0x30,0xd5]
+# CHECK: mrs x3, DBGBCR4_EL1
+[0xa1,0x04,0x10,0xd5]
+# CHECK: msr DBGBCR4_EL1, x1
+[0xa3,0x05,0x30,0xd5]
+# CHECK: mrs x3, DBGBCR5_EL1
+[0xa1,0x05,0x10,0xd5]
+# CHECK: msr DBGBCR5_EL1, x1
+[0xa3,0x06,0x30,0xd5]
+# CHECK: mrs x3, DBGBCR6_EL1
+[0xa1,0x06,0x10,0xd5]
+# CHECK: msr DBGBCR6_EL1, x1
+[0xa3,0x07,0x30,0xd5]
+# CHECK: mrs x3, DBGBCR7_EL1
+[0xa1,0x07,0x10,0xd5]
+# CHECK: msr DBGBCR7_EL1, x1
+[0xa3,0x08,0x30,0xd5]
+# CHECK: mrs x3, DBGBCR8_EL1
+[0xa1,0x08,0x10,0xd5]
+# CHECK: msr DBGBCR8_EL1, x1
+[0xa3,0x09,0x30,0xd5]
+# CHECK: mrs x3, DBGBCR9_EL1
+[0xa1,0x09,0x10,0xd5]
+# CHECK: msr DBGBCR9_EL1, x1
+[0xa3,0x0a,0x30,0xd5]
+# CHECK: mrs x3, DBGBCR10_EL1
+[0xa1,0x0a,0x10,0xd5]
+# CHECK: msr DBGBCR10_EL1, x1
+[0xa3,0x0b,0x30,0xd5]
+# CHECK: mrs x3, DBGBCR11_EL1
+[0xa1,0x0b,0x10,0xd5]
+# CHECK: msr DBGBCR11_EL1, x1
+[0xa3,0x0c,0x30,0xd5]
+# CHECK: mrs x3, DBGBCR12_EL1
+[0xa1,0x0c,0x10,0xd5]
+# CHECK: msr DBGBCR12_EL1, x1
+[0xa3,0x0d,0x30,0xd5]
+# CHECK: mrs x3, DBGBCR13_EL1
+[0xa1,0x0d,0x10,0xd5]
+# CHECK: msr DBGBCR13_EL1, x1
+[0xa3,0x0e,0x30,0xd5]
+# CHECK: mrs x3, DBGBCR14_EL1
+[0xa1,0x0e,0x10,0xd5]
+# CHECK: msr DBGBCR14_EL1, x1
+[0xa3,0x0f,0x30,0xd5]
+# CHECK: mrs x3, DBGBCR15_EL1
+[0xa1,0x0f,0x10,0xd5]
+# CHECK: msr DBGBCR15_EL1, x1
+
+[0xc3,0x00,0x30,0xd5]
+# CHECK: mrs x3, DBGWVR0_EL1
+[0xc1,0x00,0x10,0xd5]
+# CHECK: msr DBGWVR0_EL1, x1
+[0xc3,0x01,0x30,0xd5]
+# CHECK: mrs x3, DBGWVR1_EL1
+[0xc1,0x01,0x10,0xd5]
+# CHECK: msr DBGWVR1_EL1, x1
+[0xc3,0x02,0x30,0xd5]
+# CHECK: mrs x3, DBGWVR2_EL1
+[0xc1,0x02,0x10,0xd5]
+# CHECK: msr DBGWVR2_EL1, x1
+[0xc3,0x03,0x30,0xd5]
+# CHECK: mrs x3, DBGWVR3_EL1
+[0xc1,0x03,0x10,0xd5]
+# CHECK: msr DBGWVR3_EL1, x1
+[0xc3,0x04,0x30,0xd5]
+# CHECK: mrs x3, DBGWVR4_EL1
+[0xc1,0x04,0x10,0xd5]
+# CHECK: msr DBGWVR4_EL1, x1
+[0xc3,0x05,0x30,0xd5]
+# CHECK: mrs x3, DBGWVR5_EL1
+[0xc1,0x05,0x10,0xd5]
+# CHECK: msr DBGWVR5_EL1, x1
+[0xc3,0x06,0x30,0xd5]
+# CHECK: mrs x3, DBGWVR6_EL1
+[0xc1,0x06,0x10,0xd5]
+# CHECK: msr DBGWVR6_EL1, x1
+[0xc3,0x07,0x30,0xd5]
+# CHECK: mrs x3, DBGWVR7_EL1
+[0xc1,0x07,0x10,0xd5]
+# CHECK: msr DBGWVR7_EL1, x1
+[0xc3,0x08,0x30,0xd5]
+# CHECK: mrs x3, DBGWVR8_EL1
+[0xc1,0x08,0x10,0xd5]
+# CHECK: msr DBGWVR8_EL1, x1
+[0xc3,0x09,0x30,0xd5]
+# CHECK: mrs x3, DBGWVR9_EL1
+[0xc1,0x09,0x10,0xd5]
+# CHECK: msr DBGWVR9_EL1, x1
+[0xc3,0x0a,0x30,0xd5]
+# CHECK: mrs x3, DBGWVR10_EL1
+[0xc1,0x0a,0x10,0xd5]
+# CHECK: msr DBGWVR10_EL1, x1
+[0xc3,0x0b,0x30,0xd5]
+# CHECK: mrs x3, DBGWVR11_EL1
+[0xc1,0x0b,0x10,0xd5]
+# CHECK: msr DBGWVR11_EL1, x1
+[0xc3,0x0c,0x30,0xd5]
+# CHECK: mrs x3, DBGWVR12_EL1
+[0xc1,0x0c,0x10,0xd5]
+# CHECK: msr DBGWVR12_EL1, x1
+[0xc3,0x0d,0x30,0xd5]
+# CHECK: mrs x3, DBGWVR13_EL1
+[0xc1,0x0d,0x10,0xd5]
+# CHECK: msr DBGWVR13_EL1, x1
+[0xc3,0x0e,0x30,0xd5]
+# CHECK: mrs x3, DBGWVR14_EL1
+[0xc1,0x0e,0x10,0xd5]
+# CHECK: msr DBGWVR14_EL1, x1
+[0xc3,0x0f,0x30,0xd5]
+# CHECK: mrs x3, DBGWVR15_EL1
+[0xc1,0x0f,0x10,0xd5]
+# CHECK: msr DBGWVR15_EL1, x1
+
+[0xe3,0x00,0x30,0xd5]
+# CHECK: mrs x3, DBGWCR0_EL1
+[0xe1,0x00,0x10,0xd5]
+# CHECK: msr DBGWCR0_EL1, x1
+[0xe3,0x01,0x30,0xd5]
+# CHECK: mrs x3, DBGWCR1_EL1
+[0xe1,0x01,0x10,0xd5]
+# CHECK: msr DBGWCR1_EL1, x1
+[0xe3,0x02,0x30,0xd5]
+# CHECK: mrs x3, DBGWCR2_EL1
+[0xe1,0x02,0x10,0xd5]
+# CHECK: msr DBGWCR2_EL1, x1
+[0xe3,0x03,0x30,0xd5]
+# CHECK: mrs x3, DBGWCR3_EL1
+[0xe1,0x03,0x10,0xd5]
+# CHECK: msr DBGWCR3_EL1, x1
+[0xe3,0x04,0x30,0xd5]
+# CHECK: mrs x3, DBGWCR4_EL1
+[0xe1,0x04,0x10,0xd5]
+# CHECK: msr DBGWCR4_EL1, x1
+[0xe3,0x05,0x30,0xd5]
+# CHECK: mrs x3, DBGWCR5_EL1
+[0xe1,0x05,0x10,0xd5]
+# CHECK: msr DBGWCR5_EL1, x1
+[0xe3,0x06,0x30,0xd5]
+# CHECK: mrs x3, DBGWCR6_EL1
+[0xe1,0x06,0x10,0xd5]
+# CHECK: msr DBGWCR6_EL1, x1
+[0xe3,0x07,0x30,0xd5]
+# CHECK: mrs x3, DBGWCR7_EL1
+[0xe1,0x07,0x10,0xd5]
+# CHECK: msr DBGWCR7_EL1, x1
+[0xe3,0x08,0x30,0xd5]
+# CHECK: mrs x3, DBGWCR8_EL1
+[0xe1,0x08,0x10,0xd5]
+# CHECK: msr DBGWCR8_EL1, x1
+[0xe3,0x09,0x30,0xd5]
+# CHECK: mrs x3, DBGWCR9_EL1
+[0xe1,0x09,0x10,0xd5]
+# CHECK: msr DBGWCR9_EL1, x1
+[0xe3,0x0a,0x30,0xd5]
+# CHECK: mrs x3, DBGWCR10_EL1
+[0xe1,0x0a,0x10,0xd5]
+# CHECK: msr DBGWCR10_EL1, x1
+[0xe3,0x0b,0x30,0xd5]
+# CHECK: mrs x3, DBGWCR11_EL1
+[0xe1,0x0b,0x10,0xd5]
+# CHECK: msr DBGWCR11_EL1, x1
+[0xe3,0x0c,0x30,0xd5]
+# CHECK: mrs x3, DBGWCR12_EL1
+[0xe1,0x0c,0x10,0xd5]
+# CHECK: msr DBGWCR12_EL1, x1
+[0xe3,0x0d,0x30,0xd5]
+# CHECK: mrs x3, DBGWCR13_EL1
+[0xe1,0x0d,0x10,0xd5]
+# CHECK: msr DBGWCR13_EL1, x1
+[0xe3,0x0e,0x30,0xd5]
+# CHECK: mrs x3, DBGWCR14_EL1
+[0xe1,0x0e,0x10,0xd5]
+# CHECK: msr DBGWCR14_EL1, x1
+[0xe3,0x0f,0x30,0xd5]
+# CHECK: mrs x3, DBGWCR15_EL1
+[0xe1,0x0f,0x10,0xd5]
+# CHECK: msr DBGWCR15_EL1, x1
+
+[0x43,0x04,0x30,0xd5]
+# CHECK: mrs x3, MDSELR_EL1
+[0x41,0x04,0x10,0xd5]
+# CHECK: msr MDSELR_EL1, x1
+
+[0x83,0x9e,0x38,0xd5]
+# CHECK: mrs x3, PMUACR_EL1
+[0x81,0x9e,0x18,0xd5]
+# CHECK: msr PMUACR_EL1, x1
+
+[0xe3,0xeb,0x30,0xd5]
+# CHECK: mrs x3, PMCCNTSVR_EL1
+[0x03,0xec,0x30,0xd5]
+# CHECK: mrs x3, PMICNTSVR_EL1
+[0x63,0x9d,0x38,0xd5]
+# CHECK: mrs x3, PMSSCR_EL1
+[0x61,0x9d,0x18,0xd5]
+# CHECK: msr PMSSCR_EL1, x1
+[0x03,0xe8,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR0_EL1
+[0x23,0xe8,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR1_EL1
+[0x43,0xe8,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR2_EL1
+[0x63,0xe8,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR3_EL1
+[0x83,0xe8,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR4_EL1
+[0xa3,0xe8,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR5_EL1
+[0xc3,0xe8,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR6_EL1
+[0xe3,0xe8,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR7_EL1
+[0x03,0xe9,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR8_EL1
+[0x23,0xe9,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR9_EL1
+[0x43,0xe9,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR10_EL1
+[0x63,0xe9,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR11_EL1
+[0x83,0xe9,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR12_EL1
+[0xa3,0xe9,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR13_EL1
+[0xc3,0xe9,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR14_EL1
+[0xe3,0xe9,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR15_EL1
+[0x03,0xea,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR16_EL1
+[0x23,0xea,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR17_EL1
+[0x43,0xea,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR18_EL1
+[0x63,0xea,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR19_EL1
+[0x83,0xea,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR20_EL1
+[0xa3,0xea,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR21_EL1
+[0xc3,0xea,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR22_EL1
+[0xe3,0xea,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR23_EL1
+[0x03,0xeb,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR24_EL1
+[0x23,0xeb,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR25_EL1
+[0x43,0xeb,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR26_EL1
+[0x63,0xeb,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR27_EL1
+[0x83,0xeb,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR28_EL1
+[0xa3,0xeb,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR29_EL1
+[0xc3,0xeb,0x30,0xd5]
+# CHECK: mrs x3, PMEVCNTSVR30_EL1
+
+[0x03,0x94,0x3b,0xd5]
+# CHECK: mrs x3, PMICNTR_EL0
+[0x03,0x94,0x1b,0xd5]
+# CHECK: msr PMICNTR_EL0, x3
+[0x03,0x96,0x3b,0xd5]
+# CHECK: mrs x3, PMICFILTR_EL0
+[0x03,0x96,0x1b,0xd5]
+# CHECK: msr PMICFILTR_EL0, x3
+
+[0x83,0x9d,0x1b,0xd5]
+# CHECK: msr PMZR_EL0, x3
+
+[0xa3,0x9e,0x38,0xd5]
+# CHECK: mrs x3, PMECR_EL1
+[0xa1,0x9e,0x18,0xd5]
+# CHECK: msr PMECR_EL1, x1
+[0xe3,0x9e,0x38,0xd5]
+# CHECK: mrs x3, PMIAR_EL1
+[0xe1,0x9e,0x18,0xd5]
+# CHECK: msr PMIAR_EL1, x1
+
+[0x63,0x9d,0x30,0xd5]
+# CHECK: mrs x3, SPMACCESSR_EL1
+[0x61,0x9d,0x10,0xd5]
+# CHECK: msr SPMACCESSR_EL1, x1
+[0x63,0x9d,0x35,0xd5]
+# CHECK: mrs x3, SPMACCESSR_EL12
+[0x61,0x9d,0x15,0xd5]
+# CHECK: msr SPMACCESSR_EL12, x1
+[0x63,0x9d,0x34,0xd5]
+# CHECK: mrs x3, SPMACCESSR_EL2
+[0x61,0x9d,0x14,0xd5]
+# CHECK: msr SPMACCESSR_EL2, x1
+[0x63,0x9d,0x36,0xd5]
+# CHECK: mrs x3, SPMACCESSR_EL3
+[0x61,0x9d,0x16,0xd5]
+# CHECK: msr SPMACCESSR_EL3, x1
+[0x43,0x9c,0x33,0xd5]
+# CHECK: mrs x3, SPMCNTENCLR_EL0
+[0x41,0x9c,0x13,0xd5]
+# CHECK: msr SPMCNTENCLR_EL0, x1
+[0x23,0x9c,0x33,0xd5]
+# CHECK: mrs x3, SPMCNTENSET_EL0
+[0x21,0x9c,0x13,0xd5]
+# CHECK: msr SPMCNTENSET_EL0, x1
+[0x03,0x9c,0x33,0xd5]
+# CHECK: mrs x3, SPMCR_EL0
+[0x01,0x9c,0x13,0xd5]
+# CHECK: msr SPMCR_EL0, x1
+[0xc3,0x9d,0x30,0xd5]
+# CHECK: mrs x3, SPMDEVAFF_EL1
+[0xa3,0x9d,0x30,0xd5]
+# CHECK: mrs x3, SPMDEVARCH_EL1
+
+[0x03,0xe0,0x33,0xd5]
+# CHECK: mrs x3, SPMEVCNTR0_EL0
+[0x01,0xe0,0x13,0xd5]
+# CHECK: msr SPMEVCNTR0_EL0, x1
+[0x23,0xe0,0x33,0xd5]
+# CHECK: mrs x3, SPMEVCNTR1_EL0
+[0x21,0xe0,0x13,0xd5]
+# CHECK: msr SPMEVCNTR1_EL0, x1
+[0x43,0xe0,0x33,0xd5]
+# CHECK: mrs x3, SPMEVCNTR2_EL0
+[0x41,0xe0,0x13,0xd5]
+# CHECK: msr SPMEVCNTR2_EL0, x1
+[0x63,0xe0,0x33,0xd5]
+# CHECK: mrs x3, SPMEVCNTR3_EL0
+[0x61,0xe0,0x13,0xd5]
+# CHECK: msr SPMEVCNTR3_EL0, x1
+[0x83,0xe0,0x33,0xd5]
+# CHECK: mrs x3, SPMEVCNTR4_EL0
+[0x81,0xe0,0x13,0xd5]
+# CHECK: msr SPMEVCNTR4_EL0, x1
+[0xa3,0xe0,0x33,0xd5]
+# CHECK: mrs x3, SPMEVCNTR5_EL0
+[0xa1,0xe0,0x13,0xd5]
+# CHECK: msr SPMEVCNTR5_EL0, x1
+[0xc3,0xe0,0x33,0xd5]
+# CHECK: mrs x3, SPMEVCNTR6_EL0
+[0xc1,0xe0,0x13,0xd5]
+# CHECK: msr SPMEVCNTR6_EL0, x1
+[0xe3,0xe0,0x33,0xd5]
+# CHECK: mrs x3, SPMEVCNTR7_EL0
+[0xe1,0xe0,0x13,0xd5]
+# CHECK: msr SPMEVCNTR7_EL0, x1
+[0x03,0xe1,0x33,0xd5]
+# CHECK: mrs x3, SPMEVCNTR8_EL0
+[0x01,0xe1,0x13,0xd5]
+# CHECK: msr SPMEVCNTR8_EL0, x1
+[0x23,0xe1,0x33,0xd5]
+# CHECK: mrs x3, SPMEVCNTR9_EL0
+[0x21,0xe1,0x13,0xd5]
+# CHECK: msr SPMEVCNTR9_EL0, x1
+[0x43,0xe1,0x33,0xd5]
+# CHECK: mrs x3, SPMEVCNTR10_EL0
+[0x41,0xe1,0x13,0xd5]
+# CHECK: msr SPMEVCNTR10_EL0, x1
+[0x63,0xe1,0x33,0xd5]
+# CHECK: mrs x3, SPMEVCNTR11_EL0
+[0x61,0xe1,0x13,0xd5]
+# CHECK: msr SPMEVCNTR11_EL0, x1
+[0x83,0xe1,0x33,0xd5]
+# CHECK: mrs x3, SPMEVCNTR12_EL0
+[0x81,0xe1,0x13,0xd5]
+# CHECK: msr SPMEVCNTR12_EL0, x1
+[0xa3,0xe1,0x33,0xd5]
+# CHECK: mrs x3, SPMEVCNTR13_EL0
+[0xa1,0xe1,0x13,0xd5]
+# CHECK: msr SPMEVCNTR13_EL0, x1
+[0xc3,0xe1,0x33,0xd5]
+# CHECK: mrs x3, SPMEVCNTR14_EL0
+[0xc1,0xe1,0x13,0xd5]
+# CHECK: msr SPMEVCNTR14_EL0, x1
+[0xe3,0xe1,0x33,0xd5]
+# CHECK: mrs x3, SPMEVCNTR15_EL0
+[0xe1,0xe1,0x13,0xd5]
+# CHECK: msr SPMEVCNTR15_EL0, x1
+
+[0x03,0xe6,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILT2R0_EL0
+[0x01,0xe6,0x13,0xd5]
+# CHECK: msr SPMEVFILT2R0_EL0, x1
+[0x23,0xe6,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILT2R1_EL0
+[0x21,0xe6,0x13,0xd5]
+# CHECK: msr SPMEVFILT2R1_EL0, x1
+[0x43,0xe6,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILT2R2_EL0
+[0x41,0xe6,0x13,0xd5]
+# CHECK: msr SPMEVFILT2R2_EL0, x1
+[0x63,0xe6,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILT2R3_EL0
+[0x61,0xe6,0x13,0xd5]
+# CHECK: msr SPMEVFILT2R3_EL0, x1
+[0x83,0xe6,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILT2R4_EL0
+[0x81,0xe6,0x13,0xd5]
+# CHECK: msr SPMEVFILT2R4_EL0, x1
+[0xa3,0xe6,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILT2R5_EL0
+[0xa1,0xe6,0x13,0xd5]
+# CHECK: msr SPMEVFILT2R5_EL0, x1
+[0xc3,0xe6,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILT2R6_EL0
+[0xc1,0xe6,0x13,0xd5]
+# CHECK: msr SPMEVFILT2R6_EL0, x1
+[0xe3,0xe6,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILT2R7_EL0
+[0xe1,0xe6,0x13,0xd5]
+# CHECK: msr SPMEVFILT2R7_EL0, x1
+[0x03,0xe7,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILT2R8_EL0
+[0x01,0xe7,0x13,0xd5]
+# CHECK: msr SPMEVFILT2R8_EL0, x1
+[0x23,0xe7,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILT2R9_EL0
+[0x21,0xe7,0x13,0xd5]
+# CHECK: msr SPMEVFILT2R9_EL0, x1
+[0x43,0xe7,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILT2R10_EL0
+[0x41,0xe7,0x13,0xd5]
+# CHECK: msr SPMEVFILT2R10_EL0, x1
+[0x63,0xe7,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILT2R11_EL0
+[0x61,0xe7,0x13,0xd5]
+# CHECK: msr SPMEVFILT2R11_EL0, x1
+[0x83,0xe7,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILT2R12_EL0
+[0x81,0xe7,0x13,0xd5]
+# CHECK: msr SPMEVFILT2R12_EL0, x1
+[0xa3,0xe7,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILT2R13_EL0
+[0xa1,0xe7,0x13,0xd5]
+# CHECK: msr SPMEVFILT2R13_EL0, x1
+[0xc3,0xe7,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILT2R14_EL0
+[0xc1,0xe7,0x13,0xd5]
+# CHECK: msr SPMEVFILT2R14_EL0, x1
+[0xe3,0xe7,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILT2R15_EL0
+[0xe1,0xe7,0x13,0xd5]
+# CHECK: msr SPMEVFILT2R15_EL0, x1
+
+[0x03,0xe4,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILTR0_EL0
+[0x01,0xe4,0x13,0xd5]
+# CHECK: msr SPMEVFILTR0_EL0, x1
+[0x23,0xe4,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILTR1_EL0
+[0x21,0xe4,0x13,0xd5]
+# CHECK: msr SPMEVFILTR1_EL0, x1
+[0x43,0xe4,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILTR2_EL0
+[0x41,0xe4,0x13,0xd5]
+# CHECK: msr SPMEVFILTR2_EL0, x1
+[0x63,0xe4,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILTR3_EL0
+[0x61,0xe4,0x13,0xd5]
+# CHECK: msr SPMEVFILTR3_EL0, x1
+[0x83,0xe4,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILTR4_EL0
+[0x81,0xe4,0x13,0xd5]
+# CHECK: msr SPMEVFILTR4_EL0, x1
+[0xa3,0xe4,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILTR5_EL0
+[0xa1,0xe4,0x13,0xd5]
+# CHECK: msr SPMEVFILTR5_EL0, x1
+[0xc3,0xe4,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILTR6_EL0
+[0xc1,0xe4,0x13,0xd5]
+# CHECK: msr SPMEVFILTR6_EL0, x1
+[0xe3,0xe4,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILTR7_EL0
+[0xe1,0xe4,0x13,0xd5]
+# CHECK: msr SPMEVFILTR7_EL0, x1
+[0x03,0xe5,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILTR8_EL0
+[0x01,0xe5,0x13,0xd5]
+# CHECK: msr SPMEVFILTR8_EL0, x1
+[0x23,0xe5,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILTR9_EL0
+[0x21,0xe5,0x13,0xd5]
+# CHECK: msr SPMEVFILTR9_EL0, x1
+[0x43,0xe5,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILTR10_EL0
+[0x41,0xe5,0x13,0xd5]
+# CHECK: msr SPMEVFILTR10_EL0, x1
+[0x63,0xe5,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILTR11_EL0
+[0x61,0xe5,0x13,0xd5]
+# CHECK: msr SPMEVFILTR11_EL0, x1
+[0x83,0xe5,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILTR12_EL0
+[0x81,0xe5,0x13,0xd5]
+# CHECK: msr SPMEVFILTR12_EL0, x1
+[0xa3,0xe5,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILTR13_EL0
+[0xa1,0xe5,0x13,0xd5]
+# CHECK: msr SPMEVFILTR13_EL0, x1
+[0xc3,0xe5,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILTR14_EL0
+[0xc1,0xe5,0x13,0xd5]
+# CHECK: msr SPMEVFILTR14_EL0, x1
+[0xe3,0xe5,0x33,0xd5]
+# CHECK: mrs x3, SPMEVFILTR15_EL0
+[0xe1,0xe5,0x13,0xd5]
+# CHECK: msr SPMEVFILTR15_EL0, x1
+
+[0x03,0xe2,0x33,0xd5]
+# CHECK: mrs x3, SPMEVTYPER0_EL0
+[0x01,0xe2,0x13,0xd5]
+# CHECK: msr SPMEVTYPER0_EL0, x1
+[0x23,0xe2,0x33,0xd5]
+# CHECK: mrs x3, SPMEVTYPER1_EL0
+[0x21,0xe2,0x13,0xd5]
+# CHECK: msr SPMEVTYPER1_EL0, x1
+[0x43,0xe2,0x33,0xd5]
+# CHECK: mrs x3, SPMEVTYPER2_EL0
+[0x41,0xe2,0x13,0xd5]
+# CHECK: msr SPMEVTYPER2_EL0, x1
+[0x63,0xe2,0x33,0xd5]
+# CHECK: mrs x3, SPMEVTYPER3_EL0
+[0x61,0xe2,0x13,0xd5]
+# CHECK: msr SPMEVTYPER3_EL0, x1
+[0x83,0xe2,0x33,0xd5]
+# CHECK: mrs x3, SPMEVTYPER4_EL0
+[0x81,0xe2,0x13,0xd5]
+# CHECK: msr SPMEVTYPER4_EL0, x1
+[0xa3,0xe2,0x33,0xd5]
+# CHECK: mrs x3, SPMEVTYPER5_EL0
+[0xa1,0xe2,0x13,0xd5]
+# CHECK: msr SPMEVTYPER5_EL0, x1
+[0xc3,0xe2,0x33,0xd5]
+# CHECK: mrs x3, SPMEVTYPER6_EL0
+[0xc1,0xe2,0x13,0xd5]
+# CHECK: msr SPMEVTYPER6_EL0, x1
+[0xe3,0xe2,0x33,0xd5]
+# CHECK: mrs x3, SPMEVTYPER7_EL0
+[0xe1,0xe2,0x13,0xd5]
+# CHECK: msr SPMEVTYPER7_EL0, x1
+[0x03,0xe3,0x33,0xd5]
+# CHECK: mrs x3, SPMEVTYPER8_EL0
+[0x01,0xe3,0x13,0xd5]
+# CHECK: msr SPMEVTYPER8_EL0, x1
+[0x23,0xe3,0x33,0xd5]
+# CHECK: mrs x3, SPMEVTYPER9_EL0
+[0x21,0xe3,0x13,0xd5]
+# CHECK: msr SPMEVTYPER9_EL0, x1
+[0x43,0xe3,0x33,0xd5]
+# CHECK: mrs x3, SPMEVTYPER10_EL0
+[0x41,0xe3,0x13,0xd5]
+# CHECK: msr SPMEVTYPER10_EL0, x1
+[0x63,0xe3,0x33,0xd5]
+# CHECK: mrs x3, SPMEVTYPER11_EL0
+[0x61,0xe3,0x13,0xd5]
+# CHECK: msr SPMEVTYPER11_EL0, x1
+[0x83,0xe3,0x33,0xd5]
+# CHECK: mrs x3, SPMEVTYPER12_EL0
+[0x81,0xe3,0x13,0xd5]
+# CHECK: msr SPMEVTYPER12_EL0, x1
+[0xa3,0xe3,0x33,0xd5]
+# CHECK: mrs x3, SPMEVTYPER13_EL0
+[0xa1,0xe3,0x13,0xd5]
+# CHECK: msr SPMEVTYPER13_EL0, x1
+[0xc3,0xe3,0x33,0xd5]
+# CHECK: mrs x3, SPMEVTYPER14_EL0
+[0xc1,0xe3,0x13,0xd5]
+# CHECK: msr SPMEVTYPER14_EL0, x1
+[0xe3,0xe3,0x33,0xd5]
+# CHECK: mrs x3, SPMEVTYPER15_EL0
+[0xe1,0xe3,0x13,0xd5]
+# CHECK: msr SPMEVTYPER15_EL0, x1
+
+[0x83,0x9d,0x30,0xd5]
+# CHECK: mrs x3, SPMIIDR_EL1
+[0x43,0x9e,0x30,0xd5]
+# CHECK: mrs x3, SPMINTENCLR_EL1
+[0x41,0x9e,0x10,0xd5]
+# CHECK: msr SPMINTENCLR_EL1, x1
+[0x23,0x9e,0x30,0xd5]
+# CHECK: mrs x3, SPMINTENSET_EL1
+[0x21,0x9e,0x10,0xd5]
+# CHECK: msr SPMINTENSET_EL1, x1
+[0x63,0x9c,0x33,0xd5]
+# CHECK: mrs x3, SPMOVSCLR_EL0
+[0x61,0x9c,0x13,0xd5]
+# CHECK: msr SPMOVSCLR_EL0, x1
+[0x63,0x9e,0x33,0xd5]
+# CHECK: mrs x3, SPMOVSSET_EL0
+[0x61,0x9e,0x13,0xd5]
+# CHECK: msr SPMOVSSET_EL0, x1
+[0xa3,0x9c,0x33,0xd5]
+# CHECK: mrs x3, SPMSELR_EL0
+[0xa1,0x9c,0x13,0xd5]
+# CHECK: msr SPMSELR_EL0, x1
+[0x03,0x9d,0x30,0xd5]
+# CHECK: mrs x3, SPMCGCR0_EL1
+[0x23,0x9d,0x30,0xd5]
+# CHECK: mrs x3, SPMCGCR1_EL1
+[0xe3,0x9d,0x30,0xd5]
+# CHECK: mrs x3, SPMCFGR_EL1
+[0xe3,0x9e,0x36,0xd5]
+# CHECK: mrs x3, SPMROOTCR_EL3
+[0xe3,0x9e,0x16,0xd5]
+# CHECK: msr SPMROOTCR_EL3, x3
+[0xe3,0x9e,0x37,0xd5]
+# CHECK: mrs x3, SPMSCR_EL1
+[0xe3,0x9e,0x17,0xd5]
+# CHECK: msr SPMSCR_EL1, x3
+
+[0x63,0x12,0x38,0xd5]
+# CHECK: mrs x3, TRCITECR_EL1
+# ERROR-NO-ITE: mrs x3, S3_0_C1_C2_3
+[0x61,0x12,0x18,0xd5]
+# CHECK: msr TRCITECR_EL1, x1
+# ERROR-NO-ITE: msr S3_0_C1_C2_3, x1
+[0x63,0x12,0x3d,0xd5]
+# CHECK: mrs x3, TRCITECR_EL12
+# ERROR-NO-ITE: mrs x3, S3_5_C1_C2_3
+[0x61,0x12,0x1d,0xd5]
+# CHECK: msr TRCITECR_EL12, x1
+# ERROR-NO-ITE: msr S3_5_C1_C2_3, x1
+[0x63,0x12,0x3c,0xd5]
+# CHECK: mrs x3, TRCITECR_EL2
+# ERROR-NO-ITE: mrs x3, S3_4_C1_C2_3
+[0x61,0x12,0x1c,0xd5]
+# CHECK: msr TRCITECR_EL2, x1
+# ERROR-NO-ITE: msr S3_4_C1_C2_3, x1
+[0xe1,0x72,0x0b,0xd5]
+# CHECK: trcit x1
+# ERROR-NO-ITE: sys #3, c7, c2, #7, x1
+
+[0x83,0x9a,0x38,0xd5]
+# CHECK: mrs x3, PMSDSFR_EL1
+[0x83,0x9a,0x18,0xd5]
+# CHECK: msr PMSDSFR_EL1, x3
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