[PATCH] D138570: [AArch64] Add patterns for SVE predicated add/sub and mov combine

[Nicola Lancellotti via Phabricator via llvm-commits]

NicolaLancellotti marked an inline comment as done.
NicolaLancellotti added a comment.

In D138570#3949132 <https://reviews.llvm.org/D138570#3949132>, @dmgreen wrote:

> I think the H/S/D should be 255 too, according to https://godbolt.org/z/zcYcdGjfh. It looks like it's a 8bit encoding, that gets treated as a signed value so 255 becomes -1.

You are right. Done.


Repository:
  rG LLVM Github Monorepo

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