[PATCH] D138656: [CodeGen] Additional Register argument to storeRegToStackSlot/loadRegFromStackSlot

[Christudasan Devadasan via Phabricator via llvm-commits]

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With D134950 <https://reviews.llvm.org/D134950>, targets get notified when a virtual register is created and/or
cloned. Targets can do the needful with the delegate callback. AMDGPU propagates
the virtual register flags maintained in the target file itself. They are useful
to identify a certain type of machine operands while inserting spill stores and
reloads. Since RegAllocFast spills the physical register itself, there is no way
its virtual register can be mapped back to retrieve the flags. It can be solved
by passing the virtual register as an additional argument. This argument has no
use when the spill interfaces are called during the greedy allocator or even the
PrologEpilogInserter and can pass a null register in such cases.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138656

Files:
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
  llvm/lib/CodeGen/InlineSpiller.cpp
  llvm/lib/CodeGen/PrologEpilogInserter.cpp
  llvm/lib/CodeGen/RegAllocFast.cpp
  llvm/lib/CodeGen/RegisterScavenging.cpp
  llvm/lib/CodeGen/TargetInstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.h
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
  llvm/lib/Target/ARC/ARCInstrInfo.cpp
  llvm/lib/Target/ARC/ARCInstrInfo.h
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.h
  llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
  llvm/lib/Target/ARM/Thumb1InstrInfo.h
  llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
  llvm/lib/Target/ARM/Thumb2InstrInfo.h
  llvm/lib/Target/AVR/AVRInstrInfo.cpp
  llvm/lib/Target/AVR/AVRInstrInfo.h
  llvm/lib/Target/BPF/BPFInstrInfo.cpp
  llvm/lib/Target/BPF/BPFInstrInfo.h
  llvm/lib/Target/CSKY/CSKYFrameLowering.cpp
  llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
  llvm/lib/Target/CSKY/CSKYInstrInfo.h
  llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
  llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
  llvm/lib/Target/Hexagon/HexagonInstrInfo.h
  llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
  llvm/lib/Target/Lanai/LanaiInstrInfo.h
  llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
  llvm/lib/Target/M68k/M68kFrameLowering.h
  llvm/lib/Target/M68k/M68kInstrInfo.cpp
  llvm/lib/Target/M68k/M68kInstrInfo.h
  llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
  llvm/lib/Target/MSP430/MSP430InstrInfo.h
  llvm/lib/Target/Mips/MipsInstrInfo.h
  llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
  llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
  llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.h
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/lib/Target/Sparc/SparcInstrInfo.cpp
  llvm/lib/Target/Sparc/SparcInstrInfo.h
  llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
  llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
  llvm/lib/Target/SystemZ/SystemZInstrInfo.h
  llvm/lib/Target/VE/VEInstrInfo.cpp
  llvm/lib/Target/VE/VEInstrInfo.h
  llvm/lib/Target/X86/X86FastPreTileConfig.cpp
  llvm/lib/Target/X86/X86FrameLowering.cpp
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstrInfo.h
  llvm/lib/Target/XCore/XCoreFrameLowering.cpp
  llvm/lib/Target/XCore/XCoreInstrInfo.cpp
  llvm/lib/Target/XCore/XCoreInstrInfo.h

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