[PATCH] D138639: [X86] Add In64BitMode for MOVSX64/MOVZX64 instructions

[Haohai, Wen via Phabricator via llvm-commits]

HaohaiWen added a comment.

> Are you seeing a functional issue that this fixes?

I'm fixing a AlderlakeP schedmodel issue: https://github.com/llvm/llvm-project/issues/58792.
To fix it, I need to use AsmMatcherEmitter to match CodeGenOnly but encodable instructions like CVTSD2SI64rm_Int.
This trigged assertion in X86AsmParser::validateInstruction:

  if (UsesRex && HReg != X86::NoRegister) {
    StringRef RegName = X86IntelInstPrinter::getRegisterName(HReg);
    return Error(Ops[0]->getStartLoc(),
                 "can't encode '" + RegName + "' in an instruction requiring "
                 "REX prefix");
  }

By validating hasREX_W and predicates in tblgen, I found there're 245 instructions has REX_W prefix but without In64BitMode predicate.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D138639/new/

https://reviews.llvm.org/D138639