[PATCH] D138636: [LSR] Hoist IVInc to loop header if its all uses are in the loop header

[chenglin.bi via Phabricator via llvm-commits]

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When the latch block is different from header block, IVInc will be expanded in the latch loop. We can't generate the post index load/store this case.
But if the IVInc only used in the loop, actually we still can use the post index load/store because when exit loop we don't care the last IVInc value.
So, trying to hoist IVInc to help backend to generate more post index load/store.

Fix #53625


https://reviews.llvm.org/D138636

Files:
  llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
  llvm/test/Transforms/LoopStrengthReduce/AArch64/pr53625.ll

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