[llvm] 0dbc52a - Add MC support of RISCV Zcd Extension
via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 23 13:48:11 PST 2022
Author: WuXinlong
Date: 2022-11-24T05:48:06+08:00
New Revision: 0dbc52a0ab3c2b32f729e985d62401ce9bd9853e
URL: https://github.com/llvm/llvm-project/commit/0dbc52a0ab3c2b32f729e985d62401ce9bd9853e
DIFF: https://github.com/llvm/llvm-project/commit/0dbc52a0ab3c2b32f729e985d62401ce9bd9853e.diff
LOG: Add MC support of RISCV Zcd Extension
This patch add the instructions of Zcd extension.
Zcd is a subset of C Ext which include the double-precision floating-point instructions (c.fld, c.fldsp, c.fsd, c.fsdsp).
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D134177
Added:
Modified:
clang/test/Preprocessor/riscv-target-features.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoC.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/MC/RISCV/compress-rv32d.s
llvm/test/MC/RISCV/rv32dc-valid.s
llvm/test/MC/RISCV/rv64dc-valid.s
Removed:
################################################################################
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index 6ad45a5e443fd..c01e4b15f07be 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -42,6 +42,7 @@
// CHECK-NOT: __riscv_svnapot
// CHECK-NOT: __riscv_svinval
// CHECK-NOT: __riscv_xventanacondops
+// CHECK-NOT: __riscv_zcd
// CHECK-NOT: __riscv_zcf
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
@@ -439,6 +440,12 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s
// CHECK-XVENTANACONDOPS-EXT: __riscv_xventanacondops 1000000{{$}}
+// RUN: %clang -target riscv32 -march=rv32izcd0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s
+// RUN: %clang -target riscv64 -march=rv64izcd0p70 -menable-experimental-extensions \
+// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s
+// CHECK-ZCD-EXT: __riscv_zcd 70000{{$}}
+
// RUN: %clang -target riscv32 -march=rv32izcf0p70 -menable-experimental-extensions \
// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCF-EXT %s
// CHECK-ZCF-EXT: __riscv_zcf 70000{{$}}
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 3fe54c62b7953..fe9cc4c5d0f91 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -111,6 +111,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zihintntl", RISCVExtensionVersion{0, 2}},
{"zca", RISCVExtensionVersion{0, 70}},
+ {"zcd", RISCVExtensionVersion{0, 70}},
{"zcf", RISCVExtensionVersion{0, 70}},
{"zvfh", RISCVExtensionVersion{0, 1}},
{"zawrs", RISCVExtensionVersion{1, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index f981f87d41d6b..3f42886acc527 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -292,6 +292,16 @@ def HasStdExtCOrZca
"'Zca' (part of the C extension, excluding "
"compressed floating point loads/stores)">;
+def FeatureExtZcd
+ : SubtargetFeature<"experimental-zcd", "HasStdExtZcd", "true",
+ "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
+
+def HasStdExtCOrZcd
+ : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">,
+ AssemblerPredicate<(any_of FeatureStdExtC, FeatureExtZcd),
+ "'C' (Compressed Instructions) or "
+ "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
+
def FeatureExtZcf
: SubtargetFeature<"experimental-zcf", "HasStdExtZcf", "true",
"'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index 247e1b4b2e354..26a16d099e862 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -311,7 +311,7 @@ def C_ADDI4SPN : RVInst16CIW<0b000, 0b00, (outs GPRC:$rd),
let Inst{5} = imm{3};
}
-let Predicates = [HasStdExtC, HasStdExtD] in
+let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
def C_FLD : CLoad_ri<0b001, "c.fld", FPR64C, uimm8_lsb000>,
Sched<[WriteFLD64, ReadMemBase]> {
bits<8> imm;
@@ -345,7 +345,7 @@ def C_LD : CLoad_ri<0b011, "c.ld", GPRC, uimm8_lsb000>,
let Inst{6-5} = imm{7-6};
}
-let Predicates = [HasStdExtC, HasStdExtD] in
+let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
def C_FSD : CStore_rri<0b101, "c.fsd", FPR64C, uimm8_lsb000>,
Sched<[WriteFST64, ReadStoreData, ReadMemBase]> {
bits<8> imm;
@@ -501,7 +501,7 @@ def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb),
let Inst{6-2} = imm{4-0};
}
-let Predicates = [HasStdExtC, HasStdExtD] in
+let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
def C_FLDSP : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000>,
Sched<[WriteFLD64, ReadMemBase]> {
let Inst{6-5} = imm{4-3};
@@ -561,7 +561,7 @@ def C_ADD : RVInst16CR<0b1001, 0b10, (outs GPRNoX0:$rs1_wb),
let Constraints = "$rs1 = $rs1_wb";
}
-let Predicates = [HasStdExtC, HasStdExtD] in
+let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
def C_FSDSP : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000>,
Sched<[WriteFST64, ReadStoreData, ReadMemBase]> {
let Inst{12-10} = imm{5-3};
@@ -740,7 +740,7 @@ def : InstAlias<"c.flwsp $rd, (${rs1})", (C_FLWSP FPR32C:$rd, SPMem:$rs1, 0)>;
def : InstAlias<"c.fswsp $rs2, (${rs1})", (C_FSWSP FPR32C:$rs2, SPMem:$rs1, 0)>;
}
-let Predicates = [HasStdExtC, HasStdExtD] in {
+let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
def : InstAlias<"c.fld $rd, (${rs1})", (C_FLD FPR64C:$rd, GPRCMem:$rs1, 0)>;
def : InstAlias<"c.fsd $rs2, (${rs1})", (C_FSD FPR64C:$rs2, GPRCMem:$rs1, 0)>;
def : InstAlias<"c.fldsp $rd, (${rs1})", (C_FLDSP FPR64C:$rd, SPMem:$rs1, 0)>;
@@ -761,10 +761,10 @@ def : CompressPat<(ADDI GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm),
(C_ADDI4SPN GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm)>;
} // Predicates = [HasStdExtCOrZca]
-let Predicates = [HasStdExtC, HasStdExtD] in {
+let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
def : CompressPat<(FLD FPR64C:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm),
(C_FLD FPR64C:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm)>;
-} // Predicates = [HasStdExtC, HasStdExtD]
+} // Predicates = [HasStdExtCOrZcd, HasStdExtD]
let Predicates = [HasStdExtCOrZca] in {
def : CompressPat<(LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
@@ -781,10 +781,10 @@ def : CompressPat<(LD GPRC:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm),
(C_LD GPRC:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm)>;
} // Predicates = [HasStdExtCOrZca, IsRV64]
-let Predicates = [HasStdExtC, HasStdExtD] in {
+let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
def : CompressPat<(FSD FPR64C:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm),
(C_FSD FPR64C:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm)>;
-} // Predicates = [HasStdExtC, HasStdExtD]
+} // Predicates = [HasStdExtCOrZcd, HasStdExtD]
let Predicates = [HasStdExtCOrZca] in {
def : CompressPat<(SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
@@ -878,10 +878,10 @@ def : CompressPat<(SLLI GPRNoX0:$rs1, GPRNoX0:$rs1, uimmlog2xlennonzero:$imm),
(C_SLLI GPRNoX0:$rs1, uimmlog2xlennonzero:$imm)>;
} // Predicates = [HasStdExtCOrZca]
-let Predicates = [HasStdExtC, HasStdExtD] in {
+let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
def : CompressPat<(FLD FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm),
(C_FLDSP FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm)>;
-} // Predicates = [HasStdExtC, HasStdExtD]
+} // Predicates = [HasStdExtCOrZcd, HasStdExtD]
let Predicates = [HasStdExtCOrZca] in {
def : CompressPat<(LW GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
@@ -920,10 +920,10 @@ def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs1),
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
} // Predicates = [HasStdExtCOrZca]
-let Predicates = [HasStdExtC, HasStdExtD] in {
+let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
def : CompressPat<(FSD FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm),
(C_FSDSP FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm)>;
-} // Predicates = [HasStdExtC, HasStdExtD]
+} // Predicates = [HasStdExtCOrZcd, HasStdExtD]
let Predicates = [HasStdExtCOrZca] in {
def : CompressPat<(SW GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 066ad3f550553..ddfbea7b04748 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -56,6 +56,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool HasStdExtZbc = false;
bool HasStdExtZbs = false;
bool HasStdExtZca = false;
+ bool HasStdExtZcd = false;
bool HasStdExtZcf = false;
bool HasStdExtV = false;
bool HasStdExtZve32x = false;
@@ -168,6 +169,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool hasStdExtZbc() const { return HasStdExtZbc; }
bool hasStdExtZbs() const { return HasStdExtZbs; }
bool hasStdExtZca() const { return HasStdExtZca; }
+ bool hasStdExtZcd() const { return HasStdExtZcd; }
bool hasStdExtZcf() const { return HasStdExtZcf; }
bool hasStdExtZvl() const { return ZvlLen != 0; }
bool hasStdExtZvfh() const { return HasStdExtZvfh; }
diff --git a/llvm/test/MC/RISCV/compress-rv32d.s b/llvm/test/MC/RISCV/compress-rv32d.s
index 029cea7a227a3..2b2fc13589dea 100644
--- a/llvm/test/MC/RISCV/compress-rv32d.s
+++ b/llvm/test/MC/RISCV/compress-rv32d.s
@@ -8,6 +8,16 @@
# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -filetype=obj < %s \
# RUN: | llvm-objdump --triple=riscv32 --mattr=+c,+d -d -M no-aliases - \
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
+# RUN: llvm-mc -triple riscv32 -mattr=+experimental-zcd,+d -show-encoding < %s \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv32 -mattr=+experimental-zcd,+d -show-encoding \
+# RUN: -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -triple riscv32 -mattr=+experimental-zcd,+d -filetype=obj < %s \
+# RUN: | llvm-objdump --triple=riscv32 --mattr=+experimental-zcd,+d -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv32 -mattr=+experimental-zcd,+d -filetype=obj < %s \
+# RUN: | llvm-objdump --triple=riscv32 --mattr=+experimental-zcd,+d -d -M no-aliases - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -show-encoding < %s \
# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
@@ -19,6 +29,16 @@
# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -filetype=obj < %s \
# RUN: | llvm-objdump --triple=riscv64 --mattr=+c,+d -d -M no-aliases - \
# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
+# RUN: llvm-mc -triple riscv64 -mattr=+experimental-zcd,+d -show-encoding < %s \
+# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv64 -mattr=+experimental-zcd,+d -show-encoding \
+# RUN: -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK-INST %s
+# RUN: llvm-mc -triple riscv64 -mattr=+experimental-zcd,+d -filetype=obj < %s \
+# RUN: | llvm-objdump --triple=riscv64 --mattr=+experimental-zcd,+d -d - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
+# RUN: llvm-mc -triple riscv64 -mattr=+experimental-zcd,+d -filetype=obj < %s \
+# RUN: | llvm-objdump --triple=riscv64 --mattr=+experimental-zcd,+d -d -M no-aliases - \
+# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
# Tests double precision floating point instructions available in rv32 and in rv64.
diff --git a/llvm/test/MC/RISCV/rv32dc-valid.s b/llvm/test/MC/RISCV/rv32dc-valid.s
index c37b53b08cc5f..804871f17660c 100644
--- a/llvm/test/MC/RISCV/rv32dc-valid.s
+++ b/llvm/test/MC/RISCV/rv32dc-valid.s
@@ -3,31 +3,39 @@
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c,+d < %s \
# RUN: | llvm-objdump --mattr=+c,+d -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zcd,+d -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zcd,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zcd,+d -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
#
# RUN: not llvm-mc -triple riscv32 -mattr=+c \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-D %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zcd \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-D %s
# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-DC %s
# CHECK-ASM-AND-OBJ: c.fldsp fs0, 504(sp)
# CHECK-ASM: encoding: [0x7e,0x34]
# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}}
+# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}}
c.fldsp fs0, 504(sp)
# CHECK-ASM-AND-OBJ: c.fsdsp fa7, 504(sp)
# CHECK-ASM: encoding: [0xc6,0xbf]
# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}}
+# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}}
c.fsdsp fa7, 504(sp)
# CHECK-ASM-AND-OBJ: c.fld fa3, 248(a5)
# CHECK-ASM: encoding: [0xf4,0x3f]
# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}}
+# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}}
c.fld fa3, 248(a5)
# CHECK-ASM-AND-OBJ: c.fsd fa2, 248(a1)
# CHECK-ASM: encoding: [0xf0,0xbd]
# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}}
+# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}}
c.fsd fa2, 248(a1)
diff --git a/llvm/test/MC/RISCV/rv64dc-valid.s b/llvm/test/MC/RISCV/rv64dc-valid.s
index ccb789145bf78..7f39fa9d77797 100644
--- a/llvm/test/MC/RISCV/rv64dc-valid.s
+++ b/llvm/test/MC/RISCV/rv64dc-valid.s
@@ -3,31 +3,39 @@
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+d < %s \
# RUN: | llvm-objdump --mattr=+c,+d -M no-aliases -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zcd,+d -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zcd,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zcd,+d -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
#
# RUN: not llvm-mc -triple riscv64 -mattr=+c \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-D %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zcd \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-D %s
# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-DC %s
# CHECK-ASM-AND-OBJ: c.fldsp fs0, 504(sp)
# CHECK-ASM: encoding: [0x7e,0x34]
# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}}
+# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}}
c.fldsp fs0, 504(sp)
# CHECK-ASM-AND-OBJ: c.fsdsp fa7, 504(sp)
# CHECK-ASM: encoding: [0xc6,0xbf]
# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}}
+# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}}
c.fsdsp fa7, 504(sp)
# CHECK-ASM-AND-OBJ: c.fld fa3, 248(a5)
# CHECK-ASM: encoding: [0xf4,0x3f]
# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}}
+# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}}
c.fld fa3, 248(a5)
# CHECK-ASM-AND-OBJ: c.fsd fa2, 248(a1)
# CHECK-ASM: encoding: [0xf0,0xbd]
# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}}
+# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}}
c.fsd fa2, 248(a1)
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